[ADS5121] Support for the ADS5121 board

The following MPC5121e subsystems are supported:

- low-level CPU init
- NOR Boot Flash (common CFI driver)
- DDR SDRAM
- FEC
- I2C
- Watchdog

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
Signed-off-by: Jan Wrobel <wrr@semihalf.com>

6 files changed, 1389 insertions, 1 deletions

diff --git a/include/asm-ppc/e300.h b/include/asm-ppc/e300.h
index d1bb159..de82399 100644
--- a/include/asm-ppc/e300.h
+++ b/include/asm-ppc/e300.h
@@ -9,6 +9,7 @@
 #define PVR_E300C1	0x80830000
 #define PVR_E300C2	0x80840000
 #define PVR_E300C3	0x80850000
+#define PVR_E300C4	0x80860000
 
 /*
  * Hardware Implementation-Dependent Register 0 (HID0)
diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index cd24636..bbaeb3f 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -85,6 +85,10 @@ typedef	struct	global_data {
 	unsigned long	ipb_clk;
 	unsigned long	pci_clk;
 #endif
+#if defined(CONFIG_MPC512X)
+	u32 ipb_clk;
+	u32 csb_clk;
+#endif /* CONFIG_MPC512X */
 #if defined(CONFIG_MPC8220)
 	unsigned long   bExtUart;
 	unsigned long   inp_clk;
diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h
new file mode 100644
index 0000000..23d10d4
--- /dev/null
+++ b/include/asm-ppc/immap_512x.h
@@ -0,0 +1,569 @@
+/*
+ * (C) Copyright 2007 DENX Software Engineering
+ *
+ * MPC512x Internal Memory Map
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Based on the MPC83xx header.
+ */
+
+#ifndef __IMMAP_512x__
+#define __IMMAP_512x__
+
+#include <asm/types.h>
+
+typedef struct law512x {
+	u32 bar;	/* Base Addr Register */
+	u32 ar;		/* Attributes Register */
+} law521x_t;
+
+/*
+ * System configuration registers
+ */
+typedef struct sysconf512x {
+	u32 immrbar;		/* Internal memory map base address register */
+	u8 res0[0x1c];
+	u32 lpbaw;		/* LP Boot Access Window */
+	u32 lpcs0aw;		/* LP CS0 Access Window */
+	u32 lpcs1aw;		/* LP CS1 Access Window */
+	u32 lpcs2aw;		/* LP CS2 Access Window */
+	u32 lpcs3aw;		/* LP CS3 Access Window */
+	u32 lpcs4aw;		/* LP CS4 Access Window */
+	u32 lpcs5aw;		/* LP CS5 Access Window */
+	u32 lpcs6aw;		/* LP CS6 Access Window */
+	u32 lpcs7aw;		/* LP CS7 Access Window */
+	u8 res1[0x1c];
+	law521x_t pcilaw[3];	/* PCI Local Access Window 0-2 Registers */
+	u8 res2[0x28];
+	law521x_t ddrlaw;	/* DDR Local Access Window */
+	u8 res3[0x18];
+	u32 mbxbar;		/* MBX Base Address */
+	u32 srambar;		/* SRAM Base Address */
+	u32 nfcbar;		/* NFC Base Address */
+	u8 res4[0x34];
+	u32 spridr;		/* System Part and Revision ID Register */
+	u32 spcr;		/* System Priority Configuration Register */
+	u8 res5[0xf8];
+} sysconf512x_t;
+
+/*
+ * Watch Dog Timer (WDT) Registers
+ */
+typedef struct wdt512x {
+	u8 res0[4];
+	u32 swcrr;		/* System watchdog control register */
+	u32 swcnr;		/* System watchdog count register */
+	u8 res1[2];
+	u16 swsrr;		/* System watchdog service register */
+	u8 res2[0xF0];
+} wdt512x_t;
+
+/*
+ * RTC Module Registers
+ */
+typedef struct rtclk512x {
+	u8 fixme[0x100];
+} rtclk512x_t;
+
+/*
+ * General Purpose Timer
+ */
+typedef struct gpt512x {
+	u8 fixme[0x100];
+} gpt512x_t;
+
+/*
+ * Integrated Programmable Interrupt Controller
+ */
+typedef struct ipic512x {
+	u8 fixme[0x100];
+} ipic512x_t;
+
+/*
+ * System Arbiter Registers
+ */
+typedef struct arbiter512x {
+	u32 acr;		/* Arbiter Configuration Register */
+	u32 atr;		/* Arbiter Timers Register */
+	u32 ater;		/* Arbiter Transfer Error Register */
+	u32 aer;		/* Arbiter Event Register */
+	u32 aidr;		/* Arbiter Interrupt Definition Register */
+	u32 amr;		/* Arbiter Mask Register */
+	u32 aeatr;		/* Arbiter Event Attributes Register */
+	u32 aeadr;		/* Arbiter Event Address Register */
+	u32 aerr;		/* Arbiter Event Response Register */
+	u8 res1[0xDC];
+} arbiter512x_t;
+
+/*
+ * Reset Module
+ */
+typedef struct reset512x {
+	u32 rcwl;		/* Reset Configuration Word Low Register */
+	u32 rcwh;		/* Reset Configuration Word High Register */
+	u8 res0[8];
+	u32 rsr;		/* Reset Status Register */
+	u32 rmr;		/* Reset Mode Register */
+	u32 rpr;		/* Reset protection Register */
+	u32 rcr;		/* Reset Control Register */
+	u32 rcer;		/* Reset Control Enable Register */
+	u8 res1[0xDC];
+} reset512x_t;
+
+/*
+ * Clock Module
+ */
+typedef struct clk512x {
+	u32 spmr;		/* System PLL Mode Register */
+	u32 sccr[2];		/* System Clock Control Registers */
+	u32 scfr[2];		/* System Clock Frequency Registers */
+	u8 res0[4];
+	u32 bcr;		/* Bread Crumb Register */
+	u32 pscccr[12];		/* PSC0-11 Clock Control Registers */
+	u32 spccr;		/* SPDIF Clock Control Registers */
+	u32 cccr;		/* CFM Clock Control Registers */
+	u32 dccr;		/* DIU Clock Control Registers */
+	u8 res1[0xa8];
+} clk512x_t;
+
+/*
+ * Power Management Control Module
+ */
+typedef struct pmc512x {
+	u8 fixme[0x100];
+} pmc512x_t;
+
+/*
+ * General purpose I/O module
+ */
+typedef struct gpio512x {
+	u8 fixme[0x100];
+} gpio512x_t;
+
+/*
+ * DDR Memory Controller Memory Map
+ */
+typedef struct ddr512x {
+	u32 ddr_sys_config;	/* System Configuration Register */
+	u32 ddr_time_config0;	/* Timing Configuration Register */
+	u32 ddr_time_config1;	/* Timing Configuration Register */
+	u32 ddr_time_config2;	/* Timing Configuration Register */
+	u32 ddr_command;	/* Command Register */
+	u32 ddr_compact_command;	/* Compact Command Register */
+	u32 self_refresh_cmd_0;	/* Enter/Exit Self Refresh Registers */
+	u32 self_refresh_cmd_1;	/* Enter/Exit Self Refresh Registers */
+	u32 self_refresh_cmd_2;	/* Enter/Exit Self Refresh Registers */
+	u32 self_refresh_cmd_3;	/* Enter/Exit Self Refresh Registers */
+	u32 self_refresh_cmd_4;	/* Enter/Exit Self Refresh Registers */
+	u32 self_refresh_cmd_5;	/* Enter/Exit Self Refresh Registers */
+	u32 self_refresh_cmd_6;	/* Enter/Exit Self Refresh Registers */
+	u32 self_refresh_cmd_7;	/* Enter/Exit Self Refresh Registers */
+	u32 DQS_config_offset_count;	/* DQS Config Offset Count */
+	u32 DQS_config_offset_time;	/* DQS Config Offset Time */
+	u32 DQS_delay_status;	/* DQS Delay Status */
+	u32 res0[0xF];
+	u32 prioman_config1;	/* Priority Manager Configuration */
+	u32 prioman_config2;	/* Priority Manager Configuration */
+	u32 hiprio_config;	/* High Priority Configuration */
+	u32 lut_table0_main_upper;	/* LUT0 Main Upper */
+	u32 lut_table1_main_upper;	/* LUT1 Main Upper */
+	u32 lut_table2_main_upper;	/* LUT2 Main Upper */
+	u32 lut_table3_main_upper;	/* LUT3 Main Upper */
+	u32 lut_table4_main_upper;	/* LUT4 Main Upper */
+	u32 lut_table0_main_lower;	/* LUT0 Main Lower */
+	u32 lut_table1_main_lower;	/* LUT1 Main Lower */
+	u32 lut_table2_main_lower;	/* LUT2 Main Lower */
+	u32 lut_table3_main_lower;	/* LUT3 Main Lower */
+	u32 lut_table4_main_lower;	/* LUT4 Main Lower */
+	u32 lut_table0_alternate_upper;	/* LUT0 Alternate Upper */
+	u32 lut_table1_alternate_upper; /* LUT1 Alternate Upper */
+	u32 lut_table2_alternate_upper; /* LUT2 Alternate Upper */
+	u32 lut_table3_alternate_upper; /* LUT3 Alternate Upper */
+	u32 lut_table4_alternate_upper; /* LUT4 Alternate Upper */
+	u32 lut_table0_alternate_lower; /* LUT0 Alternate Lower */
+	u32 lut_table1_alternate_lower; /* LUT1 Alternate Lower */
+	u32 lut_table2_alternate_lower; /* LUT2 Alternate Lower */
+	u32 lut_table3_alternate_lower; /* LUT3 Alternate Lower */
+	u32 lut_table4_alternate_lower; /* LUT4 Alternate Lower */
+	u32 performance_monitor_config;
+	u32 event_time_counter;
+	u32 event_time_preset;
+	u32 performance_monitor1_address_low;
+	u32 performance_monitor2_address_low;
+	u32 performance_monitor1_address_hi;
+	u32 performance_monitor2_address_hi;
+	u32 res1[2];
+	u32 performance_monitor1_read_counter;
+	u32 performance_monitor2_read_counter;
+	u32 performance_monitor1_write_counter;
+	u32 performance_monitor2_write_counter;
+	u32 granted_ack_counter0;
+	u32 granted_ack_counter1;
+	u32 granted_ack_counter2;
+	u32 granted_ack_counter3;
+	u32 granted_ack_counter4;
+	u32 cumulative_wait_counter0;
+	u32 cumulative_wait_counter1;
+	u32 cumulative_wait_counter2;
+	u32 cumulative_wait_counter3;
+	u32 cumulative_wait_counter4;
+	u32 summed_priority_counter0;
+	u32 summed_priority_counter1;
+	u32 summed_priority_counter2;
+	u32 summed_priority_counter3;
+	u32 summed_priority_counter4;
+	u32 res2[0x3AD];
+} ddr512x_t;
+
+
+/*
+ * DMA/Messaging Unit
+ */
+typedef struct dma512x {
+	u8 fixme[0x1800];
+} dma512x_t;
+
+/*
+ * PCI Software Configuration Registers
+ */
+typedef struct pciconf512x {
+	u8 fixme[0x80];
+} pciconf512x_t;
+
+/*
+ * Sequencer
+ */
+typedef struct ios512x {
+	u8 fixme[0x100];
+} ios512x_t;
+
+/*
+ * PCI Controller
+ */
+typedef struct pcictrl512x {
+	u8 fixme[0x100];
+} pcictrl512x_t;
+
+
+/*
+ * MSCAN
+ */
+typedef struct mscan512x {
+	u8 fixme[0x100];
+} mscan512x_t;
+
+/*
+ * BDLC
+ */
+typedef struct bdlc512x {
+	u8 fixme[0x100];
+} bdlc512x_t;
+
+/*
+ * SDHC
+ */
+typedef struct sdhc512x {
+	u8 fixme[0x100];
+} sdhc512x_t;
+
+/*
+ * SPDIF
+ */
+typedef struct spdif512x {
+	u8 fixme[0x100];
+} spdif512x_t;
+
+/*
+ * I2C
+ */
+typedef struct i2c512x_dev {
+	volatile u32 madr;		/* I2Cn + 0x00 */
+	volatile u32 mfdr;		/* I2Cn + 0x04 */
+	volatile u32 mcr;		/* I2Cn + 0x08 */
+	volatile u32 msr;		/* I2Cn + 0x0C */
+	volatile u32 mdr;		/* I2Cn + 0x10 */
+	u8 res0[0x0C];
+} i2c512x_dev_t;
+
+typedef struct i2c512x {
+	i2c512x_dev_t dev[3];
+	volatile u32 icr;
+	volatile u32 mifr;
+	u8 res0[0x98];
+} i2c512x_t;
+
+/*
+ * AXE
+ */
+typedef struct axe512x {
+	u8 fixme[0x100];
+} axe512x_t;
+
+/*
+ * DIU
+ */
+typedef struct diu512x {
+	u8 fixme[0x100];
+} diu512x_t;
+
+/*
+ * CFM
+ */
+typedef struct cfm512x {
+	u8 fixme[0x100];
+} cfm512x_t;
+
+/*
+ * FEC
+ */
+typedef struct fec512x {
+	u8 fixme[0x800];
+} fec512x_t;
+
+/*
+ * ULPI
+ */
+typedef struct ulpi512x {
+	u8 fixme[0x600];
+} ulpi512x_t;
+
+/*
+ * UTMI
+ */
+typedef struct utmi512x {
+	u8 fixme[0x3000];
+} utmi512x_t;
+
+/*
+ * PCI DMA
+ */
+typedef struct pcidma512x {
+	u8 fixme[0x300];
+} pcidma512x_t;
+
+/*
+ * IO Control
+ */
+typedef struct ioctrl512x {
+	u32 regs[0x400];
+} ioctrl512x_t;
+
+/*
+ * IIM
+ */
+typedef struct iim512x {
+	u8 fixme[0x1000];
+} iim512x_t;
+
+/*
+ * LPC
+ */
+typedef struct lpc512x {
+	u32	cs_cfg[8];	/* Chip Select N Configuration Registers
+				   No dedicated entry for CS Boot as == CS0 */
+	u32	cs_cr;		/* Chip Select Control Register */
+	u32	cs_sr;		/* Chip Select Status Register */
+	u32	cs_bcr;		/* Chip Select Burst Control Register */
+	u32	cs_dccr;	/* Chip Select Deadcycle Control Register */
+	u32	cs_hccr;	/* Chip Select Holdcycle Control Register */
+	u8	res0[0xcc];
+	u32	sclpc_psr;	/* SCLPC Packet Size Register */
+	u32	sclpc_sar;	/* SCLPC Start Address Register */
+	u32	sclpc_cr;	/* SCLPC Control Register */
+	u32	sclpc_er;	/* SCLPC Enable Register */
+	u32	sclpc_nar;	/* SCLPC NextAddress Register */
+	u32	sclpc_sr;	/* SCLPC Status Register */
+	u32	sclpc_bdr;	/* SCLPC Bytes Done Register */
+	u32	emb_scr;	/* EMB Share Counter Register */
+	u32	emb_pcr;	/* EMB Pause Control Register */
+	u8	res1[0x1c];
+	u32	lpc_fdwr;	/* LPC RX/TX FIFO Data Word Register */
+	u32	lpc_fsr;	/* LPC RX/TX FIFO Status Register */
+	u32	lpc_cr;		/* LPC RX/TX FIFO Control Register */
+	u32	lpc_ar;		/* LPC RX/TX FIFO Alarm Register */
+	u8	res2[0xb0];
+} lpc512x_t;
+
+/*
+ * PATA
+ */
+typedef struct pata512x {
+	u8 fixme[0x100];
+} pata512x_t;
+
+/*
+ * PSC
+ */
+typedef struct psc512x {
+	volatile u8	mode;		/* PSC + 0x00 */
+	volatile u8	res0[3];
+	union {				/* PSC + 0x04 */
+		volatile u16	status;
+		volatile u16	clock_select;
+	} sr_csr;
+#define psc_status	sr_csr.status
+#define psc_clock_select sr_csr.clock_select
+	volatile u16	res1;
+	volatile u8	command;	/* PSC + 0x08 */
+	volatile u8	res2[3];
+	union {				/* PSC + 0x0c */
+		volatile u8	buffer_8;
+		volatile u16	buffer_16;
+		volatile u32	buffer_32;
+	} buffer;
+#define psc_buffer_8	buffer.buffer_8
+#define psc_buffer_16	buffer.buffer_16
+#define psc_buffer_32	buffer.buffer_32
+	union {				/* PSC + 0x10 */
+		volatile u8	ipcr;
+		volatile u8	acr;
+	} ipcr_acr;
+#define psc_ipcr	ipcr_acr.ipcr
+#define psc_acr		ipcr_acr.acr
+	volatile u8	res3[3];
+	union {				/* PSC + 0x14 */
+		volatile u16	isr;
+		volatile u16	imr;
+	} isr_imr;
+#define psc_isr		isr_imr.isr
+#define psc_imr		isr_imr.imr
+	volatile u16	res4;
+	volatile u8	ctur;		/* PSC + 0x18 */
+	volatile u8	res5[3];
+	volatile u8	ctlr;		/* PSC + 0x1c */
+	volatile u8	res6[3];
+	volatile u32	ccr;		/* PSC + 0x20 */
+	volatile u8	res7[12];
+	volatile u8	ivr;		/* PSC + 0x30 */
+	volatile u8	res8[3];
+	volatile u8	ip;		/* PSC + 0x34 */
+	volatile u8	res9[3];
+	volatile u8	op1;		/* PSC + 0x38 */
+	volatile u8	res10[3];
+	volatile u8	op0;		/* PSC + 0x3c */
+	volatile u8	res11[3];
+	volatile u32	sicr;		/* PSC + 0x40 */
+	volatile u8	res12[60];
+	volatile u32	tfcmd;		/* PSC + 0x80 */
+	volatile u32	tfalarm;	/* PSC + 0x84 */
+	volatile u32	tfstat;		/* PSC + 0x88 */
+	volatile u32	tfintstat;	/* PSC + 0x8C */
+	volatile u32	tfintmask;	/* PSC + 0x90 */
+	volatile u32	tfcount;	/* PSC + 0x94 */
+	volatile u16	tfwptr;		/* PSC + 0x98 */
+	volatile u16	tfrptr;		/* PSC + 0x9A */
+	volatile u32	tfsize;		/* PSC + 0x9C */
+	volatile u8	res13[28];
+	union {				/* PSC + 0xBC */
+		volatile u8	buffer_8;
+		volatile u16	buffer_16;
+		volatile u32	buffer_32;
+	} tfdata_buffer;
+#define tfdata_8	tfdata_buffer.buffer_8
+#define tfdata_16	tfdata_buffer.buffer_16
+#define tfdata_32	tfdata_buffer.buffer_32
+
+	volatile u32	rfcmd;		/* PSC + 0xC0 */
+	volatile u32	rfalarm;	/* PSC + 0xC4 */
+	volatile u32	rfstat;		/* PSC + 0xC8 */
+	volatile u32	rfintstat;	/* PSC + 0xCC */
+	volatile u32	rfintmask;	/* PSC + 0xD0 */
+	volatile u32	rfcount;	/* PSC + 0xD4 */
+	volatile u16	rfwptr;		/* PSC + 0xD8 */
+	volatile u16	rfrptr;		/* PSC + 0xDA */
+	volatile u32	rfsize;		/* PSC + 0xDC */
+	volatile u8	res18[28];
+	union {				/* PSC + 0xFC */
+		volatile u8	buffer_8;
+		volatile u16	buffer_16;
+		volatile u32	buffer_32;
+	} rfdata_buffer;
+#define rfdata_8	rfdata_buffer.buffer_8
+#define rfdata_16	rfdata_buffer.buffer_16
+#define rfdata_32	rfdata_buffer.buffer_32
+} psc512x_t;
+
+/*
+ * FIFOC
+ */
+typedef struct fifoc512x {
+	u32 fifoc_cmd;
+	u32 fifoc_int;
+	u32 fifoc_dma;
+	u32 fifoc_axe;
+	u32 fifoc_debug;
+	u8 fixme[0xEC];
+} fifoc512x_t;
+
+/*
+ * SATA
+ */
+typedef struct sata512x {
+	u8 fixme[0x2000];
+} sata512x_t;
+
+typedef struct immap {
+	sysconf512x_t		sysconf;	/* System configuration */
+	u8			res0[0x700];
+	wdt512x_t		wdt;		/* Watch Dog Timer (WDT) */
+	rtclk512x_t		rtc;		/* Real Time Clock Module */
+	gpt512x_t		gpt;		/* General Purpose Timer */
+	ipic512x_t		ipic;		/* Integrated Programmable Interrupt Controller */
+	arbiter512x_t		arbiter;	/* CSB Arbiter */
+	reset512x_t		reset;		/* Reset Module */
+	clk512x_t		clk;		/* Clock Module */
+	pmc512x_t		pmc;		/* Power Management Control Module */
+	gpio512x_t		gpio;		/* General purpose I/O module */
+	u8			res1[0x100];
+	mscan512x_t		mscan;		/* MSCAN */
+	bdlc512x_t		bdlc;		/* BDLC */
+	sdhc512x_t		sdhc;		/* SDHC */
+	spdif512x_t		spdif;		/* SPDIF */
+	i2c512x_t		i2c;		/* I2C Controllers */
+	u8			res2[0x800];
+	axe512x_t		axe;		/* AXE */
+	diu512x_t		diu;		/* Display Interface Unit */
+	cfm512x_t		cfm;		/* Clock Frequency Measurement */
+	u8			res3[0x500];
+	fec512x_t		fec;		/* Fast Ethernet Controller */
+	ulpi512x_t		ulpi;		/* USB ULPI */
+	u8			res4[0xa00];
+	utmi512x_t		utmi;		/* USB UTMI */
+	u8			res5[0x1000];
+	pcidma512x_t		pci_dma;	/* PCI DMA */
+	pciconf512x_t		pci_conf;	/* PCI Configuration */
+	u8			res6[0x80];
+	ios512x_t		ios;		/* PCI Sequencer */
+	pcictrl512x_t		pci_ctrl;	/* PCI Controller Control and Status */
+	u8			res7[0xa00];
+	ddr512x_t		mddrc;		/* Multi-port DDR Memory Controller */
+	ioctrl512x_t		io_ctrl;	/* IO Control */
+	iim512x_t		iim;		/* IC Identification module */
+	u8			res8[0x4000];
+	lpc512x_t		lpc;		/* LocalPlus Controller */
+	pata512x_t		pata;		/* Parallel ATA */
+	u8			res9[0xd00];
+	psc512x_t		psc[12];	/* PSCs */
+	u8			res10[0x300];
+	fifoc512x_t		fifoc;		/* FIFO Controller */
+	u8			res11[0x2000];
+	dma512x_t		dma;		/* DMA */
+	u8			res12[0xa800];
+	sata512x_t		sata;		/* Serial ATA */
+	u8			res13[0xde000];
+} immap_t;
+#endif /* __IMMAP_512x__ */
diff --git a/include/common.h b/include/common.h
index 23f9390..d823733 100644
--- a/include/common.h
+++ b/include/common.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2004
+ * (C) Copyright 2000-2007
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -65,6 +65,9 @@ typedef volatile unsigned char	vu_char;
 #include <asm/5xx_immap.h>
 #elif defined(CONFIG_MPC5xxx)
 #include <mpc5xxx.h>
+#elif defined(CONFIG_MPC512X)
+#include <mpc512x.h>
+#include <asm/immap_512x.h>
 #elif defined(CONFIG_MPC8220)
 #include <asm/immap_8220.h>
 #elif defined(CONFIG_8260)
@@ -448,6 +451,9 @@ int	prt_8260_clks (void);
 #elif defined(CONFIG_MPC5xxx)
 int	prt_mpc5xxx_clks (void);
 #endif
+#if defined(CONFIG_MPC512x)
+int	prt_mpc512xxx_clks (void);
+#endif
 #if defined(CONFIG_MPC8220)
 int	prt_mpc8220_clks (void);
 #endif
diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h
new file mode 100644
index 0000000..a1b8eef
--- /dev/null
+++ b/include/configs/ads5121.h
@@ -0,0 +1,410 @@
+/*
+ * (C) Copyright 2007 DENX Software Engineering
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * ADS5121 board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define DEBUG
+#undef DEBUG
+
+/*
+ * Memory map for the ADS5121 board:
+ *
+ * 0x0000_0000 - 0x0FFF_FFFF	DDR RAM (256 MB)
+ * 0x3000_0000 - 0x3001_FFFF	SRAM (128 KB)
+ * 0x8000_0000 - 0x803F_FFFF	IMMR (4 MB)
+ * 0x8200_0000 - 0x8200_001F	CPLD (32 B)
+ * 0xFC00_0000 - 0xFFFF_FFFF	NOR Boot FLASH (64 MB)
+ */
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 Family */
+#define CONFIG_MPC512X		1	/* MPC512X family */
+
+#undef CONFIG_PCI
+
+#define CFG_MPC512X_CLKIN	66000000	/* in Hz */
+
+#define CONFIG_BOARD_EARLY_INIT_F		/* call board_early_init_f() */
+
+#define CFG_IMMR		0x80000000
+
+#define CFG_MEMTEST_START	0x00200000      /* memtest region */
+#define CFG_MEMTEST_END		0x00400000
+
+/*
+ * DDR Setup - manually set all parameters as there's no SPD etc.
+ */
+#define CFG_DDR_SIZE		256		/* MB */
+#define CFG_DDR_BASE		0x00000000	/* DDR is system memory*/
+#define CFG_SDRAM_BASE		CFG_DDR_BASE
+
+/* DDR Controller Configuration
+
+SYS_CFG:
+ 	[31:31]	MDDRC Soft Reset:	Diabled
+	[30:30]	DRAM CKE pin:		Enabled
+	[29:29]	DRAM CLK:		Enabled
+	[28:28]	Command Mode:		Enabled (For initialization only)    
+	[27:25]	DRAM Row Select:	dram_row[15:0] = magenta_address[25:10]
+	[24:21]	DRAM Bank Select:	dram_bank[1:0] = magenta_address[11:10]
+	[20:19]	Read Test:		DON'T USE
+	[18:18]	Self Refresh:		Enabled
+	[17:17]	16bit Mode:		Disabled
+	[16:13] Ready Delay:		2
+	[12:12]	Half DQS Delay:		Disabled
+	[11:11]	Quarter DQS Delay:	Disabled
+	[10:08]	Write Delay:		2
+	[07:07]	Early ODT:		Disabled
+	[06:06]	On DIE Termination:	Disabled
+	[05:05]	FIFO Overflow Clear:	DON'T USE here
+	[04:04]	FIFO Underflow Clear:	DON'T USE here
+	[03:03]	FIFO Overflow Pending:	DON'T USE here
+	[02:02]	FIFO Underlfow Pending:	DON'T USE here
+	[01:01]	FIFO Overlfow Enabled:	Enabled
+	[00:00]	FIFO Underflow Enabled:	Enabled
+ TIME_CFG0
+ 	[31:16]	DRAM Refresh Time:	0 CSB clocks	
+	[15:8]	DRAM Command Time:	0 CSB clocks
+	[07:00]	DRAM Precharge Time:	0 CSB clocks
+ TIME_CFG1
+ 	[31:26]	DRAM tRFC:
+	[25:21]	DRAM tWR1:
+	[20:17]	DRAM tWRT1:
+	[16:11]	DRAM tDRR:
+	[10:05]	DRAM tRC:
+	[04:00]	DRAM tRAS:
+ TIME_CFG2
+ 	[31:28]	DRAM tRCD:
+	[27:23]	DRAM tFAW:
+	[22:19]	DRAM tRTW1:
+	[18:15]	DRAM tCCD:
+	[14:10] DRAM tRTP:
+	[09:05]	DRAM tRP:
+	[04:00] DRAM tRPA */
+
+#define CFG_MDDRC_SYS_CFG	0xF8604200
+#define CFG_MDDRC_SYS_CFG_RUN	0xE8604200
+#define CFG_MDDRC_SYS_CFG_EN	0x30000000
+#define CFG_MDDRC_TIME_CFG0	0x0000281E
+#define CFG_MDDRC_TIME_CFG0_RUN	0x01F4281E
+#define CFG_MDDRC_TIME_CFG1	0x54EC1168
+#define CFG_MDDRC_TIME_CFG2	0x35210864
+
+#define CFG_MICRON_NOP		0x01380000
+#define CFG_MICRON_PCHG_ALL	0x01100400
+#define CFG_MICRON_MR		0x01000022
+#define CFG_MICRON_EM2		0x01020000
+#define CFG_MICRON_EM3		0x01030000
+#define CFG_MICRON_EN_DLL	0x01010000
+#define CFG_MICRON_RST_DLL	0x01000932
+#define CFG_MICRON_RFSH		0x01080000
+#define CFG_MICRON_INIT_DEV_OP	0x01000832
+#define CFG_MICRON_OCD_DEFAULT	0x01010780
+#define CFG_MICRON_OCD_EXIT	0x01010400
+
+/* DDR Priority Manager Configuration */
+#define CFG_MDDRCGRP_PM_CFG1	0x000777AA
+#define CFG_MDDRCGRP_PM_CFG2	0x00000055
+#define CFG_MDDRCGRP_HIPRIO_CFG	0x00000000
+#define CFG_MDDRCGRP_LUT0_MU    0x11111117
+#define CFG_MDDRCGRP_LUT0_ML	0x7777777A
+#define CFG_MDDRCGRP_LUT1_MU    0x4444EEEE
+#define CFG_MDDRCGRP_LUT1_ML	0xEEEEEEEE
+#define CFG_MDDRCGRP_LUT2_MU    0x44444444
+#define CFG_MDDRCGRP_LUT2_ML	0x44444444
+#define CFG_MDDRCGRP_LUT3_MU    0x55555555
+#define CFG_MDDRCGRP_LUT3_ML	0x55555558
+#define CFG_MDDRCGRP_LUT4_MU    0x11111111
+#define CFG_MDDRCGRP_LUT4_ML	0x1111117C
+#define CFG_MDDRCGRP_LUT0_AU    0x33333377
+#define CFG_MDDRCGRP_LUT0_AL	0x7777EEEE
+#define CFG_MDDRCGRP_LUT1_AU    0x11111111
+#define CFG_MDDRCGRP_LUT1_AL	0x11111111
+#define CFG_MDDRCGRP_LUT2_AU    0x11111111
+#define CFG_MDDRCGRP_LUT2_AL	0x11111111
+#define CFG_MDDRCGRP_LUT3_AU    0x11111111
+#define CFG_MDDRCGRP_LUT3_AL	0x11111111
+#define CFG_MDDRCGRP_LUT4_AU    0x11111111
+#define CFG_MDDRCGRP_LUT4_AL	0x11111111
+
+/*
+ * NOR FLASH on the Local Bus
+ */
+#define CFG_FLASH_CFI				/* use the Common Flash Interface */
+#define CFG_FLASH_CFI_DRIVER			/* use the CFI driver */
+#define CFG_FLASH_BASE		0xFC000000	/* start of FLASH   */
+#define CFG_FLASH_SIZE		0x04000000	/* max flash size in bytes */
+#define CFG_FLASH_USE_BUFFER_WRITE
+
+#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
+#define CFG_FLASH_BANKS_LIST 	{CFG_FLASH_BASE}
+#define CFG_MAX_FLASH_SECT	256		/* max sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+
+/*
+ * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
+ * window is 64KB
+ */
+#define CFG_CPLD_BASE		0x82000000
+#define CFG_CPLD_SIZE		0x00010000	/* 64 KB */
+
+#define CFG_SRAM_BASE		0x30000000
+#define CFG_SRAM_SIZE		0x00020000	/* 128 KB */
+
+#define CFG_CS0_CFG		0x05059310	/* ALE active low, data size 4bytes */
+#define CFG_CS2_CFG		0x05059010	/* ALE active low, data size 1byte */
+
+/* Use SRAM for initial stack */
+#define CFG_INIT_RAM_ADDR	CFG_SRAM_BASE		/* Initial RAM address */
+#define CFG_INIT_RAM_END	CFG_SRAM_SIZE		/* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE	0x100			/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE	TEXT_BASE		/* Start of monitor */
+#define CFG_MONITOR_LEN		(256 * 1024)		/* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(512 * 1024)		/* Reserved for malloc */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX     1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	3	/* console is on PSC3 */
+#if CONFIG_PSC_CONSOLE != 3
+#error CONFIG_PSC_CONSOLE must be 3
+#endif
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONSOLE_FIFO_TX_SIZE	FIFOC_PSC3_TX_SIZE
+#define CONSOLE_FIFO_TX_ADDR	FIFOC_PSC3_TX_ADDR
+#define CONSOLE_FIFO_RX_SIZE	FIFOC_PSC3_RX_SIZE
+#define CONSOLE_FIFO_RX_ADDR	FIFOC_PSC3_RX_ADDR
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef  CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define CONFIG_HARD_I2C			/* I2C with hardware support */
+#undef CONFIG_SOFT_I2C			/* so disable bit-banged I2C */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CFG_I2C_SPEED		100000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+#if 0
+#define CFG_I2C_NOPROBES	{{0,0x69}}	* Don't probe these addrs */
+#endif
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC512x_FEC	1
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_ADDR		0x1
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_ETHADDR		00:e0:5e:00:e5:14
+
+#if 0
+/*
+ * Configure on-board RTC
+ */
+#define CONFIG_RTC_DS1374			/* use ds1374 rtc via i2c	*/
+#define CFG_I2C_RTC_ADDR		0x68	/* at address 0x68		*/
+#endif
+
+/*
+ * Environment
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+/* This has to be a multiple of the Flash sector size */
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CFG_ENV_SIZE		0x2000
+#define CFG_ENV_SECT_SIZE	0x40000	/* one sector (256K) for env */
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+#if defined(CONFIG_PCI)
+#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL		\
+				| CFG_CMD_PCI		\
+				| CFG_CMD_NET		\
+				| CFG_CMD_PING		\
+				)
+#else
+#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL		\
+				| CFG_CMD_NET		\
+				| CFG_CMD_PING		\
+          			| CFG_CMD_MII		\
+				| CFG_CMD_I2C)
+#endif
+
+#include <cmd_confdefs.h>
+
+/*
+ * Watchdog timeout = CFG_WATCHDOG_VALUE * 65536 / IPS clock.
+ * For example, when IPS is set to 66MHz and CFG_WATCHDOG_VALUE is set
+ * to 0xFFFF, watchdog timeouts after about 64s. For details refer
+ * to chapter 36 of the MPC5121e Reference Manual.
+ */
+#define CONFIG_WATCHDOG			/* enable watchdog */
+#define CFG_WATCHDOG_VALUE 0xFFFF
+
+ /*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory */
+#define CFG_LOAD_ADDR	0x2000000	/* default load address */
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+	#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+	#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+
+
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE		32768
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
+#endif
+
+#define CFG_HID0_INIT	0x000000000
+#define CFG_HID0_FINAL	HID0_ENABLE_MACHINE_CHECK
+#define CFG_HID2	HID2_HBE
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02	/* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_HOSTNAME		ads5121
+#define CONFIG_ROOTPATH		/nfsroot/rootfs
+#define CONFIG_BOOTFILE		uImage
+
+#define CONFIG_IPADDR		192.168.160.77
+#define CONFIG_SERVERIP		192.168.1.1
+#define CONFIG_GATEWAYIP	192.168.1.1
+#define CONFIG_NETMASK		255.255.0.0
+
+#define CONFIG_LOADADDR		200000	/* default location for tftp and bootm */
+
+//#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
+#define CONFIG_BOOTDELAY	-1
+#undef  CONFIG_BOOTARGS			/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"	\
+		"bootm\0"						\
+	"load=tftp 100000 /tftpboot/ads5121/u-boot.bin\0"		\
+	"update=protect off fff00000 fff3ffff; "			\
+		"era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0"	\
+	"upd=run load;run update\0"					\
+	""
+
+#define CONFIG_NFSBOOTCOMMAND	                                        \
+   "setenv bootargs root=/dev/nfs rw "                                  \
+      "nfsroot=$serverip:$rootpath "                                    \
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $loadaddr $bootfile;"                                          \
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+   "setenv bootargs root=/dev/ram rw "                                  \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $ramdiskaddr $ramdiskfile;"                                    \
+   "tftp $loadaddr $bootfile;"                                          \
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#endif	/* __CONFIG_H */
diff --git a/include/mpc512x.h b/include/mpc512x.h
new file mode 100644
index 0000000..03e0e9a
--- /dev/null
+++ b/include/mpc512x.h
@@ -0,0 +1,398 @@
+/*
+ * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
+ * (C) Copyright 2007 DENX Software Engineering
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * Derived from the MPC83xx header.
+ */
+
+#ifndef __MPC512X_H__
+#define __MPC512X_H__
+
+#include <config.h>
+#if defined(CONFIG_E300)
+#include <asm/e300.h>
+#endif
+
+/* System reset offset (PowerPC standard)
+ */
+#define EXC_OFF_SYS_RESET		0x0100
+#define	_START_OFFSET			EXC_OFF_SYS_RESET
+
+
+/* IMMRBAR - Internal Memory Register Base Address
+ */
+#define CONFIG_DEFAULT_IMMR		0xFF400000	/* Default IMMR base address */
+#define IMMRBAR				0x0000		/* Register offset to immr */
+#define IMMRBAR_BASE_ADDR		0xFFF00000	/* Base address mask */
+#define IMMRBAR_RES			~(IMMRBAR_BASE_ADDR)
+
+/* LAWBAR - Local Access Window Base Address Register
+ */
+#define LPBAW			0x0020		/* Register offset to immr */
+#define LPCS0AW			0x0024
+#define LPCS1AW			0x0028
+#define LPCS2AW			0x002C
+#define LPCS3AW			0x0030
+#define LPCS4AW			0x0034
+#define LPCS5AW			0x0038
+#define LPCS6AW			0x003C
+#define LPCA7AW			0x0040
+#define SRAMBAR			0x00C4
+
+#define LPC_OFFSET		0x10000
+
+#define CS0_CONFIG		0x00000
+#define CS1_CONFIG		0x00004
+#define CS2_CONFIG		0x00008
+#define CS3_CONFIG		0x0000C
+#define CS4_CONFIG		0x00010
+#define CS5_CONFIG		0x00014
+#define CS6_CONFIG		0x00018
+#define CS7_CONFIG		0x0001C
+
+#define CS_CTRL			0x00020
+#define CS_CTRL_ME		0x01000000	/* CS Master Enable bit */
+#define CS_CTRL_IE		0x08000000	/* CS Interrupt Enable bit */ 
+
+/* SPRIDR - System Part and Revision ID Register
+ */
+#define SPRIDR_PARTID		0xFFFF0000	/* Part Identification */
+#define SPRIDR_REVID		0x0000FFFF	/* Revision Identification */
+
+#define SPR_5121E		0x80180000
+
+/* SPCR - System Priority Configuration Register
+ */
+#define SPCR_PCIHPE			0x10000000	/* PCI Highest Priority Enable */
+#define SPCR_PCIHPE_SHIFT		(31-3)
+#define SPCR_PCIPR			0x03000000	/* PCI bridge system bus request priority */
+#define SPCR_PCIPR_SHIFT		(31-7)
+#define SPCR_TBEN			0x00400000	/* E300 PowerPC core time base unit enable */
+#define SPCR_TBEN_SHIFT			(31-9)
+#define SPCR_COREPR			0x00300000	/* E300 PowerPC Core system bus request priority */
+#define SPCR_COREPR_SHIFT		(31-11)
+
+/* SWCRR - System Watchdog Control Register
+ */
+#define SWCRR				0x0904		/* Register offset to immr */
+#define SWCRR_SWTC			0xFFFF0000	/* Software Watchdog Time Count */
+#define SWCRR_SWEN			0x00000004	/* Watchdog Enable bit */
+#define SWCRR_SWRI			0x00000002	/* Software Watchdog Reset/Interrupt Select bit */
+#define SWCRR_SWPR			0x00000001	/* Software Watchdog Counter Prescale bit */
+#define SWCRR_RES			~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
+
+/* SWCNR - System Watchdog Counter Register
+ */
+#define SWCNR				0x0908		/* Register offset to immr */
+#define SWCNR_SWCN			0x0000FFFF	/* Software Watchdog Count mask */
+#define SWCNR_RES			~(SWCNR_SWCN)
+
+/* SWSRR - System Watchdog Service Register
+ */
+#define SWSRR				0x090E		/* Register offset to immr */
+
+/* ACR - Arbiter Configuration Register
+ */
+#define ACR_COREDIS			0x10000000	/* Core disable */
+#define ACR_COREDIS_SHIFT		(31-7)
+#define ACR_PIPE_DEP			0x00070000	/* Pipeline depth */
+#define ACR_PIPE_DEP_SHIFT		(31-15)
+#define ACR_PCI_RPTCNT			0x00007000	/* PCI repeat count */
+#define ACR_PCI_RPTCNT_SHIFT		(31-19)
+#define ACR_RPTCNT			0x00000700	/* Repeat count */
+#define ACR_RPTCNT_SHIFT		(31-23)
+#define ACR_APARK			0x00000030	/* Address parking */
+#define ACR_APARK_SHIFT			(31-27)
+#define ACR_PARKM			0x0000000F	/* Parking master */
+#define ACR_PARKM_SHIFT			(31-31)
+
+/* ATR - Arbiter Timers Register
+ */
+#define ATR_DTO				0x00FF0000	/* Data time out */
+#define ATR_ATO				0x000000FF	/* Address time out */
+
+/* AER - Arbiter Event Register
+ */
+#define AER_ETEA			0x00000020	/* Transfer error */
+#define AER_RES				0x00000010	/* Reserved transfer type */
+#define AER_ECW				0x00000008	/* External control word transfer type */
+#define AER_AO				0x00000004	/* Address Only transfer type */
+#define AER_DTO				0x00000002	/* Data time out */
+#define AER_ATO				0x00000001	/* Address time out */
+
+/* AEATR - Arbiter Event Address Register
+ */
+#define AEATR_EVENT			0x07000000	/* Event type */
+#define AEATR_MSTR_ID			0x001F0000	/* Master Id */
+#define AEATR_TBST			0x00000800	/* Transfer burst */
+#define AEATR_TSIZE			0x00000700	/* Transfer Size */
+#define AEATR_TTYPE			0x0000001F	/* Transfer Type */
+
+/* RSR - Reset Status Register
+ */
+#define RSR_SWSR			0x00002000	/* software soft reset */
+#define RSR_SWSR_SHIFT			13
+#define RSR_SWHR			0x00001000	/* software hard reset */
+#define RSR_SWHR_SHIFT			12
+#define RSR_JHRS			0x00000200	/* jtag hreset */
+#define RSR_JHRS_SHIFT			9
+#define RSR_JSRS			0x00000100	/* jtag sreset status */
+#define RSR_JSRS_SHIFT			8
+#define RSR_CSHR			0x00000010	/* checkstop reset status */
+#define RSR_CSHR_SHIFT			4
+#define RSR_SWRS			0x00000008	/* software watchdog reset status */
+#define RSR_SWRS_SHIFT			3
+#define RSR_BMRS			0x00000004	/* bus monitop reset status */
+#define RSR_BMRS_SHIFT			2
+#define RSR_SRS				0x00000002	/* soft reset status */
+#define RSR_SRS_SHIFT			1
+#define RSR_HRS				0x00000001	/* hard reset status */
+#define RSR_HRS_SHIFT			0
+#define RSR_RES				~(RSR_SWSR | RSR_SWHR |\
+					 RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\
+					 RSR_BMRS | RSR_SRS | RSR_HRS)
+/* RMR - Reset Mode Register
+ */
+#define RMR_CSRE			0x00000001	/* checkstop reset enable */
+#define RMR_CSRE_SHIFT			0
+#define RMR_RES				~(RMR_CSRE)
+
+/* RCR - Reset Control Register
+ */
+#define RCR_SWHR			0x00000002	/* software hard reset */
+#define RCR_SWSR			0x00000001	/* software soft reset */
+#define RCR_RES				~(RCR_SWHR | RCR_SWSR)
+
+/* RCER - Reset Control Enable Register
+ */
+#define RCER_CRE			0x00000001	/* software hard reset */
+#define RCER_RES			~(RCER_CRE)
+
+/* SPMR - System PLL Mode Register
+ */
+#define SPMR_SPMF			0x0F000000
+#define SPMR_SPMF_SHIFT			24
+#define SPMR_CPMF			0x000F0000
+#define SPMR_CPMF_SHIFT			16
+
+/* SCFR1 System Clock Frequency Register 1
+ */
+#define SCFR1_IPS_DIV			0x2
+#define SCFR1_IPS_DIV_MASK		0x03800000
+#define SCFR1_IPS_DIV_SHIFT		23
+
+/* SCFR2 System Clock Frequency Register 2
+ */
+#define SCFR2_SYS_DIV			0xFC000000
+#define SCFR2_SYS_DIV_SHIFT		26
+
+/* SCCR - System Clock Control Registers
+ */
+
+/* System Clock Control Register 1 commands */
+#define CLOCK_SCCR1_CFG_EN		0x80000000
+#define CLOCK_SCCR1_LPC_EN		0x40000000
+#define CLOCK_SCCR1_NFC_EN		0x20000000
+#define CLOCK_SCCR1_PATA_EN		0x10000000
+#define CLOCK_SCCR1_PSC_EN(cn)		(0x08000000 >> (cn))
+#define CLOCK_SCCR1_PSCFIFO_EN		0x00008000
+#define CLOCK_SCCR1_SATA_EN		0x00004000
+#define CLOCK_SCCR1_FEC_EN		0x00002000
+#define CLOCK_SCCR1_TPR_EN		0x00001000
+#define CLOCK_SCCR1_PCI_EN		0x00000800
+#define CLOCK_SCCR1_DDR_EN		0x00000400
+
+/* System Clock Control Register 2 commands */
+#define CLOCK_SCCR2_DIU_EN		0x80000000
+#define CLOCK_SCCR2_AXE_EN		0x40000000
+#define CLOCK_SCCR2_MEM_EN		0x20000000
+#define CLOCK_SCCR2_USB2_EN		0x10000000
+#define CLOCK_SCCR2_USB1_EN		0x08000000
+#define CLOCK_SCCR2_I2C_EN		0x04000000
+#define CLOCK_SCCR2_BDLC_EN		0x02000000
+#define CLOCK_SCCR2_SDHC_EN		0x01000000
+#define CLOCK_SCCR2_SPDIF_EN		0x00800000
+#define CLOCK_SCCR2_MBX_BUS_EN		0x00400000
+#define CLOCK_SCCR2_MBX_EN		0x00200000
+#define CLOCK_SCCR2_MBX_3D_EN		0x00100000
+#define CLOCK_SCCR2_IIM_EN		0x00080000
+
+/* PSC FIFO Command values */
+#define PSC_FIFO_RESET_SLICE		0x80
+#define PSC_FIFO_ENABLE_SLICE		0x01
+
+/* PSC FIFO Controller Command values */
+#define FIFOC_ENABLE_CLOCK_GATE		0x01
+#define FIFOC_DISABLE_CLOCK_GATE	0x00
+
+/* PSC FIFO status */
+#define PSC_FIFO_EMPTY			0x01
+
+/* PSC Command values */
+#define PSC_RX_ENABLE		0x01
+#define PSC_RX_DISABLE		0x02
+#define PSC_TX_ENABLE		0x04
+#define PSC_TX_DISABLE		0x08
+#define PSC_SEL_MODE_REG_1	0x10
+#define PSC_RST_RX		0x20
+#define PSC_RST_TX		0x30
+#define PSC_RST_ERR_STAT	0x40
+#define PSC_RST_BRK_CHG_INT	0x50
+#define PSC_START_BRK		0x60
+#define PSC_STOP_BRK		0x70
+
+/* PSC status register bits */
+#define PSC_SR_CDE		0x0080
+#define PSC_SR_TXEMP		0x0800
+#define PSC_SR_OE		0x1000
+#define PSC_SR_PE		0x2000
+#define PSC_SR_FE		0x4000
+#define PSC_SR_RB		0x8000
+
+/* PSC mode fields */
+#define PSC_MODE_5_BITS		0x00
+#define PSC_MODE_6_BITS		0x01
+#define PSC_MODE_7_BITS		0x02
+#define PSC_MODE_8_BITS		0x03
+#define PSC_MODE_PAREVEN	0x00
+#define PSC_MODE_PARODD		0x04
+#define PSC_MODE_PARFORCE	0x08
+#define PSC_MODE_PARNONE	0x10
+#define PSC_MODE_ENTIMEOUT	0x20
+#define PSC_MODE_RXRTS		0x80
+#define PSC_MODE_1_STOPBIT	0x07
+
+/*
+ * Centralized FIFO Controller has internal memory for all 12 PSCs FIFOs
+ *
+ * NOTE: individual PSC units are free to use whatever area (and size) of the
+ * FIFOC internal memory, so make sure memory areas for FIFO slices used by
+ * different PSCs do not overlap!
+ *
+ * Overall size of FIFOC memory is not documented in the MPC5121e RM, but
+ * tests indicate that it is 1024 words total.
+ */
+#define FIFOC_PSC0_TX_SIZE	0x0	/* number of 4-byte words for FIFO slice */
+#define FIFOC_PSC0_TX_ADDR	0x0
+#define FIFOC_PSC0_RX_SIZE	0x0
+#define FIFOC_PSC0_RX_ADDR	0x0
+
+#define FIFOC_PSC1_TX_SIZE	0x0
+#define FIFOC_PSC1_TX_ADDR	0x0
+#define FIFOC_PSC1_RX_SIZE	0x0
+#define FIFOC_PSC1_RX_ADDR	0x0
+
+#define FIFOC_PSC2_TX_SIZE	0x0
+#define FIFOC_PSC2_TX_ADDR	0x0
+#define FIFOC_PSC2_RX_SIZE	0x0
+#define FIFOC_PSC2_RX_ADDR	0x0
+
+#define FIFOC_PSC3_TX_SIZE	0x04
+#define FIFOC_PSC3_TX_ADDR	0x0
+#define FIFOC_PSC3_RX_SIZE	0x04
+#define FIFOC_PSC3_RX_ADDR	0x10
+
+#define FIFOC_PSC4_TX_SIZE	0x0
+#define FIFOC_PSC4_TX_ADDR	0x0
+#define FIFOC_PSC4_RX_SIZE	0x0
+#define FIFOC_PSC4_RX_ADDR	0x0
+
+#define FIFOC_PSC5_TX_SIZE	0x0
+#define FIFOC_PSC5_TX_ADDR	0x0
+#define FIFOC_PSC5_RX_SIZE	0x0
+#define FIFOC_PSC5_RX_ADDR	0x0
+
+#define FIFOC_PSC6_TX_SIZE	0x0
+#define FIFOC_PSC6_TX_ADDR	0x0
+#define FIFOC_PSC6_RX_SIZE	0x0
+#define FIFOC_PSC6_RX_ADDR	0x0
+
+#define FIFOC_PSC7_TX_SIZE	0x0
+#define FIFOC_PSC7_TX_ADDR	0x0
+#define FIFOC_PSC7_RX_SIZE	0x0
+#define FIFOC_PSC7_RX_ADDR	0x0
+
+#define FIFOC_PSC8_TX_SIZE	0x0
+#define FIFOC_PSC8_TX_ADDR	0x0
+#define FIFOC_PSC8_RX_SIZE	0x0
+#define FIFOC_PSC8_RX_ADDR	0x0
+
+#define FIFOC_PSC9_TX_SIZE	0x0
+#define FIFOC_PSC9_TX_ADDR	0x0
+#define FIFOC_PSC9_RX_SIZE	0x0
+#define FIFOC_PSC9_RX_ADDR	0x0
+
+#define FIFOC_PSC10_TX_SIZE	0x0
+#define FIFOC_PSC10_TX_ADDR	0x0
+#define FIFOC_PSC10_RX_SIZE	0x0
+#define FIFOC_PSC10_RX_ADDR	0x0
+
+#define FIFOC_PSC11_TX_SIZE	0x0
+#define FIFOC_PSC11_TX_ADDR	0x0
+#define FIFOC_PSC11_RX_SIZE	0x0
+#define FIFOC_PSC11_RX_ADDR	0x0
+
+/* IO Control Register
+ */
+
+/* Indexes in regs array */
+#define MEM_IDX			0x00
+#define SPDIF_TXCLOCK_IDX	0x73
+#define SPDIF_TX_IDX		0x74
+#define SPDIF_RX_IDX		0x75
+#define PSC0_0_IDX		0x83
+#define PSC0_1_IDX		0x84
+#define PSC0_2_IDX		0x85
+#define PSC0_3_IDX		0x86
+#define PSC0_4_IDX		0x87
+#define PSC1_0_IDX		0x88
+#define PSC1_1_IDX		0x89
+#define PSC1_2_IDX		0x8a
+#define PSC1_3_IDX		0x8b
+#define PSC1_4_IDX		0x8c
+#define PSC2_0_IDX		0x8d
+#define PSC2_1_IDX		0x8e
+#define PSC2_2_IDX		0x8f
+#define PSC2_3_IDX		0x90
+#define PSC2_4_IDX		0x91
+
+#define IOCTRL_FUNCMUX_SHIFT	7
+#define IOCTRL_FUNCMUX_FEC	1
+#define IOCTRL_MUX_FEC		(IOCTRL_FUNCMUX_FEC << IOCTRL_FUNCMUX_SHIFT)
+
+/* Set for DDR */
+#define IOCTRL_MUX_DDR		0x00000036
+
+ /* Register Offset Base */
+#define MPC512X_FEC		(CFG_IMMR + 0x02800)
+
+/* Number of I2C buses */
+#define I2C_BUS_CNT	3
+
+/* I2Cn control register bits */
+#define I2C_EN		0x80
+#define I2C_IEN		0x40
+#define I2C_STA		0x20
+#define I2C_TX		0x10
+#define I2C_TXAK	0x08
+#define I2C_RSTA	0x04
+#define I2C_INIT_MASK	(I2C_EN | I2C_STA | I2C_TX | I2C_RSTA)
+
+/* I2Cn status register bits */
+#define I2C_CF		0x80
+#define I2C_AAS		0x40
+#define I2C_BB		0x20
+#define I2C_AL		0x10
+#define I2C_SRW		0x04
+#define I2C_IF		0x02
+#define I2C_RXAK	0x01
+
+#endif	/* __MPC512X_H__ */