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| author | Terry Lv <r65388@freescale.com> | 2011-09-16 16:48:44 +0800 |
|---|---|---|
| committer | Terry Lv <r65388@freescale.com> | 2011-10-18 10:13:57 +0800 |
| commit | e7cdad7018f5921a651d06ef84a01b0c0dd7a5f1 (patch) | |
| tree | 09f71121ed0341461cb2325060f677450582eb5f /include | |
| parent | 856b3602d1f175706ceb54df4388e406bd3c6ff5 (diff) | |
| download | u-boot-imx-e7cdad7018f5921a651d06ef84a01b0c0dd7a5f1.zip u-boot-imx-e7cdad7018f5921a651d06ef84a01b0c0dd7a5f1.tar.gz u-boot-imx-e7cdad7018f5921a651d06ef84a01b0c0dd7a5f1.tar.bz2 | |
ENGR00156930: Update MX35 DDR2 scripts
Update MX35 DDR2 scripts for that when enabling 256MB, the CSD1 is not
stable.
1. Add CSD1 configs to support 256M RAM.
2. Add mx35 TO2 256M RAM configs.
3. Update DDR init code in lowlevel_init.S for external boot.
Signed-off-by: Terry Lv <r65388@freescale.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-arm/arch-mx35/mmu.h | 17 | ||||
| -rw-r--r-- | include/configs/mx35_3stack.h | 16 | ||||
| -rw-r--r-- | include/configs/mx35_3stack_mmc.h | 16 |
3 files changed, 37 insertions, 12 deletions
diff --git a/include/asm-arm/arch-mx35/mmu.h b/include/asm-arm/arch-mx35/mmu.h index 1b15dba..6cdc44c 100644 --- a/include/asm-arm/arch-mx35/mmu.h +++ b/include/asm-arm/arch-mx35/mmu.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -138,10 +138,11 @@ union ARM_MMU_FIRST_LEVEL_DESCRIPTOR { */ inline unsigned long iomem_to_phys(unsigned long virt) { - if (virt < 0x08000000) - return (unsigned long)(virt | PHYS_SDRAM_1); - - if ((virt & 0xF0000000) == PHYS_SDRAM_1) + if (((virt & 0xF0000000) == PHYS_SDRAM_1) +#ifdef CONFIG_MX35_256M_RAM + || ((virt & 0xF0000000) == PHYS_SDRAM_2) +#endif + ) return (unsigned long)(virt & (~0x08000000)); return (unsigned long)virt; @@ -161,7 +162,11 @@ void *__ioremap(unsigned long offset, size_t size, unsigned long flags) if (1 == flags) { /* 0x88000000~0x87FFFFFF is uncacheable meory space which is mapped to SDRAM */ - if ((offset & 0xF0000000) == PHYS_SDRAM_1) + if ((offset & 0xF0000000) == PHYS_SDRAM_1 +#ifdef CONFIG_MX35_256M_RAM + || ((offset & 0xF0000000) == PHYS_SDRAM_2) +#endif + ) return (void *)(offset | 0x08000000); else return NULL; diff --git a/include/configs/mx35_3stack.h b/include/configs/mx35_3stack.h index 40bf5f8..d337e5d 100644 --- a/include/configs/mx35_3stack.h +++ b/include/configs/mx35_3stack.h @@ -185,11 +185,21 @@ /*----------------------------------------------------------------------- * Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_MX35_256M_RAM #define PHYS_SDRAM_1 CSD0_BASE_ADDR #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) -#define iomem_valid_addr(addr, size) \ - (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) +#ifdef CONFIG_MX35_256M_RAM + #define CONFIG_NR_DRAM_BANKS 2 + #define PHYS_SDRAM_2 CSD1_BASE_ADDR + #define PHYS_SDRAM_2_SIZE (128 * 1024 * 1024) + #define iomem_valid_addr(addr, size) \ + ((addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) \ + || (addr >= PHYS_SDRAM_2 && addr <= (PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE))) +#else + #define CONFIG_NR_DRAM_BANKS 1 + #define iomem_valid_addr(addr, size) \ + (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) +#endif /*----------------------------------------------------------------------- * FLASH and environment organization diff --git a/include/configs/mx35_3stack_mmc.h b/include/configs/mx35_3stack_mmc.h index 727f926..5c2ebf6 100644 --- a/include/configs/mx35_3stack_mmc.h +++ b/include/configs/mx35_3stack_mmc.h @@ -187,11 +187,21 @@ /*----------------------------------------------------------------------- * Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_MX35_256M_RAM #define PHYS_SDRAM_1 CSD0_BASE_ADDR #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) -#define iomem_valid_addr(addr, size) \ - (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) +#ifdef CONFIG_MX35_256M_RAM + #define CONFIG_NR_DRAM_BANKS 2 + #define PHYS_SDRAM_2 CSD1_BASE_ADDR + #define PHYS_SDRAM_2_SIZE (128 * 1024 * 1024) + #define iomem_valid_addr(addr, size) \ + ((addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) \ + || (addr >= PHYS_SDRAM_2 && addr <= (PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE))) +#else + #define CONFIG_NR_DRAM_BANKS 1 + #define iomem_valid_addr(addr, size) \ + (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) +#endif /* * MMC Configs |