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| author | Niklaus Giger <niklausgiger@gmx.ch> | 2007-06-27 18:11:38 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-07-04 10:14:07 +0200 |
| commit | f780b83316d9af1f61d71cc88b1917b387b9b995 (patch) | |
| tree | ebc742ebba52c7f3884e702bcdffb9a7630efa89 /include | |
| parent | 04e6c38b766eaa2f3287561563c9e215e0c3a0d4 (diff) | |
| download | u-boot-imx-f780b83316d9af1f61d71cc88b1917b387b9b995.zip u-boot-imx-f780b83316d9af1f61d71cc88b1917b387b9b995.tar.gz u-boot-imx-f780b83316d9af1f61d71cc88b1917b387b9b995.tar.bz2 | |
resubmit: ppc4xx: Remove sequoia/sequioa.h. Cleanup ppc440.h for PPC440EPX
Signed-off-by: Niklaus Giger <niklaus.giger@nestal.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/ppc440.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/include/ppc440.h b/include/ppc440.h index 76330f1..61c937d 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -1025,7 +1025,7 @@ #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */ #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -#define SDR_USB2D0CR 0x0320 +#define SDR0_USB2D0CR 0x0320 #define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC Master Selection */ #define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection */ #define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */ @@ -1423,7 +1423,7 @@ #define uicvr uic0vr #define uicvcr uic0vcr -#if defined(CONFIG_440SPE) +#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) /*----------------------------------------------------------------------------+ | Clock / Power-on-reset DCR's. +----------------------------------------------------------------------------*/ @@ -1492,9 +1492,11 @@ #define CPR0_OPBD_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1) #define CPR0_PERD 0xE0 +#if !defined(CONFIG_440EPX) #define CPR0_PERD_PERDV0_MASK 0x03000000 #define CPR0_PERD_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) #define CPR0_PERD_PERDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1) +#endif #define CPR0_MALD 0x100 #define CPR0_MALD_MALDV0_MASK 0x03000000 |