ENGR00118576 MX25: Support Smc911x ethernet

1. Add imx cspi support for cpld access.
2. Add smc911x ethernet support from cpld.

Signed-off-by: Sammy He <r62914@freescale.com>

7 files changed, 97 insertions, 22 deletions

diff --git a/include/asm-arm/arch-mx25/imx_spi_cpld.h b/include/asm-arm/arch-mx25/imx_spi_cpld.h
new file mode 100644
index 0000000..f0fa00c
--- /dev/null
+++ b/include/asm-arm/arch-mx25/imx_spi_cpld.h
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _IMX_SPI_CPLD_H_
+#define _IMX_SPI_CPLD_H_
+
+#include <linux/types.h>
+
+extern struct spi_slave *spi_cpld_probe();
+extern void spi_cpld_free(struct spi_slave *slave);
+extern unsigned int cpld_reg_xfer(unsigned int reg, unsigned int val,
+				  unsigned int read);
+
+#endif				/* _IMX_SPI_CPLD_H_ */
diff --git a/include/asm-arm/arch-mx25/mx25.h b/include/asm-arm/arch-mx25/mx25.h
index 60e0de0..a51b893 100644
--- a/include/asm-arm/arch-mx25/mx25.h
+++ b/include/asm-arm/arch-mx25/mx25.h
@@ -36,6 +36,7 @@ enum mxc_clock {
 	MXC_IPG_CLK,
 	MXC_IPG_PERCLK,
 	MXC_UART_CLK,
+	MXC_CSPI_CLK
 };
 
 extern unsigned int mx25_get_ipg_clk(void);
diff --git a/include/configs/mx25_3stack.h b/include/configs/mx25_3stack.h
index 8272cbe..aa24d53 100644
--- a/include/configs/mx25_3stack.h
+++ b/include/configs/mx25_3stack.h
@@ -39,6 +39,10 @@
 #define CONFIG_MX25_HCLK_FREQ	24000000
 #define CONFIG_MX25_CLK32	32768
 
+#define CONFIG_IMX_CSPI		1
+#define IMX_CSPI_VER_0_7	1
+#define CONFIG_IMX_SPI_CPLD
+
 /* IF iMX25 3DS V-1.0 define it */
 /* #define CONFIG_MX25_3DS_V10 */
 
@@ -122,23 +126,29 @@
 
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"							\
-	"ethprime=fec\0"						\
+	"ethprime=smc911x-0\0"						\
+	"uboot=u-boot.bin\0"						\
+	"uboot_addr=0xa0000000\0"					\
+	"kernel=uImage\0"						\
 	"bootargs_base=setenv bootargs console=ttymxc0,115200\0"	\
 	"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs "	\
 		"ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0"	\
 	"bootcmd=run bootcmd_net\0"					\
-	"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; "	\
-		"tftpboot 0x81000000 uImage; bootm\0"
+	"bootcmd_net=run bootargs_base bootargs_nfs; "			\
+		"tftpboot ${loadaddr} ${kernel}; bootm\0"		\
+	"load_uboot=tftpboot ${loadaddr} ${uboot}\0"
 
 /*Support LAN9217*/
-/*#define CONFIG_SMC911X   1
-#define CONFIG_SMC911X_16_BIT 1
-#define CONFIG_SMC911X_BASE CS5_BASE*/
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_CPLD
+#define CONFIG_SMC911X_BASE	0
 
-/*#define CONFIG_HAS_ETH1*/
+#define CONFIG_HAS_ETH1
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_DHCP
-#define CONFIG_NET_MULTI	1
+#define CONFIG_NET_MULTI
+#define CONFIG_ETH_PRIME
+
 #define CONFIG_MXC_FEC
 #define CONFIG_MII
 #define CONFIG_DISCOVER_PHY
diff --git a/include/configs/mx51_3stack_android.h b/include/configs/mx51_3stack_android.h
index 7661713..04bcbb8 100644
--- a/include/configs/mx51_3stack_android.h
+++ b/include/configs/mx51_3stack_android.h
@@ -77,10 +77,10 @@
 #define CONFIG_CMD_SF
 #define CONFIG_SPI_FLASH_IMX_ATMEL	1
 #define CONFIG_SPI_FLASH_CS	1
-#define CONFIG_IMX_SPI
+#define CONFIG_IMX_ECSPI
 #define CONFIG_IMX_SPI_PMIC
 #define CONFIG_IMX_SPI_PMIC_CS 0
-
+#define IMX_CSPI_VER_2_3	1
 #define MAX_SPI_BYTES		(64 * 4)
 */
 
diff --git a/include/configs/mx51_bbg.h b/include/configs/mx51_bbg.h
index 64f0e2b..e00ae62 100644
--- a/include/configs/mx51_bbg.h
+++ b/include/configs/mx51_bbg.h
@@ -73,10 +73,10 @@
 #define CONFIG_FSL_SF		1
 #define CONFIG_SPI_FLASH_IMX_ATMEL	1
 #define CONFIG_SPI_FLASH_CS	1
-#define CONFIG_IMX_SPI
+#define CONFIG_IMX_ECSPI
 #define CONFIG_IMX_SPI_PMIC
-#define CONFIG_IMX_SPI_PMIC_CS 0
-
+#define CONFIG_IMX_SPI_PMIC_CS	0
+#define	IMX_CSPI_VER_2_3	1
 #define MAX_SPI_BYTES		(64 * 4)
 
 /*
diff --git a/include/configs/mx51_bbg_android.h b/include/configs/mx51_bbg_android.h
index f791f4d..24ffc6c 100644
--- a/include/configs/mx51_bbg_android.h
+++ b/include/configs/mx51_bbg_android.h
@@ -227,9 +227,10 @@
 #define CONFIG_CMD_SF
 #define CONFIG_SPI_FLASH_IMX_ATMEL	1
 #define CONFIG_SPI_FLASH_CS	1
-#define CONFIG_IMX_SPI
+#define CONFIG_IMX_ECSPI
 #define CONFIG_IMX_SPI_PMIC
 #define CONFIG_IMX_SPI_PMIC_CS 0
+#define IMX_CSPI_VER_2_3        1
 
 #define MAX_SPI_BYTES		(64 * 4)
 
diff --git a/include/asm-arm/arch-mx51/imx_spi.h b/include/imx_spi.h
index c9d51e9..e4f6444 100644
--- a/include/asm-arm/arch-mx51/imx_spi.h
+++ b/include/imx_spi.h
@@ -31,14 +31,44 @@
 #define IMX_SPI_ACTIVE_LOW      0
 #define SPI_RETRY_TIMES         100
 
-#define	SPI_RX_DATA				0x0
-#define SPI_TX_DATA				0x4
-#define SPI_CON_REG				0x8
-#define SPI_CFG_REG				0xc
-#define SPI_INT_REG				0x10
-#define SPI_DMA_REG				0x14
-#define SPI_STAT_REG				0x18
-#define SPI_PERIOD_REG				0x1C
+#if defined(IMX_CSPI_VER_0_7)
+	#define	SPI_RX_DATA		0x0
+	#define SPI_TX_DATA		0x4
+	#define SPI_CON_REG		0x8
+	#define SPI_INT_REG		0xC
+	#define SPI_DMA_REG		0x10
+	#define SPI_STAT_REG		0x14
+	#define SPI_PERIOD_REG		0x18
+
+	#define SPI_CTRL_EN		(1 << 0)
+	#define SPI_CTRL_MODE		(1 << 1)
+	#define SPI_CTRL_REG_XCH_BIT	(1 << 2)
+	#define SPI_CTRL_SSPOL		(1 << 7)
+	#define SPI_CTRL_SSPOL_OFF	(7)
+	#define SPI_CTRL_SSCTL		(1 << 6)
+	#define SPI_CTRL_SSCTL_OFF	(6)
+	#define SPI_CTRL_SCLK_POL	(1 << 4)
+	#define SPI_CTRL_SCLK_POL_OFF	(4)
+	#define SPI_CTRL_SCLK_PHA	(1 << 5)
+	#define SPI_CTRL_SCLK_PHA_OFF	(5)
+	#define SPI_CTRL_SS_OFF		(12)
+	#define SPI_CTRL_SS_MASK	(3 << 12)
+	#define SPI_CTRL_DATA_OFF	(16)
+	#define SPI_CTRL_DATA_MASK	(7 << 16)
+	#define SPI_CTRL_BURST_OFF	(20)
+	#define SPI_CTRL_BURST_MASK	(0xFFF << 20)
+	#define SPI_INT_STAT_TC		(1 << 7)
+
+#elif defined(IMX_CSPI_VER_2_3)
+	#define	SPI_RX_DATA		0x0
+	#define SPI_TX_DATA		0x4
+	#define SPI_CON_REG		0x8
+	#define SPI_CFG_REG		0xC
+	#define SPI_INT_REG		0x10
+	#define SPI_DMA_REG		0x14
+	#define SPI_STAT_REG		0x18
+	#define SPI_PERIOD_REG		0x1C
+#endif
 
 struct spi_reg_t {
 	u32 ctrl_reg;