ENGR00113941 MX233: Make UBOOT v2009.01 work on EVK board

Porting MX233 UBOOT from 1.3.3 to V2009.01. Clear old cfg macro, such as
CFG_HZ. Change MAC address getting source from initial configuration to
On-Chip OTP.

Signed-off-by: Lionel Xu <r63889@freescale.com>

9 files changed, 628 insertions, 0 deletions

diff --git a/include/asm-arm/arch-stmp378x/clkctrl.h b/include/asm-arm/arch-stmp378x/clkctrl.h
new file mode 100644
index 0000000..4960707
--- /dev/null
+++ b/include/asm-arm/arch-stmp378x/clkctrl.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2008 Embedded Alley Solutions Inc.
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * Clock control register descriptions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef CLKCTRL_H
+#define CLKCTRL_H
+
+#include <asm/arch/stmp378x.h>
+
+#define CLKCTRL_BASE	(STMP378X_REGS_BASE + 0x40000)
+
+#define	CLKCTRL_PLLCTRL0	0x000
+#define	CLKCTRL_PLLCTRL1	0x010
+#define	CLKCTRL_CPU		0x020
+#define CLKCTRL_HBUS		0x030
+#define	CLKCTRL_XBUS		0x040
+#define	CLKCTRL_XTAL		0x050
+#define CLKCTRL_PIX		0x060
+#define	CLKCTRL_SSP		0x070
+#define	CLKCTRL_GPMI		0x080
+#define CLKCTRL_SPDIF		0x090
+#define	CLKCTRL_EMI		0x0a0
+#define	CLKCTRL_IR		0x0b0
+#define CLKCTRL_SAIF		0x0c0
+#define	CLKCTRL_TV		0x0d0
+#define	CLKCTRL_ETM		0x0e0
+#define	CLKCTRL_FRAC		0x0f0
+#define	CLKCTRL_FRAC1		0x100
+#define CLKCTRL_CLKSEQ		0x110
+#define	CLKCTRL_RESET		0x120
+#define	CLKCTRL_STATUS		0x130
+#define CLKCTRL_VERSION		0x140
+
+/* CLKCTRL_SSP register bits, bit fields and values */
+#define	SSP_CLKGATE	(1 << 31)
+#define	SSP_BUSY	(1 << 29)
+#define	SSP_DIV_FRAC_EN	(1 << 9)
+#define SSP_DIV		0
+
+/* CLKCTRL_FRAC register bits, bit fields and values */
+#define	FRAC_CLKGATEIO	(1 << 31)
+#define FRAC_IOFRAC	24
+
+/* CLKCTRL_FRAC register bits, bit fields and values */
+#define CLKSEQ_BYPASS_SSP	(1 << 5)
+
+#endif /* CLKCTRL_H */
diff --git a/include/asm-arm/arch-stmp378x/dbguart.h b/include/asm-arm/arch-stmp378x/dbguart.h
new file mode 100644
index 0000000..fc5d658
--- /dev/null
+++ b/include/asm-arm/arch-stmp378x/dbguart.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2008 Embedded Alley Solutions Inc.
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * Debug UART register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef DBGUART_H
+#define DBGUART_H
+
+#include <asm/arch/stmp378x.h>
+
+#define DBGUART_BASE	(STMP378X_REGS_BASE + 0x00070000)
+
+#endif /* DBGUART_H */
diff --git a/include/asm-arm/arch-stmp378x/ocotp.h b/include/asm-arm/arch-stmp378x/ocotp.h
new file mode 100644
index 0000000..b2b4062
--- /dev/null
+++ b/include/asm-arm/arch-stmp378x/ocotp.h
@@ -0,0 +1,69 @@
+/* Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * On-Chip OTP register descriptions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef OCOTP_H
+#define OCOTP_H
+
+#include <asm/arch/stmp378x.h>
+
+#define OCOTP_BASE	(STMP378X_REGS_BASE + 0x2c000)
+
+#define	OCOTP_CTRL		0x000
+#define	OCOTP_CTRL_SET		0x004
+#define	OCOTP_CTRL_CLR		0x008
+#define	OCOTP_CTRL_TOG		0x00c
+#define	OCOTP_DATA		0x010
+#define	OCOTP_CUST0		0x020
+#define	OCOTP_CUST1		0x030
+#define	OCOTP_CUST2		0x040
+#define	OCOTP_CUST3		0x050
+#define	OCOTP_CRYPTO1		0x070
+#define	OCOTP_CRYPTO2		0x080
+#define	OCOTP_CRYPTO3		0x090
+#define	OCOTP_HWCAP0		0x0a0
+#define	OCOTP_HWCAP1		0x0b0
+#define	OCOTP_HWCAP2		0x0c0
+#define	OCOTP_HWCAP3		0x0d0
+#define	OCOTP_HWCAP4		0x0e0
+#define	OCOTP_HWCAP5		0x0f0
+#define	OCOTP_SWCAP		0x100
+#define	OCOTP_CUSTCAP		0x110
+#define	OCOTP_LOCK		0x120
+#define	OCOTP_OPS0		0x130
+#define	OCOTP_OPS1		0x140
+#define	OCOTP_OPS2		0x150
+#define	OCOTP_OPS3		0x160
+#define	OCOTP_UN0		0x170
+#define	OCOTP_UN1		0x180
+#define	OCOTP_UN2		0x190
+#define	OCOTP_ROM0		0x1a0
+#define	OCOTP_ROM1		0x1b0
+#define	OCOTP_ROM2		0x1c0
+#define	OCOTP_ROM3		0x1d0
+#define	OCOTP_ROM4		0x1e0
+#define	OCOTP_ROM5		0x1f0
+#define	OCOTP_ROM6		0x200
+#define	OCOTP_ROM7		0x210
+#define	OCOTP_VERSION		0x220
+
+
+/* OCOTP_CTRL register bits, bit fields and values */
+#define CTRL_RD_BANK_OPEN	(1 << 12)
+#define CTRL_BUSY		(8 << 12)
+
+#endif /* OCOTP_H */
diff --git a/include/asm-arm/arch-stmp378x/pinmux.h b/include/asm-arm/arch-stmp378x/pinmux.h
new file mode 100644
index 0000000..3364bcb
--- /dev/null
+++ b/include/asm-arm/arch-stmp378x/pinmux.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2008 Embedded Alley Solutions Inc.
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * Clock control register descriptions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef PINMUX_H
+#define PINMUX_H
+
+#include <asm/arch/stmp378x.h>
+
+#define	PINCTRL_BASE	(STMP378X_REGS_BASE + 0x18000)
+
+#define PINCTRL_CTRL		0x000
+#define	PINCTRL_MUXSEL(n)	(0x100 + 0x10*(n))
+#define PINCTRL_DRIVE(n)	(0x200 + 0x10*(n))
+#define PINCTRL_PULL(n)		(0x400 + 0x10*(n))
+#define PINCTRL_DOUT(n)		(0x500 + 0x10*(n))
+#define PINCTRL_DIN(n)		(0x600 + 0x10*(n))
+#define PINCTRL_DOE(n)		(0x700 + 0x10*(n))
+#define PINCTRL_PIN2IRQ(n)	(0x800 + 0x10*(n))
+#define PINCTRL_IRQEN(n)	(0x900 + 0x10*(n))
+#define PINCTRL_IRQLEVEL(n)	(0xa00 + 0x10*(n))
+#define PINCTRL_IRQPOL(n)	(0xb00 + 0x10*(n))
+#define PINCTRL_IRQSTAT(n)	(0xc00 + 0x10*(n))
+
+#endif /* PINMUX_H */
diff --git a/include/asm-arm/arch-stmp378x/spi.h b/include/asm-arm/arch-stmp378x/spi.h
new file mode 100644
index 0000000..afd3245
--- /dev/null
+++ b/include/asm-arm/arch-stmp378x/spi.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2008 Embedded Alley Solutions Inc.
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * SSP/SPI driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef SPI_H
+#define SPI_H
+
+#include <config.h>
+#include <common.h>
+#include <asm/arch/ssp.h>
+
+/*
+ * Flags to set SPI mode
+ */
+#define SPI_PHASE	0x1 /* Set phase to 1 */
+#define SPI_POLARITY	0x2 /* Set polarity to 1 */
+
+/* Various flags to control SPI transfers */
+#define SPI_START	0x1	/* Lock CS signal */
+#define SPI_STOP	0x2	/* Unlock CS signal */
+
+/*
+ * Init SSPx interface, must be called first
+ */
+void spi_init(void);
+
+/*
+ * Set phase, polarity and CS number (SS0, SS1, SS2)
+ */
+void spi_set_cfg(unsigned int bus, unsigned int cs, unsigned long mode);
+
+
+/*
+ * Send @rx_len bytes from @dout, then receive @rx_len bytes
+ * saving them to @din
+ */
+void spi_txrx(const char *dout, unsigned int tx_len, char *din,
+	       unsigned int rx_len, unsigned long flags);
+
+
+/* Lock/unlock SPI bus */
+static inline void spi_lock(void)
+{
+	disable_interrupts();
+}
+
+static inline void spi_unlock(void)
+{
+	enable_interrupts();
+}
+
+#endif /* SPI_H */
diff --git a/include/asm-arm/arch-stmp378x/ssp.h b/include/asm-arm/arch-stmp378x/ssp.h
new file mode 100644
index 0000000..0cd58cb
--- /dev/null
+++ b/include/asm-arm/arch-stmp378x/ssp.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (C) 2008 Embedded Alley Solutions Inc.
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * SSP register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef SSP_H
+#define SSP_H
+
+#include <asm/arch/stmp378x.h>
+
+#define SSP1_BASE	(STMP378X_REGS_BASE + 0x10000)
+#define SSP2_BASE	(STMP378X_REGS_BASE + 0x34000)
+
+#define SSP_CTRL0	0x000
+#define SSP_CMD0	0x010
+#define SSP_CMD1	0x020
+#define SSP_COMPREF	0x030
+#define SSP_COMPMASK	0x040
+#define SSP_TIMING	0x050
+#define SSP_CTRL1	0x060
+#define SSP_DATA	0x070
+#define SSP_SDRESP0	0x080
+#define SSP_SDRESP1	0x090
+#define SSP_SDRESP2	0x0a0
+#define SSP_SDRESP3	0x0b0
+#define SSP_STATUS	0x0c0
+#define SSP_DEBUG	0x100
+#define SSP_VERSION	0x110
+
+/* CTRL0 bits, bit fields and values */
+#define CTRL0_SFTRST		(0x1 << 31)
+#define CTRL0_CLKGATE		(0x1 << 30)
+#define	CTRL0_RUN		(0x1 << 29)
+#define CTRL0_LOCK_CS		(0x1 << 27)
+#define CTRL0_IGNORE_CRC	(0x1 << 26)
+#define CTRL0_DATA_XFER		(0x1 << 24)
+#define CTRL0_READ		(0x1 << 25)
+#define CTRL0_BUS_WIDTH		22
+#define CTRL0_WAIT_FOR_IRQ	(0x1 << 21)
+#define CTRL0_WAIT_FOR_CMD	(0x1 << 20)
+#define CTRL0_XFER_COUNT	0
+
+#define BUS_WIDTH_SPI1	(0x0 << CTRL0_BUS_WIDTH)
+#define BUS_WIDTH_SPI4	(0x1 << CTRL0_BUS_WIDTH)
+#define BUS_WIDTH_SPI8	(0x2 << CTRL0_BUS_WIDTH)
+
+#define SPI_CS0		0x0
+#define SPI_CS1		CTRL0_WAIT_FOR_CMD
+#define SPI_CS2		CTRL0_WAIT_FOR_IRQ
+#define SPI_CS_CLR_MASK	(CTRL0_WAIT_FOR_CMD | CTRL0_WAIT_FOR_IRQ)
+
+/* CMD0 bits, bit fields and values */
+#define CMD0_BLOCK_SIZE		16
+#define CMD0_BLOCK_COUNT	12
+#define CMD0_CMD		0
+
+/* TIMING bits, bit fields and values */
+#define TIMING_TIMEOUT		16
+#define TIMING_CLOCK_DIVIDE	8
+#define TIMING_CLOCK_RATE	0
+
+/* CTRL1 bits, bit fields and values */
+#define CTRL1_DMA_ENABLE	(0x1 << 13)
+#define CTRL1_PHASE		(0x1 << 10)
+#define CTRL1_POLARITY		(0x1 << 9)
+#define CTRL1_SLAVE_MODE	(0x1 << 8)
+#define CTRL1_WORD_LENGTH	4
+#define CTRL1_SSP_MODE		0
+
+#define WORD_LENGTH4	(0x3 << CTRL1_WORD_LENGTH)
+#define WORD_LENGTH8	(0x7 << CTRL1_WORD_LENGTH)
+#define WORD_LENGTH16	(0xF << CTRL1_WORD_LENGTH)
+
+#define SSP_MODE_SPI	(0x0 << CTRL1_SSP_MODE)
+#define SSP_MODE_SSI	(0x1 << CTRL1_SSP_MODE)
+#define SSP_MODE_SD_MMC	(0x3 << CTRL1_SSP_MODE)
+#define SSP_MODE_MS	(0x4 << CTRL1_SSP_MODE)
+#define SSP_MODE_ATA	(0x7 << CTRL1_SSP_MODE)
+
+/* CTRL1 bits, bit fields and values */
+#define STATUS_FIFO_EMPTY	(1 << 5)
+#define STATUS_FIFO_FULL	(1 << 8)
+
+#endif /* SSP_H */
diff --git a/include/asm-arm/arch-stmp378x/stmp378x.h b/include/asm-arm/arch-stmp378x/stmp378x.h
new file mode 100644
index 0000000..f425185
--- /dev/null
+++ b/include/asm-arm/arch-stmp378x/stmp378x.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2008 Embedded Alley Solutions Inc.
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef STMP378X_H
+#define STMP378X_H
+
+/*
+ * Most of 378x SoC registers are associated with four addresses
+ * used for different operations - read/write, set, clear and toggle bits.
+ *
+ * Some of registers do not implement such feature and, thus, should be
+ * accessed/manipulated via single address in common way.
+ */
+#define REG_RD(x)	(*(volatile unsigned int *)(x))
+#define REG_WR(x, v)	((*(volatile unsigned int *)(x)) = (v))
+#define REG_SET(x, v)	((*(volatile unsigned int *)((x) + 0x04)) = (v))
+#define REG_CLR(x, v)	((*(volatile unsigned int *)((x) + 0x08)) = (v))
+#define REG_TOG(x, v)	((*(volatile unsigned int *)((x) + 0x0c)) = (v))
+
+#define STMP378X_OCRAM_BASE	0x00000000
+#define STMP378X_SDRAM_BASE	0x40000000
+#define STMP378X_REGS_BASE	0x80000000
+
+#endif /* STMP378X_H */
diff --git a/include/asm-arm/arch-stmp378x/timrot.h b/include/asm-arm/arch-stmp378x/timrot.h
new file mode 100644
index 0000000..c8c5e33
--- /dev/null
+++ b/include/asm-arm/arch-stmp378x/timrot.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2008 Embedded Alley Solutions Inc.
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * Timers and rotary encoder register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef TIMROT_H
+#define TIMROT_H
+
+#include <asm/arch/stmp378x.h>
+
+#define TIMROT_BASE	(STMP378X_REGS_BASE + 0x00068000)
+
+/* Timer and rotary encoder register offsets */
+#define ROTCTRL		0x0
+#define ROTCOUNT	0x10
+#define TIMCTRL0	0x20
+#define TIMCOUNT0	0x30
+#define TIMCTRL1	0x40
+#define TIMCOUNT1	0x50
+#define TIMCTRL2	0x60
+#define TIMCOUNT2	0x70
+#define TIMCTRL3	0x80
+#define TIMCTRL3	0x90
+
+/* TIMCTRL bits, bit fields and values */
+#define TIMCTRL_SELECT		0
+#define TIMCTRL_PRESCALE	4
+#define TIMCTRL_RELOAD		(1 << 6)
+#define TIMCTRL_UPDATE		(1 << 7)
+#define TIMCTRL_POLARITY	(1 << 8)
+#define TIMCTRL_IRQEN		(1 << 14)
+#define TIMCTRL_IRQ		(1 << 15)
+
+#define TIMCTRL_SELECT_PWM0	(0x1 << TIMCTRL_SELECT)
+#define TIMCTRL_SELECT_PWM1	(0x2 << TIMCTRL_SELECT)
+#define TIMCTRL_SELECT_PWM2	(0x3 << TIMCTRL_SELECT)
+#define TIMCTRL_SELECT_PWM3	(0x4 << TIMCTRL_SELECT)
+#define TIMCTRL_SELECT_PWM4	(0x5 << TIMCTRL_SELECT)
+#define TIMCTRL_SELECT_ROTARYA	(0x6 << TIMCTRL_SELECT)
+#define TIMCTRL_SELECT_ROTARYB	(0x7 << TIMCTRL_SELECT)
+#define TIMCTRL_SELECT_32KHZ	(0x8 << TIMCTRL_SELECT)
+#define TIMCTRL_SELECT_8KHZ	(0x9 << TIMCTRL_SELECT)
+#define TIMCTRL_SELECT_4KHZ	(0xa << TIMCTRL_SELECT)
+#define TIMCTRL_SELECT_1KHZ	(0xb << TIMCTRL_SELECT)
+#define TIMCTRL_SELECT_ALWAYS	(0xc << TIMCTRL_SELECT)
+
+#endif /* TIMROT_H */
diff --git a/include/configs/stmp378x_dev.h b/include/configs/stmp378x_dev.h
new file mode 100644
index 0000000..c0368c3
--- /dev/null
+++ b/include/configs/stmp378x_dev.h
@@ -0,0 +1,151 @@
+/*
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/sizes.h>
+
+/*
+ * Define this to make U-Boot skip low level initialization when loaded
+ * by initial bootloader. Not required by NAND U-Boot version but IS
+ * required for a NOR version used to burn the real NOR U-Boot into
+ * NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive
+ * so it is NOT possible to build a U-Boot with both NAND and NOR routines.
+ * NOR U-Boot is loaded directly from Flash so it must perform all the
+ * low level initialization itself. NAND version is loaded by an initial
+ * bootloader (UBL in TI-ese) that performs such an initialization so it's
+ * skipped in NAND version. The third DaVinci boot mode loads a bootloader
+ * via UART0 and that bootloader in turn loads and runs U-Boot (or whatever)
+ * performing low level init prior to loading. All that means we can NOT use
+ * NAND version to put U-Boot into NOR because it doesn't have NOR support and
+ * we can NOT use NOR version because it performs low level initialization
+ * effectively destroying itself in DDR memory. That's why a separate NOR
+ * version with this define is needed. It is loaded via UART, then one uses
+ * it to somehow download a proper NOR version built WITHOUT this define to
+ * RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze
+ * NOR support into the initial bootloader so it won't be needed but DaVinci
+ * static RAM might be too small for this (I have something like 2Kbytes left
+ * as of now, without NOR support) so this might've not happened...
+ *
+ */
+
+/*===================*/
+/* SoC Configuration */
+/*===================*/
+#define CONFIG_ARM926EJS			/* arm926ejs CPU core */
+#define CONFIG_STMP378X				/* STMP378x SoC */
+#define CONFIG_STMP378X_DEV			/* STMP378x Development board */
+#define CONFIG_SYS_CLK_FREQ	120000000	/* Arm Clock frequency */
+#define CONFIG_USE_TIMER0			/* use timer 0 */
+#define CONFIG_SYS_HZ		1000		/* Ticks per second */
+/*=============*/
+/* Memory Info */
+/*=============*/
+#define CONFIG_SYS_MALLOC_LEN	(0x10000 + 128*1024)	/* malloc() len */
+#define CONFIG_SYS_GBL_DATA_SIZE 128		/* reserved for initial data */
+#define CONFIG_SYS_MEMTEST_START 0x40000000	/* memtest start address */
+#define CONFIG_SYS_MEMTEST_END	 0x41000000	/* 16MB RAM test */
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE	(256*1024)	/* regular stack */
+#define PHYS_SDRAM_1		0x40000000	/* mDDR Start */
+#define PHYS_SDRAM_1_SIZE	0x02000000	/* mDDR size 32MB */
+
+/*====================*/
+/* Serial Driver info */
+/*====================*/
+#define CONFIG_STMP3XXX_DBGUART			/* 378x debug UART */
+#define CONFIG_DBGUART_CLK	24000000
+#define CONFIG_BAUDRATE		115200		/* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*====================*/
+/* SPI Driver info */
+/*====================*/
+#define CONFIG_SSP_CLK		48000000
+#define CONFIG_SPI_CLK		3000000
+#define CONFIG_SPI_SSP1
+#undef CONFIG_SPI_SSP2
+
+/*=====================*/
+/* Flash & Environment */
+/*=====================*/
+#define CONFIG_SYS_NO_FLASH			/* Flash is not supported */
+#define CONFIG_ENV_IS_NOWHERE		/* Store ENV in memory only */
+#define CONFIG_ENV_SIZE		0x20000
+
+/*==============================*/
+/* U-Boot general configuration */
+/*==============================*/
+#undef	CONFIG_USE_IRQ				/* No IRQ/FIQ in U-Boot */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		192.167.10.2
+#define CONFIG_SERVERIP		192.167.10.1
+#define CONFIG_BOOTDELAY	2
+#define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
+#define CONFIG_SYS_PROMPT	"stmp378x U-Boot > "
+						/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size  */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+						/* Print buffer sz */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+						/* Boot Argument Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR	0x40400000
+				/* default Linux kernel load address */
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE	/* Won't work with hush so far, may be later */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_CMDLINE_EDITING
+#define CFG_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/*===================*/
+/* Linux Information */
+/*===================*/
+#define LINUX_BOOT_PARAM_ADDR	0x40000100
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTARGS		"console=ttyAM0,115200n8 "\
+			"root=/dev/mtdblock1 rootfstype=jffs2 lcd_panel=lms350"
+#define CONFIG_BOOTCOMMAND	"tftpboot ; bootm"
+
+/*=================*/
+/* U-Boot commands */
+/*=================*/
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#undef CONFIG_CMD_DIAG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_SAVES
+#undef CONFIG_CMD_IMLS
+
+/* Ethernet chip - select an alternative driver */
+#define CONFIG_ENC28J60_ETH
+#define CONFIG_ENC28J60_ETH_SPI_BUS	0
+#define CONFIG_ENC28J60_ETH_SPI_CS	0
+
+#endif /* __CONFIG_H */