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authorwdenk <wdenk>2003-08-28 09:41:22 +0000
committerwdenk <wdenk>2003-08-28 09:41:22 +0000
commitd94f92cbd7f4a4d3bf0d5d963b709c686e8f6633 (patch)
treec85dd4a10c5a68ca09b9139c1b6428d55ada6451 /include
parente0ac62d798ce60ec5d43125d4786e58b0d881836 (diff)
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* Fix ICU862 environment problem
* Fix RAM size detection for RMU board * Implement "reset" for MGT5100/MPC5200 systems
Diffstat (limited to 'include')
-rw-r--r--include/configs/ICU862.h2
-rw-r--r--include/configs/IceCube.h2
-rw-r--r--include/configs/rmu.h8
-rw-r--r--include/mpc5xxx.h5
-rw-r--r--include/version.h2
5 files changed, 11 insertions, 8 deletions
diff --git a/include/configs/ICU862.h b/include/configs/ICU862.h
index a7a11a6..fea0fce 100644
--- a/include/configs/ICU862.h
+++ b/include/configs/ICU862.h
@@ -196,7 +196,7 @@
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
#endif
#else
-#define CFG_MONITOR_LEN (272 << 10) /* Reserve 272 kB for Monitor */
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#endif
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h
index 6a43441..352beae 100644
--- a/include/configs/IceCube.h
+++ b/include/configs/IceCube.h
@@ -131,9 +131,7 @@
*/
#define CFG_MBAR 0xf0000000
#define CFG_SDRAM_BASE 0x00000000
-#ifdef CONFIG_MPC5200
#define CFG_DEFAULT_MBAR 0x80000000
-#endif
/* Use SRAM until RAM will be available */
#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
diff --git a/include/configs/rmu.h b/include/configs/rmu.h
index 0a94714..7b33c7e 100644
--- a/include/configs/rmu.h
+++ b/include/configs/rmu.h
@@ -291,12 +291,12 @@
*
*/
#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
-#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */
+#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB */
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
#define CFG_OR_TIMING_SDRAM 0x00000E00
-#define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_OR1_PRELIM (0xF0000000 | CFG_OR_TIMING_SDRAM ) /* map 256 MB */
#define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
/* RPXLITE mem setting */
@@ -321,8 +321,8 @@
* MAMR settings for SDRAM
*/
-/* 10 column SDRAM */
-#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X)
diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h
index b803d03..4218b05 100644
--- a/include/mpc5xxx.h
+++ b/include/mpc5xxx.h
@@ -78,6 +78,7 @@
#define MPC5XXX_CDM (CFG_MBAR + 0x0200)
#define MPC5XXX_LPB (CFG_MBAR + 0x0300)
#define MPC5XXX_ICTL (CFG_MBAR + 0x0500)
+#define MPC5XXX_GPT (CFG_MBAR + 0x0600)
#define MPC5XXX_GPIO (CFG_MBAR + 0x0b00)
#define MPC5XXX_PCI (CFG_MBAR + 0x0d00)
#define MPC5XXX_SDMA (CFG_MBAR + 0x1200)
@@ -183,6 +184,10 @@
#define MPC5XXX_ICTL_PER_STS (MPC5XXX_ICTL + 0x0030)
#define MPC5XXX_ICTL_BUS_STS (MPC5XXX_ICTL + 0x0038)
+/* General Purpose Timers registers */
+#define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0)
+#define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4)
+
/* Programmable Serial Controller (PSC) status register bits */
#define PSC_SR_CDE 0x0080
#define PSC_SR_RXRDY 0x0100
diff --git a/include/version.h b/include/version.h
index 5ba8488..d295c2a 100644
--- a/include/version.h
+++ b/include/version.h
@@ -24,6 +24,6 @@
#ifndef __VERSION_H__
#define __VERSION_H__
-#define U_BOOT_VERSION "U-Boot 0.4.6"
+#define U_BOOT_VERSION "U-Boot 0.4.7"
#endif /* __VERSION_H__ */