Merge with /home/wd/git/u-boot/master

11 files changed, 1891 insertions, 108 deletions

diff --git a/include/asm-m68k/immap_5282.h b/include/asm-m68k/immap_5282.h
index f2b77db..6553b08 100644
--- a/include/asm-m68k/immap_5282.h
+++ b/include/asm-m68k/immap_5282.h
@@ -13,7 +13,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -25,39 +25,61 @@
 #ifndef __IMMAP_5282__
 #define __IMMAP_5282__
 
+struct sys_ctrl {
+	uint ipsbar;
+	char res1[4];
+	uint rambar;
+	char res2[4];
+	uchar crsr;
+	uchar cwcr;
+	uchar lpicr;
+	uchar cwsr;
+	uint dmareqc;
+	char res3[4];
+	uint mpark;
+
+    /* TODO: finish these */
+};
 
 /* Fast ethernet controller registers
  */
 typedef struct fec {
-	uint	fec_ecntrl;		/* ethernet control register		*/
-	uint	fec_ievent;		/* interrupt event register		*/
-	uint	fec_imask;		/* interrupt mask register		*/
-	uint	fec_ivec;		/* interrupt level and vector status	*/
-	uint	fec_r_des_active;	/* Rx ring updated flag			*/
-	uint	fec_x_des_active;	/* Tx ring updated flag			*/
-	uint	res3[10];		/* reserved				*/
-	uint	fec_mii_data;		/* MII data register			*/
-	uint	fec_mii_speed;		/* MII speed control register		*/
-	uint	res4[17];		/* reserved				*/
-	uint	fec_r_bound;		/* end of RAM (read-only)		*/
-	uint	fec_r_fstart;		/* Rx FIFO start address		*/
-	uint	res5[6];		/* reserved				*/
-	uint	fec_x_fstart;		/* Tx FIFO start address		*/
-	uint	res7[21];		/* reserved				*/
-	uint	fec_r_cntrl;		/* Rx control register			*/
-	uint	fec_r_hash;		/* Rx hash register			*/
-	uint	res8[14];		/* reserved				*/
-	uint	fec_x_cntrl;		/* Tx control register			*/
-	uint	res9[0x9e];		/* reserved				*/
-	uint	fec_addr_low;		/* lower 32 bits of station address	*/
-	uint	fec_addr_high;		/* upper 16 bits of station address	*/
-	uint	fec_hash_table_high;	/* upper 32-bits of hash table		*/
-	uint	fec_hash_table_low;	/* lower 32-bits of hash table		*/
-	uint	fec_r_des_start;	/* beginning of Rx descriptor ring	*/
-	uint	fec_x_des_start;	/* beginning of Tx descriptor ring	*/
-	uint	fec_r_buff_size;	/* Rx buffer size			*/
-	uint	res2[9];		/* reserved				*/
-	uchar	fec_fifo[960];		/* fifo RAM				*/
+	uint	res1;		/* reserved			1000*/
+	uint	fec_ievent;	/* interrupt event register	1004*/	/* EIR */
+	uint	fec_imask;	/* interrupt mask register	1008*/	/* EIMR */
+	uint	res2;		/* reserved			100c*/
+	uint	fec_r_des_active;    /* Rx ring updated flag	1010*/	/* RDAR */
+	uint	fec_x_des_active;    /* Tx ring updated flag	1014*/	/* XDAR */
+	uint	res3[3];	/* reserved			1018*/
+	uint	fec_ecntrl;	/* ethernet control register	1024*/	/* ECR */
+	uint	res4[6];	/* reserved			1028*/
+	uint	fec_mii_data;	/* MII data register		1040*/	/* MDATA */
+	uint	fec_mii_speed;	/* MII speed control register	1044*/	/* MSCR */
+				      /*1044*/
+	uint	res5[7];	/* reserved			1048*/
+	uint	fec_mibc;	/* MIB Control/Status register	1064*/ /* MIBC */
+	uint	res6[7];	/* reserved			1068*/
+	uint	fec_r_cntrl;	/* Rx control register		1084*/	/* RCR */
+	uint	res7[15];	/* reserved			1088*/
+	uint	fec_x_cntrl;	/* Tx control register		10C4*/	/* TCR */
+	uint	res8[7];	/* reserved			10C8*/
+	uint	fec_addr_low;	/* lower 32 bits of station address */	/* PALR */
+	uint	fec_addr_high;	/* upper 16 bits of station address  */ /* PAUR */
+	uint	fec_opd;	/* opcode + pause duration	10EC*/	/* OPD */
+	uint	res9[10];	/* reserved			10F0*/
+	uint	fec_ihash_table_high;	/* upper 32-bits of individual hash */ /* IAUR */
+	uint	fec_ihash_table_low;	/* lower 32-bits of individual hash */ /* IALR */
+	uint	fec_ghash_table_high;	/* upper 32-bits of group hash	*/ /* GAUR */
+	uint	fec_ghash_table_low;	/* lower 32-bits of group hash	*/ /* GALR */
+	uint	res10[7];	/* reserved			1128*/
+	uint	fec_tfwr;	/* Transmit FIFO watermark	1144*/	/* TFWR */
+	uint	res11;		/* reserved			1148*/
+	uint	fec_r_bound;	/* FIFO Receive Bound Register = end of */ /* FRBR */
+	uint	fec_r_fstart;	/* FIFO Receive FIfo Start Registers =	*/ /* FRSR */
+	uint	res12[11];	/* reserved			1154*/
+	uint	fec_r_des_start;/* beginning of Rx descriptor ring    1180*/ /* ERDSR */
+	uint	fec_x_des_start;/* beginning of Tx descriptor ring    1184*/ /* ETDSR */
+	uint	fec_r_buff_size;/* Rx buffer size		1188*/	/* EMRBR */
 } fec_t;
 
 #endif /* __IMMAP_5282__ */
diff --git a/include/asm-m68k/m5282.h b/include/asm-m68k/m5282.h
index 073b0bc..e5058a4 100644
--- a/include/asm-m68k/m5282.h
+++ b/include/asm-m68k/m5282.h
@@ -1,9 +1,6 @@
 /*
  * mcf5282.h -- Definitions for Motorola Coldfire 5282
  *
- * Based on mcf5282sim.h of uCLinux distribution:
- *      (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
- *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -34,27 +31,515 @@
 
 #define INT_RAM_SIZE	65536
 
+/* General Purpose I/O Module GPIO */
 
-/*
- *	Define the 5282 SIM register set addresses.
- */
-#define	MCFICM_INTC0		0x0c00		/* Base for Interrupt Ctrl 0 */
-#define	MCFICM_INTC1		0x0d00		/* Base for Interrupt Ctrl 0 */
-#define	MCFINTC_IPRH		0x00		/* Interrupt pending 32-63 */
-#define	MCFINTC_IPRL		0x04		/* Interrupt pending 1-31 */
-#define	MCFINTC_IMRH		0x08		/* Interrupt mask 32-63 */
-#define	MCFINTC_IMRL		0x0c		/* Interrupt mask 1-31 */
-#define	MCFINTC_INTFRCH		0x10		/* Interrupt force 32-63 */
-#define	MCFINTC_INTFRCL		0x14		/* Interrupt force 1-31 */
-#define	MCFINTC_IRLR		0x18		/* */
-#define	MCFINTC_IACKL		0x19		/* */
-#define	MCFINTC_ICR0		0x40		/* Base ICR register */
-
-#define	MCFINT_UART0		13		/* Interrupt number for UART0 */
-#define	MCFINT_PIT1		55		/* Interrupt number for PIT1 */
-
-#define	MCF5282_GPIO_PUAPAR	0x10005C
+#define MCFGPIO_PORTA		(*(vu_char *) (CFG_MBAR+0x100000))
+#define MCFGPIO_PORTB		(*(vu_char *) (CFG_MBAR+0x100001))
+#define MCFGPIO_PORTC		(*(vu_char *) (CFG_MBAR+0x100002))
+#define MCFGPIO_PORTD		(*(vu_char *) (CFG_MBAR+0x100003))
+#define MCFGPIO_PORTE		(*(vu_char *) (CFG_MBAR+0x100004))
+#define MCFGPIO_PORTF		(*(vu_char *) (CFG_MBAR+0x100005))
+#define MCFGPIO_PORTG		(*(vu_char *) (CFG_MBAR+0x100006))
+#define MCFGPIO_PORTH		(*(vu_char *) (CFG_MBAR+0x100007))
+#define MCFGPIO_PORTJ		(*(vu_char *) (CFG_MBAR+0x100008))
+#define MCFGPIO_PORTDD		(*(vu_char *) (CFG_MBAR+0x100009))
+#define MCFGPIO_PORTEH		(*(vu_char *) (CFG_MBAR+0x10000A))
+#define MCFGPIO_PORTEL		(*(vu_char *) (CFG_MBAR+0x10000B))
+#define MCFGPIO_PORTAS		(*(vu_char *) (CFG_MBAR+0x10000C))
+#define MCFGPIO_PORTQS		(*(vu_char *) (CFG_MBAR+0x10000D))
+#define MCFGPIO_PORTSD		(*(vu_char *) (CFG_MBAR+0x10000E))
+#define MCFGPIO_PORTTC		(*(vu_char *) (CFG_MBAR+0x10000F))
+#define MCFGPIO_PORTTD		(*(vu_char *) (CFG_MBAR+0x100010))
+#define MCFGPIO_PORTUA		(*(vu_char *) (CFG_MBAR+0x100011))
+
+#define MCFGPIO_DDRA		(*(vu_char *) (CFG_MBAR+0x100014))
+#define MCFGPIO_DDRB		(*(vu_char *) (CFG_MBAR+0x100015))
+#define MCFGPIO_DDRC		(*(vu_char *) (CFG_MBAR+0x100016))
+#define MCFGPIO_DDRD		(*(vu_char *) (CFG_MBAR+0x100017))
+#define MCFGPIO_DDRE		(*(vu_char *) (CFG_MBAR+0x100018))
+#define MCFGPIO_DDRF		(*(vu_char *) (CFG_MBAR+0x100019))
+#define MCFGPIO_DDRG		(*(vu_char *) (CFG_MBAR+0x10001A))
+#define MCFGPIO_DDRH		(*(vu_char *) (CFG_MBAR+0x10001B))
+#define MCFGPIO_DDRJ		(*(vu_char *) (CFG_MBAR+0x10001C))
+#define MCFGPIO_DDRDD		(*(vu_char *) (CFG_MBAR+0x10001D))
+#define MCFGPIO_DDREH		(*(vu_char *) (CFG_MBAR+0x10001E))
+#define MCFGPIO_DDREL		(*(vu_char *) (CFG_MBAR+0x10001F))
+#define MCFGPIO_DDRAS		(*(vu_char *) (CFG_MBAR+0x100020))
+#define MCFGPIO_DDRQS		(*(vu_char *) (CFG_MBAR+0x100021))
+#define MCFGPIO_DDRSD		(*(vu_char *) (CFG_MBAR+0x100022))
+#define MCFGPIO_DDRTC		(*(vu_char *) (CFG_MBAR+0x100023))
+#define MCFGPIO_DDRTD		(*(vu_char *) (CFG_MBAR+0x100024))
+#define MCFGPIO_DDRUA		(*(vu_char *) (CFG_MBAR+0x100025))
+
+#define MCFGPIO_PORTAP		(*(vu_char *) (CFG_MBAR+0x100028))
+#define MCFGPIO_PORTBP		(*(vu_char *) (CFG_MBAR+0x100029))
+#define MCFGPIO_PORTCP		(*(vu_char *) (CFG_MBAR+0x10002A))
+#define MCFGPIO_PORTDP		(*(vu_char *) (CFG_MBAR+0x10002B))
+#define MCFGPIO_PORTEP		(*(vu_char *) (CFG_MBAR+0x10002C))
+#define MCFGPIO_PORTFP		(*(vu_char *) (CFG_MBAR+0x10002D))
+#define MCFGPIO_PORTGP		(*(vu_char *) (CFG_MBAR+0x10002E))
+#define MCFGPIO_PORTHP		(*(vu_char *) (CFG_MBAR+0x10002F))
+#define MCFGPIO_PORTJP		(*(vu_char *) (CFG_MBAR+0x100030))
+#define MCFGPIO_PORTDDP		(*(vu_char *) (CFG_MBAR+0x100031))
+#define MCFGPIO_PORTEHP		(*(vu_char *) (CFG_MBAR+0x100032))
+#define MCFGPIO_PORTELP		(*(vu_char *) (CFG_MBAR+0x100033))
+#define MCFGPIO_PORTASP		(*(vu_char *) (CFG_MBAR+0x100034))
+#define MCFGPIO_PORTQSP		(*(vu_char *) (CFG_MBAR+0x100035))
+#define MCFGPIO_PORTSDP		(*(vu_char *) (CFG_MBAR+0x100036))
+#define MCFGPIO_PORTTCP		(*(vu_char *) (CFG_MBAR+0x100037))
+#define MCFGPIO_PORTTDP		(*(vu_char *) (CFG_MBAR+0x100038))
+#define MCFGPIO_PORTUAP		(*(vu_char *) (CFG_MBAR+0x100039))
+
+#define MCFGPIO_SETA		(*(vu_char *) (CFG_MBAR+0x100028))
+#define MCFGPIO_SETB		(*(vu_char *) (CFG_MBAR+0x100029))
+#define MCFGPIO_SETC		(*(vu_char *) (CFG_MBAR+0x10002A))
+#define MCFGPIO_SETD		(*(vu_char *) (CFG_MBAR+0x10002B))
+#define MCFGPIO_SETE		(*(vu_char *) (CFG_MBAR+0x10002C))
+#define MCFGPIO_SETF		(*(vu_char *) (CFG_MBAR+0x10002D))
+#define MCFGPIO_SETG   		(*(vu_char *) (CFG_MBAR+0x10002E))
+#define MCFGPIO_SETH   		(*(vu_char *) (CFG_MBAR+0x10002F))
+#define MCFGPIO_SETJ   		(*(vu_char *) (CFG_MBAR+0x100030))
+#define MCFGPIO_SETDD  		(*(vu_char *) (CFG_MBAR+0x100031))
+#define MCFGPIO_SETEH  		(*(vu_char *) (CFG_MBAR+0x100032))
+#define MCFGPIO_SETEL  		(*(vu_char *) (CFG_MBAR+0x100033))
+#define MCFGPIO_SETAS  		(*(vu_char *) (CFG_MBAR+0x100034))
+#define MCFGPIO_SETQS  		(*(vu_char *) (CFG_MBAR+0x100035))
+#define MCFGPIO_SETSD  		(*(vu_char *) (CFG_MBAR+0x100036))
+#define MCFGPIO_SETTC  		(*(vu_char *) (CFG_MBAR+0x100037))
+#define MCFGPIO_SETTD  		(*(vu_char *) (CFG_MBAR+0x100038))
+#define MCFGPIO_SETUA  		(*(vu_char *) (CFG_MBAR+0x100039))
+
+#define MCFGPIO_CLRA  		(*(vu_char *) (CFG_MBAR+0x10003C))
+#define MCFGPIO_CLRB  		(*(vu_char *) (CFG_MBAR+0x10003D))
+#define MCFGPIO_CLRC  		(*(vu_char *) (CFG_MBAR+0x10003E))
+#define MCFGPIO_CLRD  		(*(vu_char *) (CFG_MBAR+0x10003F))
+#define MCFGPIO_CLRE  		(*(vu_char *) (CFG_MBAR+0x100040))
+#define MCFGPIO_CLRF  		(*(vu_char *) (CFG_MBAR+0x100041))
+#define MCFGPIO_CLRG  		(*(vu_char *) (CFG_MBAR+0x100042))
+#define MCFGPIO_CLRH  		(*(vu_char *) (CFG_MBAR+0x100043))
+#define MCFGPIO_CLRJ  		(*(vu_char *) (CFG_MBAR+0x100044))
+#define MCFGPIO_CLRDD  		(*(vu_char *) (CFG_MBAR+0x100045))
+#define MCFGPIO_CLREH  		(*(vu_char *) (CFG_MBAR+0x100046))
+#define MCFGPIO_CLREL  		(*(vu_char *) (CFG_MBAR+0x100047))
+#define MCFGPIO_CLRAS  		(*(vu_char *) (CFG_MBAR+0x100048))
+#define MCFGPIO_CLRQS  		(*(vu_char *) (CFG_MBAR+0x100049))
+#define MCFGPIO_CLRSD  		(*(vu_char *) (CFG_MBAR+0x10004A))
+#define MCFGPIO_CLRTC  		(*(vu_char *) (CFG_MBAR+0x10004B))
+#define MCFGPIO_CLRTD  		(*(vu_char *) (CFG_MBAR+0x10004C))
+#define MCFGPIO_CLRUA  		(*(vu_char *) (CFG_MBAR+0x10004D))
+
+#define MCFGPIO_PBCDPAR  	(*(vu_char *) (CFG_MBAR+0x100050))
+#define MCFGPIO_PFPAR  		(*(vu_char *) (CFG_MBAR+0x100051))
+#define MCFGPIO_PEPAR  		(*(vu_short *)(CFG_MBAR+0x100052))
+#define MCFGPIO_PJPAR  		(*(vu_char *) (CFG_MBAR+0x100054))
+#define MCFGPIO_PSDPAR  	(*(vu_char *) (CFG_MBAR+0x100055))
+#define MCFGPIO_PASPAR  	(*(vu_short *)(CFG_MBAR+0x100056))
+#define MCFGPIO_PEHLPAR  	(*(vu_char *) (CFG_MBAR+0x100058))
+#define MCFGPIO_PQSPAR  	(*(vu_char *) (CFG_MBAR+0x100059))
+#define MCFGPIO_PTCPAR  	(*(vu_char *) (CFG_MBAR+0x10005A))
+#define MCFGPIO_PTDPAR  	(*(vu_char *) (CFG_MBAR+0x10005B))
+#define MCFGPIO_PUAPAR  	(*(vu_char *) (CFG_MBAR+0x10005C))
+
+/* Bit level definitions and macros */
+#define MCFGPIO_PORT7			(0x80)
+#define MCFGPIO_PORT6			(0x40)
+#define MCFGPIO_PORT5			(0x20)
+#define MCFGPIO_PORT4			(0x10)
+#define MCFGPIO_PORT3			(0x08)
+#define MCFGPIO_PORT2			(0x04)
+#define MCFGPIO_PORT1			(0x02)
+#define MCFGPIO_PORT0			(0x01)
+#define MCFGPIO_PORT(x)			(0x01<<x)
+
+#define MCFGPIO_DDR7			(0x80)
+#define MCFGPIO_DDR6			(0x40)
+#define MCFGPIO_DDR5			(0x20)
+#define MCFGPIO_DDR4			(0x10)
+#define MCFGPIO_DDR3			(0x08)
+#define MCFGPIO_DDR2			(0x04)
+#define MCFGPIO_DDR1			(0x02)
+#define MCFGPIO_DDR0			(0x01)
+#define MCFGPIO_DDR(x)			(0x01<<x)
+
+#define MCFGPIO_Px7			(0x80)
+#define MCFGPIO_Px6			(0x40)
+#define MCFGPIO_Px5			(0x20)
+#define MCFGPIO_Px4			(0x10)
+#define MCFGPIO_Px3			(0x08)
+#define MCFGPIO_Px2			(0x04)
+#define MCFGPIO_Px1			(0x02)
+#define MCFGPIO_Px0			(0x01)
+#define MCFGPIO_Px(x)			(0x01<<x)
+
+
+#define MCFGPIO_PBCDPAR_PBPA		(0x80)
+#define MCFGPIO_PBCDPAR_PCDPA		(0x40)
+
+#define MCFGPIO_PEPAR_PEPA7		(0x4000)
+#define MCFGPIO_PEPAR_PEPA6		(0x1000)
+#define MCFGPIO_PEPAR_PEPA5		(0x0400)
+#define MCFGPIO_PEPAR_PEPA4		(0x0100)
+#define MCFGPIO_PEPAR_PEPA3		(0x0040)
+#define MCFGPIO_PEPAR_PEPA2		(0x0010)
+#define MCFGPIO_PEPAR_PEPA1(x)		(((x)&0x3)<<2)
+#define MCFGPIO_PEPAR_PEPA0(x)		(((x)&0x3))
+
+#define MCFGPIO_PFPAR_PFPA7		(0x80)
+#define MCFGPIO_PFPAR_PFPA6		(0x40)
+#define MCFGPIO_PFPAR_PFPA5		(0x20)
+
+#define MCFGPIO_PJPAR_PJPA7		(0x80)
+#define MCFGPIO_PJPAR_PJPA6		(0x40)
+#define MCFGPIO_PJPAR_PJPA5		(0x20)
+#define MCFGPIO_PJPAR_PJPA4		(0x10)
+#define MCFGPIO_PJPAR_PJPA3		(0x08)
+#define MCFGPIO_PJPAR_PJPA2		(0x04)
+#define MCFGPIO_PJPAR_PJPA1		(0x02)
+#define MCFGPIO_PJPAR_PJPA0		(0x01)
+#define MCFGPIO_PJPAR_PJPA(x)		(0x01<<x)
+
+#define MCFGPIO_PSDPAR_PSDPA		(0x80)
+
+#define MCFGPIO_PASPAR_PASPA5(x)	(((x)&0x3)<<10)
+#define MCFGPIO_PASPAR_PASPA4(x)	(((x)&0x3)<<8)
+#define MCFGPIO_PASPAR_PASPA3(x)	(((x)&0x3)<<6)
+#define MCFGPIO_PASPAR_PASPA2(x)	(((x)&0x3)<<4)
+#define MCFGPIO_PASPAR_PASPA1(x)	(((x)&0x3)<<2)
+#define MCFGPIO_PASPAR_PASPA0(x)	(((x)&0x3))
+
+#define MCFGPIO_PEHLPAR_PEHPA		(0x80)
+#define MCFGPIO_PEHLPAR_PELPA		(0x40)
+
+#define MCFGPIO_PQSPAR_PQSPA6		(0x40)
+#define MCFGPIO_PQSPAR_PQSPA5		(0x20)
+#define MCFGPIO_PQSPAR_PQSPA4		(0x10)
+#define MCFGPIO_PQSPAR_PQSPA3		(0x08)
+#define MCFGPIO_PQSPAR_PQSPA2		(0x04)
+#define MCFGPIO_PQSPAR_PQSPA1		(0x02)
+#define MCFGPIO_PQSPAR_PQSPA0		(0x01)
+#define MCFGPIO_PQSPAR_PQSPA(x)		(0x01<<x)
+
+#define MCFGPIO_PTCPAR_PTCPA3(x)	(((x)&0x3)<<6)
+#define MCFGPIO_PTCPAR_PTCPA2(x)	(((x)&0x3)<<4)
+#define MCFGPIO_PTCPAR_PTCPA1(x)	(((x)&0x3)<<2)
+#define MCFGPIO_PTCPAR_PTCPA0(x)	(((x)&0x3))
+
+#define MCFGPIO_PTDPAR_PTDPA3(x)	(((x)&0x3)<<6)
+#define MCFGPIO_PTDPAR_PTDPA2(x)	(((x)&0x3)<<4)
+#define MCFGPIO_PTDPAR_PTDPA1(x)	(((x)&0x3)<<2)
+#define MCFGPIO_PTDPAR_PTDPA0(x)	(((x)&0x3))
+
+#define MCFGPIO_PUAPAR_PUAPA3		(0x08)
+#define MCFGPIO_PUAPAR_PUAPA2		(0x04)
+#define MCFGPIO_PUAPAR_PUAPA1		(0x02)
+#define MCFGPIO_PUAPAR_PUAPA0		(0x01)
+
+/* System Conrol Module SCM */
+
+#define MCFSCM_RAMBAR           (*(vu_long *) (CFG_MBAR+0x00000008))
+#define MCFSCM_CRSR		(*(vu_char *) (CFG_MBAR+0x00000010))
+#define MCFSCM_CWCR		(*(vu_char *) (CFG_MBAR+0x00000011))
+#define MCFSCM_LPICR		(*(vu_char *) (CFG_MBAR+0x00000012))
+#define MCFSCM_CWSR		(*(vu_char *) (CFG_MBAR+0x00000013))
+
+#define MCFSCM_MPARK		(*(vu_long *) (CFG_MBAR+0x0000001C))
+#define MCFSCM_MPR		(*(vu_char *) (CFG_MBAR+0x00000020))
+#define MCFSCM_PACR0		(*(vu_char *) (CFG_MBAR+0x00000024))
+#define MCFSCM_PACR1		(*(vu_char *) (CFG_MBAR+0x00000025))
+#define MCFSCM_PACR2		(*(vu_char *) (CFG_MBAR+0x00000026))
+#define MCFSCM_PACR3		(*(vu_char *) (CFG_MBAR+0x00000027))
+#define MCFSCM_PACR4		(*(vu_char *) (CFG_MBAR+0x00000028))
+#define MCFSCM_PACR5		(*(vu_char *) (CFG_MBAR+0x0000002A))
+#define MCFSCM_PACR6		(*(vu_char *) (CFG_MBAR+0x0000002B))
+#define MCFSCM_PACR7		(*(vu_char *) (CFG_MBAR+0x0000002C))
+#define MCFSCM_PACR8		(*(vu_char *) (CFG_MBAR+0x0000002E))
+#define MCFSCM_GPACR0		(*(vu_char *) (CFG_MBAR+0x00000030))
+#define MCFSCM_GPACR1		(*(vu_char *) (CFG_MBAR+0x00000031))
+
+
+#define MCFSCM_CRSR_EXT		(0x80)
+#define MCFSCM_CRSR_CWDR	(0x20)
+#define MCFSCM_RAMBAR_BA(x)     ((x)&0xFFFF0000)
+#define MCFSCM_RAMBAR_BDE       (0x00000200)
+
+/* Reset Controller Module RCM */
+
+#define MCFRESET_RCR		(*(vu_char *) (CFG_MBAR+0x00110000))
+#define MCFRESET_RSR		(*(vu_char *) (CFG_MBAR+0x00110001))
+
+#define MCFRESET_RCR_SOFTRST    (0x80)
+#define MCFRESET_RCR_FRCRSTOUT  (0x40)
+#define MCFRESET_RCR_LVDF       (0x10)
+#define MCFRESET_RCR_LVDIE      (0x08)
+#define MCFRESET_RCR_LVDRE      (0x04)
+#define MCFRESET_RCR_LVDE       (0x01)
+
+#define MCFRESET_RSR_LVD        (0x40)
+#define MCFRESET_RSR_SOFT       (0x20)
+#define MCFRESET_RSR_WDR        (0x10)
+#define MCFRESET_RSR_POR        (0x08)
+#define MCFRESET_RSR_EXT        (0x04)
+#define MCFRESET_RSR_LOC        (0x02)
+#define MCFRESET_RSR_LOL        (0x01)
+#define MCFRESET_RSR_ALL        (0x7F)
+#define MCFRESET_RCR_SOFTRST    (0x80)
+#define MCFRESET_RCR_FRCRSTOUT  (0x40)
+
+/* Chip Configuration Module CCM */
+
+#define MCFCCM_CCR		(*(vu_short *)(CFG_MBAR+0x00110004))
+#define MCFCCM_RCON		(*(vu_short *)(CFG_MBAR+0x00110008))
+#define MCFCCM_CIR		(*(vu_short *)(CFG_MBAR+0x0011000A))
+
+
+/* Bit level definitions and macros */
+#define MCFCCM_CCR_LOAD			(0x8000)
+#define MCFCCM_CCR_MODE(x) 		(((x)&0x0007)<<8)
+#define MCFCCM_CCR_SZEN    		(0x0040)
+#define MCFCCM_CCR_PSTEN   		(0x0020)
+#define MCFCCM_CCR_BME			(0x0008)
+#define MCFCCM_CCR_BMT(x)  		(((x)&0x0007))
+
+#define MCFCCM_CIR_PIN_MASK		(0xFF00)
+#define MCFCCM_CIR_PRN_MASK		(0x00FF)
+
+/* Clock Module */
+
+#define MCFCLOCK_SYNCR          (*(vu_short *)(CFG_MBAR+0x120000))
+#define MCFCLOCK_SYNSR          (*(vu_char *) (CFG_MBAR+0x120002))
+
+#define MCFCLOCK_SYNCR_MFD(x)   (((x)&0x0007)<<12)
+#define MCFCLOCK_SYNCR_RFD(x)   (((x)&0x0007)<<8)
+#define MCFCLOCK_SYNSR_LOCK     0x08
+
+#define MCFSDRAMC_DCR		(*(vu_short *)(CFG_MBAR+0x00000040))
+#define MCFSDRAMC_DACR0		(*(vu_long *) (CFG_MBAR+0x00000048))
+#define MCFSDRAMC_DMR0		(*(vu_long *) (CFG_MBAR+0x0000004c))
+#define MCFSDRAMC_DACR1		(*(vu_long *) (CFG_MBAR+0x00000050))
+#define MCFSDRAMC_DMR1		(*(vu_long *) (CFG_MBAR+0x00000054))
+
+#define MCFSDRAMC_DCR_NAM	(0x2000)
+#define MCFSDRAMC_DCR_COC	(0x1000)
+#define MCFSDRAMC_DCR_IS	(0x0800)
+#define MCFSDRAMC_DCR_RTIM_3	(0x0000)
+#define MCFSDRAMC_DCR_RTIM_6	(0x0200)
+#define MCFSDRAMC_DCR_RTIM_9	(0x0400)
+#define MCFSDRAMC_DCR_RC(x)	((x)&0x01FF)
+
+#define MCFSDRAMC_DACR_BASE(x)	((x)&0xFFFC0000)
+#define MCFSDRAMC_DACR_RE	(0x00008000)
+#define MCFSDRAMC_DACR_CASL(x)	(((x)&0x03)<<12)
+#define MCFSDRAMC_DACR_CBM(x)	(((x)&0x07)<<8)
+#define MCFSDRAMC_DACR_PS_32	(0x00000000)
+#define MCFSDRAMC_DACR_PS_16	(0x00000020)
+#define MCFSDRAMC_DACR_PS_8	(0x00000010)
+#define MCFSDRAMC_DACR_IP	(0x00000008)
+#define MCFSDRAMC_DACR_IMRS	(0x00000040)
+
+#define MCFSDRAMC_DMR_BAM_16M	(0x00FC0000)
+#define MCFSDRAMC_DMR_WP        (0x00000100)
+#define MCFSDRAMC_DMR_CI        (0x00000040)
+#define MCFSDRAMC_DMR_AM        (0x00000020)
+#define MCFSDRAMC_DMR_SC        (0x00000010)
+#define MCFSDRAMC_DMR_SD        (0x00000008)
+#define MCFSDRAMC_DMR_UC        (0x00000004)
+#define MCFSDRAMC_DMR_UD        (0x00000002)
+#define MCFSDRAMC_DMR_V         (0x00000001)
+
+#define MCFWTM_WCR              (*(vu_short *)(CFG_MBAR+0x00140000))
+#define MCFWTM_WMR              (*(vu_short *)(CFG_MBAR+0x00140002))
+#define MCFWTM_WCNTR            (*(vu_short *)(CFG_MBAR+0x00140004))
+#define MCFWTM_WSR              (*(vu_short *)(CFG_MBAR+0x00140006))
+
+/*  Chip SELECT Module CSM */
+#define MCFCSM_CSAR0		(*(vu_short *)(CFG_MBAR+0x00000080))
+#define MCFCSM_CSMR0		(*(vu_long *) (CFG_MBAR+0x00000084))
+#define MCFCSM_CSCR0		(*(vu_short *)(CFG_MBAR+0x0000008a))
+#define MCFCSM_CSAR1		(*(vu_short *)(CFG_MBAR+0x0000008C))
+#define MCFCSM_CSMR1		(*(vu_long *) (CFG_MBAR+0x00000090))
+#define MCFCSM_CSCR1		(*(vu_short *)(CFG_MBAR+0x00000096))
+#define MCFCSM_CSAR2		(*(vu_short *)(CFG_MBAR+0x00000098))
+#define MCFCSM_CSMR2		(*(vu_long *) (CFG_MBAR+0x0000009C))
+#define MCFCSM_CSCR2		(*(vu_short *)(CFG_MBAR+0x000000A2))
+#define MCFCSM_CSAR3		(*(vu_short *)(CFG_MBAR+0x000000A4))
+#define MCFCSM_CSMR3		(*(vu_long *) (CFG_MBAR+0x000000A8))
+#define MCFCSM_CSCR3		(*(vu_short *)(CFG_MBAR+0x000000AE))
+
+#define MCFCSM_CSMR_BAM(x)	((x) & 0xFFFF0000)
+#define MCFCSM_CSMR_WP		(1<<8)
+#define MCFCSM_CSMR_V		(0x01)
+#define MCFCSM_CSCR_WS(x)	((x & 0x0F)<<10)
+#define MCFCSM_CSCR_AA		(0x0100)
+#define MCFCSM_CSCR_PS_32	(0x0000)
+#define MCFCSM_CSCR_PS_8	(0x0040)
+#define MCFCSM_CSCR_PS_16	(0x0080)
+
+/*********************************************************************
+*
+* General Purpose Timer (GPT) Module
+*
+*********************************************************************/
+
+#define MCFGPTA_GPTIOS		(*(vu_char *)(CFG_MBAR+0x1A0000))
+#define MCFGPTA_GPTCFORC	(*(vu_char *)(CFG_MBAR+0x1A0001))
+#define MCFGPTA_GPTOC3M		(*(vu_char *)(CFG_MBAR+0x1A0002))
+#define MCFGPTA_GPTOC3D		(*(vu_char *)(CFG_MBAR+0x1A0003))
+#define MCFGPTA_GPTCNT		(*(vu_short *)(CFG_MBAR+0x1A0004))
+#define MCFGPTA_GPTSCR1		(*(vu_char *)(CFG_MBAR+0x1A0006))
+#define MCFGPTA_GPTTOV		(*(vu_char *)(CFG_MBAR+0x1A0008))
+#define MCFGPTA_GPTCTL1		(*(vu_char *)(CFG_MBAR+0x1A0009))
+#define MCFGPTA_GPTCTL2		(*(vu_char *)(CFG_MBAR+0x1A000B))
+#define MCFGPTA_GPTIE		(*(vu_char *)(CFG_MBAR+0x1A000C))
+#define MCFGPTA_GPTSCR2		(*(vu_char *)(CFG_MBAR+0x1A000D))
+#define MCFGPTA_GPTFLG1		(*(vu_char *)(CFG_MBAR+0x1A000E))
+#define MCFGPTA_GPTFLG2		(*(vu_char *)(CFG_MBAR+0x1A000F))
+#define MCFGPTA_GPTC0		(*(vu_short *)(CFG_MBAR+0x1A0010))
+#define MCFGPTA_GPTC1		(*(vu_short *)(CFG_MBAR+0x1A0012))
+#define MCFGPTA_GPTC2		(*(vu_short *)(CFG_MBAR+0x1A0014))
+#define MCFGPTA_GPTC3		(*(vu_short *)(CFG_MBAR+0x1A0016))
+#define MCFGPTA_GPTPACTL	(*(vu_char *)(CFG_MBAR+0x1A0018))
+#define MCFGPTA_GPTPAFLG	(*(vu_char *)(CFG_MBAR+0x1A0019))
+#define MCFGPTA_GPTPACNT	(*(vu_short *)(CFG_MBAR+0x1A001A))
+#define MCFGPTA_GPTPORT		(*(vu_char *)(CFG_MBAR+0x1A001D))
+#define MCFGPTA_GPTDDR		(*(vu_char *)(CFG_MBAR+0x1A001E))
+
+
+#define MCFGPTB_GPTIOS		(*(vu_char *)(CFG_MBAR+0x1B0000))
+#define MCFGPTB_GPTCFORC	(*(vu_char *)(CFG_MBAR+0x1B0001))
+#define MCFGPTB_GPTOC3M		(*(vu_char *)(CFG_MBAR+0x1B0002))
+#define MCFGPTB_GPTOC3D		(*(vu_char *)(CFG_MBAR+0x1B0003))
+#define MCFGPTB_GPTCNT		(*(vu_short *)(CFG_MBAR+0x1B0004))
+#define MCFGPTB_GPTSCR1		(*(vu_char *)(CFG_MBAR+0x1B0006))
+#define MCFGPTB_GPTTOV		(*(vu_char *)(CFG_MBAR+0x1B0008))
+#define MCFGPTB_GPTCTL1		(*(vu_char *)(CFG_MBAR+0x1B0009))
+#define MCFGPTB_GPTCTL2		(*(vu_char *)(CFG_MBAR+0x1B000B))
+#define MCFGPTB_GPTIE		(*(vu_char *)(CFG_MBAR+0x1B000C))
+#define MCFGPTB_GPTSCR2		(*(vu_char *)(CFG_MBAR+0x1B000D))
+#define MCFGPTB_GPTFLG1		(*(vu_char *)(CFG_MBAR+0x1B000E))
+#define MCFGPTB_GPTFLG2		(*(vu_char *)(CFG_MBAR+0x1B000F))
+#define MCFGPTB_GPTC0		(*(vu_short *)(CFG_MBAR+0x1B0010))
+#define MCFGPTB_GPTC1		(*(vu_short *)(CFG_MBAR+0x1B0012))
+#define MCFGPTB_GPTC2		(*(vu_short *)(CFG_MBAR+0x1B0014))
+#define MCFGPTB_GPTC3		(*(vu_short *)(CFG_MBAR+0x1B0016))
+#define MCFGPTB_GPTPACTL	(*(vu_char *)(CFG_MBAR+0x1B0018))
+#define MCFGPTB_GPTPAFLG	(*(vu_char *)(CFG_MBAR+0x1B0019))
+#define MCFGPTB_GPTPACNT	(*(vu_short *)(CFG_MBAR+0x1B001A))
+#define MCFGPTB_GPTPORT		(*(vu_char *)(CFG_MBAR+0x1B001D))
+#define MCFGPTB_GPTDDR		(*(vu_char *)(CFG_MBAR+0x1B001E))
+
+/* Bit level definitions and macros */
+#define MCFGPT_GPTIOS_IOS3		(0x08)
+#define MCFGPT_GPTIOS_IOS2		(0x04)
+#define MCFGPT_GPTIOS_IOS1		(0x02)
+#define MCFGPT_GPTIOS_IOS0		(0x01)
+
+#define MCFGPT_GPTCFORC_FOC3		(0x08)
+#define MCFGPT_GPTCFORC_FOC2		(0x04)
+#define MCFGPT_GPTCFORC_FOC1		(0x02)
+#define MCFGPT_GPTCFORC_FOC0		(0x01)
+
+#define MCFGPT_GPTOC3M_OC3M3		(0x08)
+#define MCFGPT_GPTOC3M_OC3M2		(0x04)
+#define MCFGPT_GPTOC3M_OC3M1		(0x02)
+#define MCFGPT_GPTOC3M_OC3M0		(0x01)
+
+#define MCFGPT_GPTOC3M_OC3D(x)		(((x)&0x04))
+
+#define MCFGPT_GPTSCR1_GPTEN		(0x80)
+#define MCFGPT_GPTSCR1_TFFCA		(0x10)
+
+#define MCFGPT_GPTTOV3			(0x08)
+#define MCFGPT_GPTTOV2			(0x04)
+#define MCFGPT_GPTTOV1			(0x02)
+#define MCFGPT_GPTTOV0			(0x01)
+
+#define MCFGPT_GPTCTL_OMOL3(x)		(((x)&0x03)<<6)
+#define MCFGPT_GPTCTL_OMOL2(x)		(((x)&0x03)<<4)
+#define MCFGPT_GPTCTL_OMOL1(x)		(((x)&0x03)<<2)
+#define MCFGPT_GPTCTL_OMOL0(x)		(((x)&0x03))
+
+#define MCFGPT_GPTCTL2_EDG3(x)		(((x)&0x03)<<6)
+#define MCFGPT_GPTCTL2_EDG2(x)		(((x)&0x03)<<4)
+#define MCFGPT_GPTCTL2_EDG1(x)		(((x)&0x03)<<2)
+#define MCFGPT_GPTCTL2_EDG0(x)		(((x)&0x03))
+
+#define MCFGPT_GPTIE_C3I		(0x08)
+#define MCFGPT_GPTIE_C2I		(0x04)
+#define MCFGPT_GPTIE_C1I		(0x02)
+#define MCFGPT_GPTIE_C0I		(0x01)
+
+#define MCFGPT_GPTSCR2_TOI 		(0x80)
+#define MCFGPT_GPTSCR2_PUPT		(0x20)
+#define MCFGPT_GPTSCR2_RDPT		(0x10)
+#define MCFGPT_GPTSCR2_TCRE		(0x08)
+#define MCFGPT_GPTSCR2_PR(x)		(((x)&0x07))
+
+#define MCFGPT_GPTFLG1_C3F		(0x08)
+#define MCFGPT_GPTFLG1_C2F		(0x04)
+#define MCFGPT_GPTFLG1_C1F		(0x02)
+#define MCFGPT_GPTFLG1_C0F		(0x01)
+
+#define MCFGPT_GPTFLG2_TOF		(0x80)
+#define MCFGPT_GPTFLG2_C3F		(0x08)
+#define MCFGPT_GPTFLG2_C2F		(0x04)
+#define MCFGPT_GPTFLG2_C1F		(0x02)
+#define MCFGPT_GPTFLG2_C0F		(0x01)
+
+#define MCFGPT_GPTPACTL_PAE		(0x40)
+#define MCFGPT_GPTPACTL_PAMOD		(0x20)
+#define MCFGPT_GPTPACTL_PEDGE		(0x10)
+#define MCFGPT_GPTPACTL_CLK_PACLK	(0x04)
+#define MCFGPT_GPTPACTL_CLK_PACLK256	(0x08)
+#define MCFGPT_GPTPACTL_CLK_PACLK65536	(0x0C)
+#define MCFGPT_GPTPACTL_CLK(x)		(((x)&0x03)<<2)
+#define MCFGPT_GPTPACTL_PAOVI		(0x02)
+#define MCFGPT_GPTPACTL_PAI		(0x01)
+
+#define MCFGPT_GPTPAFLG_PAOVF		(0x02)
+#define MCFGPT_GPTPAFLG_PAIF		(0x01)
+
+#define MCFGPT_GPTPORT_PORTT3		(0x08)
+#define MCFGPT_GPTPORT_PORTT2		(0x04)
+#define MCFGPT_GPTPORT_PORTT1		(0x02)
+#define MCFGPT_GPTPORT_PORTT0		(0x01)
+
+#define MCFGPT_GPTDDR_DDRT3		(0x08)
+#define MCFGPT_GPTDDR_DDRT2		(0x04)
+#define MCFGPT_GPTDDR_DDRT1		(0x02)
+#define MCFGPT_GPTDDR_DDRT0		(0x01)
+
+/* Coldfire Flash Module CFM */
+
+#define MCFCFM_MCR			(*(vu_short *)(CFG_MBAR+0x1D0000))
+#define MCFCFM_MCR_LOCK			(0x0400)
+#define MCFCFM_MCR_PVIE			(0x0200)
+#define MCFCFM_MCR_AEIE			(0x0100)
+#define MCFCFM_MCR_CBEIE		(0x0080)
+#define MCFCFM_MCR_CCIE			(0x0040)
+#define MCFCFM_MCR_KEYACC		(0x0020)
+
+#define MCFCFM_CLKD			(*(vu_char *)(CFG_MBAR+0x1D0002))
+
+#define MCFCFM_SEC			(*(vu_long*) (CFG_MBAR+0x1D0008))
+#define MCFCFM_SEC_KEYEN		(0x80000000)
+#define MCFCFM_SEC_SECSTAT		(0x40000000)
+
+#define MCFCFM_PROT			(*(vu_long*) (CFG_MBAR+0x1D0010))
+#define MCFCFM_SACC			(*(vu_long*) (CFG_MBAR+0x1D0014))
+#define MCFCFM_DACC			(*(vu_long*) (CFG_MBAR+0x1D0018))
+#define MCFCFM_USTAT			(*(vu_char*) (CFG_MBAR+0x1D0020))
+#define MCFCFM_USTAT_CBEIF		0x80
+#define MCFCFM_USTAT_CCIF		0x40
+#define MCFCFM_USTAT_PVIOL		0x20
+#define MCFCFM_USTAT_ACCERR		0x10
+#define MCFCFM_USTAT_BLANK		0x04
 
+#define MCFCFM_CMD			(*(vu_char*) (CFG_MBAR+0x1D0024))
+#define MCFCFM_CMD_ERSVER		0x05
+#define MCFCFM_CMD_PGERSVER		0x06
+#define MCFCFM_CMD_PGM			0x20
+#define MCFCFM_CMD_PGERS		0x40
+#define MCFCFM_CMD_MASERS		0x41
 
 /****************************************************************************/
 #endif	/* m5282_h */
diff --git a/include/asm-nios2/io.h b/include/asm-nios2/io.h
index b16a988..0fab53b 100644
--- a/include/asm-nios2/io.h
+++ b/include/asm-nios2/io.h
@@ -39,12 +39,13 @@ extern unsigned inl (unsigned port);
 #define readl(addr)\
 	({unsigned long val;\
 	 asm volatile( "ldwio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;})
+
 #define writeb(addr,val)\
-	asm volatile ("stbio %0, 0(%1)" : : "r" (addr), "r" (val))
+	asm volatile ("stbio %1, 0(%0)" : : "r" (addr), "r" (val))
 #define writew(addr,val)\
-	asm volatile ("sthio %0, 0(%1)" : : "r" (addr), "r" (val))
+	asm volatile ("sthio %1, 0(%0)" : : "r" (addr), "r" (val))
 #define writel(addr,val)\
-	asm volatile ("stwio %0, 0(%1)" : : "r" (addr), "r" (val))
+	asm volatile ("stwio %1, 0(%0)" : : "r" (addr), "r" (val))
 
 #define inb(addr)	readb(addr)
 #define inw(addr)	readw(addr)
diff --git a/include/configs/EB+MCF-EV123.h b/include/configs/EB+MCF-EV123.h
new file mode 100644
index 0000000..720b335
--- /dev/null
+++ b/include/configs/EB+MCF-EV123.h
@@ -0,0 +1,223 @@
+/*
+ * Configuation settings for the BuS EB+MCF-EV123 boards.
+ *
+ * (C) Copyright 2005 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _CONFIG_EB_MCF_EV123_H_
+#define _CONFIG_EB_MCF_EV123_H_
+
+#define  CONFIG_EB_MCF_EV123
+
+#undef DEBUG
+#undef CFG_HALT_BEFOR_RAM_JUMP
+#undef ET_DEBUG
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+#define	CONFIG_MCF52x2			/* define processor family */
+#define CONFIG_M5282			/* define processor type */
+
+#define CONFIG_MISC_INIT_R
+
+#define FEC_ENET
+#define CONFIG_ETHADDR 00:CF:52:82:EB:01
+
+#define CONFIG_BAUDRATE 9600
+#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+
+#undef	CONFIG_MONITOR_IS_IN_RAM	/* define if monitor is started from a pre-loader */
+
+#define CONFIG_BOOTCOMMAND "printenv"
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+#define CFG_ENV_ADDR		0xF003C000	/* End of 256K */
+#define CFG_ENV_SECT_SIZE	0x4000
+#define CFG_ENV_IS_IN_FLASH	1
+/*
+#define CFG_ENV_IS_EMBEDDED	1
+#define CFG_ENV_ADDR_REDUND		0xF0018000
+#define CFG_ENV_SECT_SIZE_REDUND	0x4000
+*/
+#else
+#define CFG_ENV_ADDR		0xFFE04000
+#define CFG_ENV_SECT_SIZE	0x2000
+#define CFG_ENV_IS_IN_FLASH	1
+#endif
+
+/*#define CONFIG_COMMANDS  ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) ) */
+#define CONFIG_COMMANDS  ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADB))
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	5
+#define CFG_PROMPT		"\nEV123 U-Boot> "
+#define	CFG_LONGHELP				/* undef to save memory		*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_LOAD_ADDR		0x20000
+
+#define CFG_MEMTEST_START	0x100000
+#define CFG_MEMTEST_END		0x400000
+/*#define CFG_DRAM_TEST		1 */
+#undef CFG_DRAM_TEST
+
+/* Clock and PLL Configuration */
+#define CFG_HZ			10000000
+#define	CFG_CLK			58982400       /* 9,8304MHz * 6 */
+
+/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
+
+#define CFG_MFD			0x01	/* PLL Multiplication Factor Devider */
+#define CFG_RFD			0x00	/* PLL Reduce Frecuency Devider */
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+#define	CFG_MBAR		0x40000000
+
+#define	CFG_DISCOVER_PHY
+/* #define	CFG_ENET_BD_BASE	0x380000 */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR       0x20000000
+#define CFG_INIT_RAM_END	0x10000		/* End of used area in internal SRAM	*/
+#define CFG_GBL_DATA_SIZE	64      	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE1		0x00000000
+#define	CFG_SDRAM_SIZE1		16		/* SDRAM size in MB */
+
+/*
+#define CFG_SDRAM_BASE0		CFG_SDRAM_BASE1+CFG_SDRAM_SIZE1*1024*1024
+#define	CFG_SDRAM_SIZE0		16	*/	/* SDRAM size in MB */
+
+#define CFG_SDRAM_BASE		CFG_SDRAM_BASE1
+#define	CFG_SDRAM_SIZE		CFG_SDRAM_SIZE1
+
+#define CFG_FLASH_BASE		0xFFE00000
+#define	CFG_INT_FLASH_BASE	0xF0000000
+
+/* If M5282 port is fully implemented the monitor base will be behind
+ * the vector table. */
+#if (TEXT_BASE !=  CFG_INT_FLASH_BASE)
+#define CFG_MONITOR_BASE	(TEXT_BASE + 0x400)
+#else
+#define CFG_MONITOR_BASE	(TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
+#endif
+
+#define CFG_MONITOR_LEN		0x20000
+#define CFG_MALLOC_LEN		(256 << 10)
+#define CFG_BOOTPARAMS_LEN	64*1024
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define	CFG_MAX_FLASH_SECT	35
+#define	CFG_MAX_FLASH_BANKS	2
+#define	CFG_FLASH_ERASE_TOUT	10000000
+#define	CFG_FLASH_PROTECTION
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+
+#define CFG_CS0_BASE		CFG_FLASH_BASE
+#define CFG_CS0_SIZE		2*1024*1024
+#define CFG_CS0_WIDTH		16
+#define CFG_CS0_RO 		0
+#define CFG_CS0_WS		6
+
+#define CFG_CS3_BASE		0xE0000000
+#define CFG_CS3_SIZE		1*1024*1024
+#define CFG_CS3_WIDTH		16
+#define CFG_CS3_RO 		0
+#define CFG_CS3_WS		6
+
+/*-----------------------------------------------------------------------
+ * Port configuration
+ */
+#define CFG_PACNT		0x0000000	/* Port A D[31:24] */
+#define CFG_PADDR		0x0000000
+#define CFG_PADAT		0x0000000
+
+#define CFG_PBCNT		0x0000000	/* Port B D[23:16] */
+#define CFG_PBDDR		0x0000000
+#define CFG_PBDAT		0x0000000
+
+#define CFG_PCCNT		0x0000000	/* Port C D[15:08] */
+#define CFG_PCDDR		0x0000000
+#define CFG_PCDAT		0x0000000
+
+#define CFG_PDCNT		0x0000000	/* Port D D[07:00] */
+#define CFG_PCDDR		0x0000000
+#define CFG_PCDAT		0x0000000
+
+#define CFG_PEHLPAR		0xC0
+#define CFG_PUAPAR		0x0F		/* UA0..UA3 = Uart 0 +1 */
+#define CFG_DDRUA		0x05
+#define CFG_PJPAR 		0xFF;
+
+/*-----------------------------------------------------------------------
+ * CCM configuration
+ */
+
+#define	CFG_CCM_SIZ		0
+
+/*---------------------------------------------------------------------*/
+#endif	/* _CONFIG_M5282EVB_H */
+/*---------------------------------------------------------------------*/
diff --git a/include/configs/EP1C20.h b/include/configs/EP1C20.h
new file mode 100644
index 0000000..5507f35
--- /dev/null
+++ b/include/configs/EP1C20.h
@@ -0,0 +1,199 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*------------------------------------------------------------------------
+ * BOARD/CPU
+ *----------------------------------------------------------------------*/
+#define CONFIG_EP1C20		1		/* EP1C20 board		*/
+#define CONFIG_SYS_CLK_FREQ	50000000	/* 50 MHz core clk	*/
+
+#define CFG_RESET_ADDR		0x00000000	/* Hard-reset address	*/
+#define CFG_EXCEPTION_ADDR	0x01000020	/* Exception entry point*/
+#define CFG_NIOS_SYSID_BASE	0x021208b8	/* System id address	*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* enable early board-spec. init*/
+
+/*------------------------------------------------------------------------
+ * CACHE -- the following will support II/s and II/f. The II/s does not
+ * have dcache, so the cache instructions will behave as NOPs.
+ *----------------------------------------------------------------------*/
+#define CFG_ICACHE_SIZE		4096		/* 4 KByte total	*/
+#define CFG_ICACHELINE_SIZE	32		/* 32 bytes/line	*/
+#define CFG_DCACHE_SIZE		2048		/* 2 KByte (II/f)	*/
+#define CFG_DCACHELINE_SIZE	4		/* 4 bytes/line (II/f)	*/
+
+/*------------------------------------------------------------------------
+ * MEMORY BASE ADDRESSES
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_BASE		0x00000000	/* FLASH base addr	*/
+#define CFG_FLASH_SIZE		0x00800000	/* 8 MByte		*/
+#define CFG_SDRAM_BASE		0x01000000	/* SDRAM base addr	*/
+#define CFG_SDRAM_SIZE		0x01000000	/* 16 MByte		*/
+#define CFG_SRAM_BASE		0x02000000	/* SRAM base addr	*/
+#define CFG_SRAM_SIZE		0x00100000	/* 1 MB (only 1M mapped)*/
+
+/*------------------------------------------------------------------------
+ * MEMORY ORGANIZATION
+ *	-Monitor at top.
+ *	-The heap is placed below the monitor.
+ *	-Global data is placed below the heap.
+ *	-The stack is placed below global data (&grows down).
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 128k		*/
+#define CFG_GBL_DATA_SIZE	128		/* Global data size rsvd*/
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
+#define CFG_GBL_DATA_OFFSET	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP		CFG_GBL_DATA_OFFSET
+
+/*------------------------------------------------------------------------
+ * FLASH (AM29LV065D)
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_SECT	128		/* Max # sects per bank */
+#define CFG_MAX_FLASH_BANKS	1		/* Max # of flash banks */
+#define CFG_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
+#define CFG_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
+#define CFG_FLASH_WORD_SIZE	unsigned char	/* flash word size	*/
+
+/*------------------------------------------------------------------------
+ * ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above
+ * CFG_RESET_ADDR, since we assume the monitor is stored at the
+ * reset address, no? This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ *----------------------------------------------------------------------*/
+#define CFG_ENV_IS_IN_FLASH	1		/* Environment in flash */
+#define CFG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
+#define CONFIG_ENV_OVERWRITE			/* Serial change Ok	*/
+#define CFG_ENV_ADDR	(CFG_RESET_ADDR + CFG_MONITOR_LEN)
+
+/*------------------------------------------------------------------------
+ * CONSOLE
+ *----------------------------------------------------------------------*/
+#if defined(CONFIG_CONSOLE_JTAG)
+#define CFG_NIOS_CONSOLE	0x021208b0	/* JTAG UART base addr	*/
+#else
+#define CFG_NIOS_CONSOLE	0x02120840	/* UART base addr	*/
+#endif
+
+#define CFG_NIOS_FIXEDBAUD	1		/* Baudrate is fixed	*/
+#define CONFIG_BAUDRATE		115200		/* Initial baudrate	*/
+#define CFG_BAUDRATE_TABLE	{115200}	/* It's fixed ;-)	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1		/* Suppress console info*/
+
+/*------------------------------------------------------------------------
+ * EPCS Device -- wne CFG_NIOS_EPCSBASE is defined code/commands for
+ * epcs device access is enabled. The base address is the epcs
+ * _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK.
+ * The register base is currently at offset 0x600 from the memory base.
+ *----------------------------------------------------------------------*/
+#define CFG_NIOS_EPCSBASE	0x02100200	/* EPCS register base	*/
+
+/*------------------------------------------------------------------------
+ * DEBUG
+ *----------------------------------------------------------------------*/
+#undef CONFIG_ROM_STUBS				/* Stubs not in ROM	*/
+
+/*------------------------------------------------------------------------
+ * TIMEBASE --
+ *
+ * The high res timer defaults to 1 msec. Since it includes the period
+ * registers, we can slow it down to 10 msec using TMRCNT. If the default
+ * period is acceptable, TMRCNT can be left undefined.
+ *----------------------------------------------------------------------*/
+#define CFG_NIOS_TMRBASE	0x02120820	/* Tick timer base addr */
+#define CFG_NIOS_TMRIRQ		3		/* Timer IRQ num	*/
+#define CFG_NIOS_TMRMS		10		/* 10 msec per tick	*/
+#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
+#define CFG_HZ		(CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1))
+
+/*------------------------------------------------------------------------
+ * STATUS LED -- Provides a simple blinking led. For Nios2 each board
+ * must implement its own led routines -- leds are, after all,
+ * board-specific, no?
+ *----------------------------------------------------------------------*/
+#define CFG_LEDPIO_ADDR		0x02120870	/* LED PIO base addr	*/
+#define CONFIG_STATUS_LED			/* Enable status driver */
+
+#define STATUS_LED_BIT		1		/* Bit-0 on PIO		*/
+#define STATUS_LED_STATE	1		/* Blinking		*/
+#define STATUS_LED_PERIOD	(500/CFG_NIOS_TMRMS) /* Every 500 msec	*/
+
+/*------------------------------------------------------------------------
+ * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
+ * and really doesn't need any additional clutter. So I choose the lazy
+ * way out to avoid changes there -- define the base address to ensure
+ * cache bypass so there's no need to monkey with inx/outx macros.
+ *----------------------------------------------------------------------*/
+#define CONFIG_SMC91111_BASE	0x82110300	/* Base addr (bypass)	*/
+#define CONFIG_DRIVER_SMC91111			/* Using SMC91c111	*/
+#undef	CONFIG_SMC91111_EXT_PHY			/* Internal PHY		*/
+#define CONFIG_SMC_USE_32_BIT			/* 32-bit interface	*/
+
+#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		192.168.2.21
+#define CONFIG_SERVERIP		192.168.2.16
+
+/*------------------------------------------------------------------------
+ * COMMANDS
+ *----------------------------------------------------------------------*/
+#define CONFIG_COMMANDS		(CFG_CMD_BDI	| \
+				 CFG_CMD_DHCP	| \
+				 CFG_CMD_ECHO	| \
+				 CFG_CMD_ENV	| \
+				 CFG_CMD_FLASH	| \
+				 CFG_CMD_IMI	| \
+				 CFG_CMD_IRQ	| \
+				 CFG_CMD_LOADS	| \
+				 CFG_CMD_LOADB	| \
+				 CFG_CMD_MEMORY | \
+				 CFG_CMD_MISC	| \
+				 CFG_CMD_NET	| \
+				 CFG_CMD_PING	| \
+				 CFG_CMD_RUN	| \
+				 CFG_CMD_SAVES	)
+#include <cmd_confdefs.h>
+
+/*------------------------------------------------------------------------
+ * MISC
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP				/* Provide extended help*/
+#define CFG_PROMPT		"==> "		/* Command prompt	*/
+#define CFG_CBSIZE		256		/* Console I/O buf size */
+#define CFG_MAXARGS		16		/* Max command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot arg buf size	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */
+#define CFG_LOAD_ADDR		CFG_SDRAM_BASE	/* Default load address */
+#define CFG_MEMTEST_START	CFG_SDRAM_BASE	/* Start addr for test	*/
+#define CFG_MEMTEST_END		CFG_INIT_SP - 0x00020000
+
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/EP1S10.h b/include/configs/EP1S10.h
new file mode 100644
index 0000000..6eca9f2
--- /dev/null
+++ b/include/configs/EP1S10.h
@@ -0,0 +1,193 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*------------------------------------------------------------------------
+ * BOARD/CPU
+ *----------------------------------------------------------------------*/
+#define CONFIG_EP1S10		1		/* EP1S10 board		*/
+#define CONFIG_SYS_CLK_FREQ	50000000	/* 50 MHz core clk	*/
+
+#define CFG_RESET_ADDR		0x00000000	/* Hard-reset address	*/
+#define CFG_EXCEPTION_ADDR	0x01000020	/* Exception entry point*/
+#define CFG_NIOS_SYSID_BASE	0x021208b8	/* System id address	*/
+
+/*------------------------------------------------------------------------
+ * CACHE -- the following will support II/s and II/f. The II/s does not
+ * have dcache, so the cache instructions will behave as NOPs.
+ *----------------------------------------------------------------------*/
+#define CFG_ICACHE_SIZE		4096		/* 4 KByte total	*/
+#define CFG_ICACHELINE_SIZE	32		/* 32 bytes/line	*/
+#define CFG_DCACHE_SIZE		2048		/* 2 KByte (II/f)	*/
+#define CFG_DCACHELINE_SIZE	4		/* 4 bytes/line (II/f)	*/
+
+/*------------------------------------------------------------------------
+ * MEMORY BASE ADDRESSES
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_BASE		0x00000000	/* FLASH base addr	*/
+#define CFG_FLASH_SIZE		0x00800000	/* 8 MByte		*/
+#define CFG_SDRAM_BASE		0x01000000	/* SDRAM base addr	*/
+#define CFG_SDRAM_SIZE		0x01000000	/* 16 MByte		*/
+#define CFG_SRAM_BASE		0x02000000	/* SRAM base addr	*/
+#define CFG_SRAM_SIZE		0x00100000	/* 1 MB			*/
+
+/*------------------------------------------------------------------------
+ * MEMORY ORGANIZATION
+ *	-Monitor at top.
+ *	-The heap is placed below the monitor.
+ *	-Global data is placed below the heap.
+ *	-The stack is placed below global data (&grows down).
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256k		*/
+#define CFG_GBL_DATA_SIZE	128		/* Global data size rsvd*/
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 256*1024) /* 256k heap */
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
+#define CFG_GBL_DATA_OFFSET	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP		CFG_GBL_DATA_OFFSET
+
+/*------------------------------------------------------------------------
+ * FLASH (AM29LV065D)
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_SECT	128		/* Max # sects per bank */
+#define CFG_MAX_FLASH_BANKS	1		/* Max # of flash banks */
+#define CFG_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
+#define CFG_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
+
+/*------------------------------------------------------------------------
+ * ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above
+ * CFG_FLASH_BASE, since we assume that u-boot is stored at the bottom
+ * of flash memory. This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ *----------------------------------------------------------------------*/
+#define CFG_ENV_IS_IN_FLASH	1		/* Environment in flash */
+#define CFG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
+#define CONFIG_ENV_OVERWRITE			/* Serial change Ok	*/
+#define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_MONITOR_LEN)
+
+/*------------------------------------------------------------------------
+ * CONSOLE
+ *----------------------------------------------------------------------*/
+#if defined(CONFIG_CONSOLE_JTAG)
+#define CFG_NIOS_CONSOLE	0x021208b0	/* JTAG UART base addr	*/
+#else
+#define CFG_NIOS_CONSOLE	0x02120840	/* UART base addr	*/
+#endif
+
+#define CFG_NIOS_FIXEDBAUD	1		/* Baudrate is fixed	*/
+#define CONFIG_BAUDRATE		115200		/* Initial baudrate	*/
+#define CFG_BAUDRATE_TABLE	{115200}	/* It's fixed ;-)	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1		/* Suppress console info*/
+
+/*------------------------------------------------------------------------
+ * EPCS Device -- None for stratix.
+ *----------------------------------------------------------------------*/
+#undef CFG_NIOS_EPCSBASE
+
+/*------------------------------------------------------------------------
+ * DEBUG
+ *----------------------------------------------------------------------*/
+#undef CONFIG_ROM_STUBS				/* Stubs not in ROM	*/
+
+/*------------------------------------------------------------------------
+ * TIMEBASE --
+ *
+ * The high res timer defaults to 1 msec. Since it includes the period
+ * registers, we can slow it down to 10 msec using TMRCNT. If the default
+ * period is acceptable, TMRCNT can be left undefined.
+ *----------------------------------------------------------------------*/
+#define CFG_NIOS_TMRBASE	0x02120820	/* Tick timer base addr */
+#define CFG_NIOS_TMRIRQ		3		/* Timer IRQ num	*/
+#define CFG_NIOS_TMRMS		10		/* 10 msec per tick	*/
+#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
+#define CFG_HZ		(CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1))
+
+/*------------------------------------------------------------------------
+ * STATUS LED -- Provides a simple blinking led. For Nios2 each board
+ * must implement its own led routines -- since leds are board-specific.
+ *----------------------------------------------------------------------*/
+#define CFG_LEDPIO_ADDR		0x02120870	/* LED PIO base addr	*/
+#define CONFIG_STATUS_LED			/* Enable status driver */
+
+#define STATUS_LED_BIT		1		/* Bit-0 on PIO		*/
+#define STATUS_LED_STATE	1		/* Blinking		*/
+#define STATUS_LED_PERIOD	(500/CFG_NIOS_TMRMS) /* Every 500 msec	*/
+
+/*------------------------------------------------------------------------
+ * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
+ * and really doesn't need any additional clutter. So I choose the lazy
+ * way out to avoid changes there -- define the base address to ensure
+ * cache bypass so there's no need to monkey with inx/outx macros.
+ *----------------------------------------------------------------------*/
+#define CONFIG_SMC91111_BASE	0x82110300	/* Base addr (bypass)	*/
+#define CONFIG_DRIVER_SMC91111			/* Using SMC91c111	*/
+#undef	CONFIG_SMC91111_EXT_PHY			/* Internal PHY		*/
+#define CONFIG_SMC_USE_32_BIT			/* 32-bit interface	*/
+
+#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		192.168.2.21
+#define CONFIG_SERVERIP		192.168.2.16
+
+/*------------------------------------------------------------------------
+ * COMMANDS
+ *----------------------------------------------------------------------*/
+#define CONFIG_COMMANDS		(CFG_CMD_BDI	| \
+				 CFG_CMD_DHCP	| \
+				 CFG_CMD_ECHO	| \
+				 CFG_CMD_ENV	| \
+				 CFG_CMD_FLASH	| \
+				 CFG_CMD_IMI	| \
+				 CFG_CMD_IRQ	| \
+				 CFG_CMD_LOADS	| \
+				 CFG_CMD_LOADB	| \
+				 CFG_CMD_MEMORY | \
+				 CFG_CMD_MISC	| \
+				 CFG_CMD_NET	| \
+				 CFG_CMD_PING	| \
+				 CFG_CMD_RUN	| \
+				 CFG_CMD_SAVES	)
+#include <cmd_confdefs.h>
+
+/*------------------------------------------------------------------------
+ * MISC
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP				/* Provide extended help*/
+#define CFG_PROMPT		"==> "		/* Command prompt	*/
+#define CFG_CBSIZE		256		/* Console I/O buf size */
+#define CFG_MAXARGS		16		/* Max command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot arg buf size	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */
+#define CFG_LOAD_ADDR		CFG_SDRAM_BASE	/* Default load address */
+#define CFG_MEMTEST_START	CFG_SDRAM_BASE	/* Start addr for test	*/
+#define CFG_MEMTEST_END		CFG_INIT_SP - 0x00020000
+
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/EP1S40.h b/include/configs/EP1S40.h
new file mode 100644
index 0000000..976e79a
--- /dev/null
+++ b/include/configs/EP1S40.h
@@ -0,0 +1,193 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*------------------------------------------------------------------------
+ * BOARD/CPU
+ *----------------------------------------------------------------------*/
+#define CONFIG_EP1S40		1		/* EP1S40 board		*/
+#define CONFIG_SYS_CLK_FREQ	50000000	/* 50 MHz core clk	*/
+
+#define CFG_RESET_ADDR		0x00000000	/* Hard-reset address	*/
+#define CFG_EXCEPTION_ADDR	0x01000020	/* Exception entry point*/
+#define CFG_NIOS_SYSID_BASE	0x021208b8	/* System id address	*/
+
+/*------------------------------------------------------------------------
+ * CACHE -- the following will support II/s and II/f. The II/s does not
+ * have dcache, so the cache instructions will behave as NOPs.
+ *----------------------------------------------------------------------*/
+#define CFG_ICACHE_SIZE		4096		/* 4 KByte total	*/
+#define CFG_ICACHELINE_SIZE	32		/* 32 bytes/line	*/
+#define CFG_DCACHE_SIZE		2048		/* 2 KByte (II/f)	*/
+#define CFG_DCACHELINE_SIZE	4		/* 4 bytes/line (II/f)	*/
+
+/*------------------------------------------------------------------------
+ * MEMORY BASE ADDRESSES
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_BASE		0x00000000	/* FLASH base addr	*/
+#define CFG_FLASH_SIZE		0x00800000	/* 8 MByte		*/
+#define CFG_SDRAM_BASE		0x01000000	/* SDRAM base addr	*/
+#define CFG_SDRAM_SIZE		0x01000000	/* 16 MByte		*/
+#define CFG_SRAM_BASE		0x02000000	/* SRAM base addr	*/
+#define CFG_SRAM_SIZE		0x00100000	/* 1 MB			*/
+
+/*------------------------------------------------------------------------
+ * MEMORY ORGANIZATION
+ *	-Monitor at top.
+ *	-The heap is placed below the monitor.
+ *	-Global data is placed below the heap.
+ *	-The stack is placed below global data (&grows down).
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256k		*/
+#define CFG_GBL_DATA_SIZE	128		/* Global data size rsvd*/
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 256*1024) /* 256k heap */
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
+#define CFG_GBL_DATA_OFFSET	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP		CFG_GBL_DATA_OFFSET
+
+/*------------------------------------------------------------------------
+ * FLASH (AM29LV065D)
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_SECT	128		/* Max # sects per bank */
+#define CFG_MAX_FLASH_BANKS	1		/* Max # of flash banks */
+#define CFG_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
+#define CFG_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
+
+/*------------------------------------------------------------------------
+ * ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above
+ * CFG_FLASH_BASE, since we assume that u-boot is stored at the bottom
+ * of flash memory. This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ *----------------------------------------------------------------------*/
+#define CFG_ENV_IS_IN_FLASH	1		/* Environment in flash */
+#define CFG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
+#define CONFIG_ENV_OVERWRITE			/* Serial change Ok	*/
+#define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_MONITOR_LEN)
+
+/*------------------------------------------------------------------------
+ * CONSOLE
+ *----------------------------------------------------------------------*/
+#if defined(CONFIG_CONSOLE_JTAG)
+#define CFG_NIOS_CONSOLE	0x021208b0	/* JTAG UART base addr	*/
+#else
+#define CFG_NIOS_CONSOLE	0x02120840	/* UART base addr	*/
+#endif
+
+#define CFG_NIOS_FIXEDBAUD	1		/* Baudrate is fixed	*/
+#define CONFIG_BAUDRATE		115200		/* Initial baudrate	*/
+#define CFG_BAUDRATE_TABLE	{115200}	/* It's fixed ;-)	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1		/* Suppress console info*/
+
+/*------------------------------------------------------------------------
+ * EPCS Device -- None for stratix.
+ *----------------------------------------------------------------------*/
+#undef CFG_NIOS_EPCSBASE
+
+/*------------------------------------------------------------------------
+ * DEBUG
+ *----------------------------------------------------------------------*/
+#undef CONFIG_ROM_STUBS				/* Stubs not in ROM	*/
+
+/*------------------------------------------------------------------------
+ * TIMEBASE --
+ *
+ * The high res timer defaults to 1 msec. Since it includes the period
+ * registers, we can slow it down to 10 msec using TMRCNT. If the default
+ * period is acceptable, TMRCNT can be left undefined.
+ *----------------------------------------------------------------------*/
+#define CFG_NIOS_TMRBASE	0x02120820	/* Tick timer base addr */
+#define CFG_NIOS_TMRIRQ		3		/* Timer IRQ num	*/
+#define CFG_NIOS_TMRMS		10		/* 10 msec per tick	*/
+#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
+#define CFG_HZ		(CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1))
+
+/*------------------------------------------------------------------------
+ * STATUS LED -- Provides a simple blinking led. For Nios2 each board
+ * must implement its own led routines -- since leds are board-specific.
+ *----------------------------------------------------------------------*/
+#define CFG_LEDPIO_ADDR		0x02120870	/* LED PIO base addr	*/
+#define CONFIG_STATUS_LED			/* Enable status driver */
+
+#define STATUS_LED_BIT		1		/* Bit-0 on PIO		*/
+#define STATUS_LED_STATE	1		/* Blinking		*/
+#define STATUS_LED_PERIOD	(500/CFG_NIOS_TMRMS) /* Every 500 msec	*/
+
+/*------------------------------------------------------------------------
+ * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
+ * and really doesn't need any additional clutter. So I choose the lazy
+ * way out to avoid changes there -- define the base address to ensure
+ * cache bypass so there's no need to monkey with inx/outx macros.
+ *----------------------------------------------------------------------*/
+#define CONFIG_SMC91111_BASE	0x82110300	/* Base addr (bypass)	*/
+#define CONFIG_DRIVER_SMC91111			/* Using SMC91c111	*/
+#undef	CONFIG_SMC91111_EXT_PHY			/* Internal PHY		*/
+#define CONFIG_SMC_USE_32_BIT			/* 32-bit interface	*/
+
+#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		192.168.2.21
+#define CONFIG_SERVERIP		192.168.2.16
+
+/*------------------------------------------------------------------------
+ * COMMANDS
+ *----------------------------------------------------------------------*/
+#define CONFIG_COMMANDS		(CFG_CMD_BDI	| \
+				 CFG_CMD_DHCP	| \
+				 CFG_CMD_ECHO	| \
+				 CFG_CMD_ENV	| \
+				 CFG_CMD_FLASH	| \
+				 CFG_CMD_IMI	| \
+				 CFG_CMD_IRQ	| \
+				 CFG_CMD_LOADS	| \
+				 CFG_CMD_LOADB	| \
+				 CFG_CMD_MEMORY | \
+				 CFG_CMD_MISC	| \
+				 CFG_CMD_NET	| \
+				 CFG_CMD_PING	| \
+				 CFG_CMD_RUN	| \
+				 CFG_CMD_SAVES	)
+#include <cmd_confdefs.h>
+
+/*------------------------------------------------------------------------
+ * MISC
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP				/* Provide extended help*/
+#define CFG_PROMPT		"==> "		/* Command prompt	*/
+#define CFG_CBSIZE		256		/* Console I/O buf size */
+#define CFG_MAXARGS		16		/* Max command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot arg buf size	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */
+#define CFG_LOAD_ADDR		CFG_SDRAM_BASE	/* Default load address */
+#define CFG_MEMTEST_START	CFG_SDRAM_BASE	/* Start addr for test	*/
+#define CFG_MEMTEST_END		CFG_INIT_SP - 0x00020000
+
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/PK1C20.h b/include/configs/PK1C20.h
index 91e9518..83a7ec2 100644
--- a/include/configs/PK1C20.h
+++ b/include/configs/PK1C20.h
@@ -32,7 +32,7 @@
 
 #define CFG_RESET_ADDR		0x00000000	/* Hard-reset address	*/
 #define CFG_EXCEPTION_ADDR	0x01000020	/* Exception entry point*/
-#define CFG_NIOS_SYSID_BASE	0x00920828	/* System id address	*/
+#define CFG_NIOS_SYSID_BASE	0x021208b8	/* System id address	*/
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* enable early board-spec. init*/
 
 /*------------------------------------------------------------------------
@@ -51,7 +51,7 @@
 #define CFG_FLASH_SIZE		0x00800000	/* 8 MByte		*/
 #define CFG_SDRAM_BASE		0x01000000	/* SDRAM base addr	*/
 #define CFG_SDRAM_SIZE		0x01000000	/* 16 MByte		*/
-#define CFG_SRAM_BASE		0x00800000	/* SRAM base addr	*/
+#define CFG_SRAM_BASE		0x02000000	/* SRAM base addr	*/
 #define CFG_SRAM_SIZE		0x00100000	/* 1 MB (only 1M mapped)*/
 
 /*------------------------------------------------------------------------
@@ -61,7 +61,7 @@
  *	-Global data is placed below the heap.
  *	-The stack is placed below global data (&grows down).
  *----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN		(128 * 1024)	/* Reserve 128k		*/
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 128k		*/
 #define CFG_GBL_DATA_SIZE	128		/* Global data size rsvd*/
 #define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
 
@@ -95,9 +95,9 @@
  * CONSOLE
  *----------------------------------------------------------------------*/
 #if defined(CONFIG_CONSOLE_JTAG)
-#define CFG_NIOS_CONSOLE	0x00920820	/* JTAG UART base addr	*/
+#define CFG_NIOS_CONSOLE	0x021208b0	/* JTAG UART base addr	*/
 #else
-#define CFG_NIOS_CONSOLE	0x009208a0	/* UART base addr	*/
+#define CFG_NIOS_CONSOLE	0x02120840	/* UART base addr	*/
 #endif
 
 #define CFG_NIOS_FIXEDBAUD	1		/* Baudrate is fixed	*/
@@ -110,9 +110,9 @@
  * EPCS Device -- wne CFG_NIOS_EPCSBASE is defined code/commands for
  * epcs device access is enabled. The base address is the epcs
  * _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK.
- * The register base is currently at offset 0x400 from the memory base.
+ * The register base is currently at offset 0x600 from the memory base.
  *----------------------------------------------------------------------*/
-#define CFG_NIOS_EPCSBASE	0x00900400	/* EPCS register base	*/
+#define CFG_NIOS_EPCSBASE	0x02100200	/* EPCS register base	*/
 
 /*------------------------------------------------------------------------
  * DEBUG
@@ -126,7 +126,7 @@
  * registers, we can slow it down to 10 msec using TMRCNT. If the default
  * period is acceptable, TMRCNT can be left undefined.
  *----------------------------------------------------------------------*/
-#define CFG_NIOS_TMRBASE	0x00920860	/* Tick timer base addr */
+#define CFG_NIOS_TMRBASE	0x02120820	/* Tick timer base addr */
 #define CFG_NIOS_TMRIRQ		3		/* Timer IRQ num	*/
 #define CFG_NIOS_TMRMS		10		/* 10 msec per tick	*/
 #define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
@@ -137,7 +137,7 @@
  * must implement its own led routines -- leds are, after all,
  * board-specific, no?
  *----------------------------------------------------------------------*/
-#define CFG_LEDPIO_ADDR		0x00920840	/* LED PIO base addr	*/
+#define CFG_LEDPIO_ADDR		0x02120870	/* LED PIO base addr	*/
 #define CONFIG_STATUS_LED			/* Enable status driver */
 
 #define STATUS_LED_BIT		1		/* Bit-0 on PIO		*/
@@ -150,7 +150,7 @@
  * way out to avoid changes there -- define the base address to ensure
  * cache bypass so there's no need to monkey with inx/outx macros.
  *----------------------------------------------------------------------*/
-#define CONFIG_SMC91111_BASE	0x80910300	/* Base addr (bypass)	*/
+#define CONFIG_SMC91111_BASE	0x82110300	/* Base addr (bypass)	*/
 #define CONFIG_DRIVER_SMC91111			/* Using SMC91c111	*/
 #undef	CONFIG_SMC91111_EXT_PHY			/* Internal PHY		*/
 #define CONFIG_SMC_USE_32_BIT			/* 32-bit interface	*/
diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h
new file mode 100644
index 0000000..50c1c4f
--- /dev/null
+++ b/include/configs/pcs440ep.h
@@ -0,0 +1,412 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * pcs440ep.h - configuration for PCS440EP board
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_PCS440EP		1	/* Board is PCS440EP            */
+#define CONFIG_440EP		1	/* Specific PPC440EP support    */
+#define CONFIG_4xx		1	/* ... PPC4xx family	        */
+#define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN		(384 * 1024)	/* Reserve 384 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+#define CFG_MONITOR_BASE	(-CFG_MONITOR_LEN)
+#define CFG_SDRAM_BASE	        0x00000000	    /* _must_ be 0	*/
+#define CFG_FLASH_BASE	        0xfff00000	    /* start of FLASH	*/
+#define CFG_PCI_MEMBASE	        0xa0000000	    /* mapped pci memory*/
+#define CFG_PCI_MEMBASE1        CFG_PCI_MEMBASE  + 0x10000000
+#define CFG_PCI_MEMBASE2        CFG_PCI_MEMBASE1 + 0x10000000
+#define CFG_PCI_MEMBASE3        CFG_PCI_MEMBASE2 + 0x10000000
+
+/*Don't change either of these*/
+#define CFG_PERIPHERAL_BASE     0xef600000	    /* internal peripherals*/
+#define CFG_PCI_BASE	        0xe0000000	    /* internal PCI regs*/
+/*Don't change either of these*/
+
+#define CFG_USB_DEVICE          0x50000000
+#define CFG_BOOT_BASE_ADDR      0xf0000000
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in SDRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_ADDR	0x70000000		/* DCache       */
+#define CFG_INIT_RAM_END	(8 << 10)
+#define CFG_GBL_DATA_SIZE	256			/* num bytes initial data*/
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef CFG_EXT_SERIAL_CLOCK		/* no external clk used		*/
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SERIAL_MULTI     1
+/*define this if you want console on UART1*/
+#undef CONFIG_UART1_CONSOLE
+
+#define CFG_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE	unsigned char	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE	0x10000 	/* size of one complete sector	*/
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for setup             */
+#undef CONFIG_DDR_ECC			/* don't use ECC			*/
+#define SPD_EEPROM_ADDRESS      {0x50}
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C		1	    /* I2C with hardware support	*/
+#undef	CONFIG_SOFT_I2C			    /* I2C bit-banged		*/
+#define CFG_I2C_SPEED		100000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	(0xa4>>1)
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=pcs440ep\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
+	        "bootm\0"						\
+	"rootpath=/opt/eldk/ppc_4xx\0"					\
+	"bootfile=/tftpboot/pcs440ep/uImage\0"				\
+	"kernel_addr=FFF00000\0"					\
+	"ramdisk_addr=FFF00000\0"					\
+	"load=tftp 100000 /tftpboot/pcs440ep/u-boot.bin\0"		\
+	"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;"	\
+		"cp.b 100000 FFFA0000 60000\0"			        \
+	"upd=run load;run update\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_NET_MULTI        1	/* required for netconsole      */
+#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
+#define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
+#define CONFIG_PHY1_ADDR        2
+
+#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#ifdef CONFIG_440EP
+/* USB */
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+/*Comment this out to enable USB 1.1 device*/
+#define USB_2_0_DEVICE
+#endif /*CONFIG_440EP*/
+
+#ifdef DEBUG
+#define CONFIG_PANIC_HANG
+#else
+#define CONFIG_HW_WATCHDOG			/* watchdog */
+#endif
+
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DIAG	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_NET	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_REGINFO	| \
+				CFG_CMD_SDRAM	| \
+				CFG_CMD_EXT2	| \
+				CFG_CMD_FAT	| \
+				CFG_CMD_USB	)
+
+
+#define CONFIG_SUPPORT_VFAT
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	        16	/* max number of command args	*/
+#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000 /* memtest works on	        */
+#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+#define CONFIG_LYNXKDI          1       /* support kdi files            */
+
+#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI			/* include pci support	        */
+#undef  CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
+#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
+#define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT                /* enable board pci_pre_init()  */
+#define CFG_PCI_TARGET_INIT
+#define CFG_PCI_MASTER_INIT
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CFG_PCI_SUBSYS_ID       0xcafe	/* Whatever */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+#define FLASH_BASE0_PRELIM	0xFFF00000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0xFFF80000	/* FLASH bank #1	*/
+
+#define CFG_FLASH		FLASH_BASE0_PRELIM
+#define CFG_SRAM		0xF1000000
+#define CFG_FPGA		0xF2000000
+#define CFG_CF1			0xF0000000
+#define CFG_CF2			0xF0100000
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CFG_EBC_PB0AP		0x02010000	/* TWT=4,OEN=1			*/
+#define CFG_EBC_PB0CR		(CFG_FLASH | 0x18000) /* BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 1 (SRAM) initialization						*/
+#define CFG_EBC_PB1AP		0x01810040	/* TWT=3,OEN=1,BEM=1		*/
+#define CFG_EBC_PB1CR		(CFG_SRAM | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit	*/
+
+/* Memory Bank 2 (FPGA) initialization						*/
+#define CFG_EBC_PB2AP		0x01010440	/* TWT=2,OEN=1,TH=2,BEM=1	*/
+#define CFG_EBC_PB2CR		(CFG_FPGA | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit	*/
+
+/* Memory Bank 3 (CompactFlash) initialization					*/
+#define CFG_EBC_PB3AP		0x080BD400
+#define CFG_EBC_PB3CR		(CFG_CF1 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit	*/
+
+/* Memory Bank 4 (CompactFlash) initialization					*/
+#define CFG_EBC_PB4AP		0x080BD400
+#define CFG_EBC_PB4CR		(CFG_CF2 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit	*/
+
+/*-----------------------------------------------------------------------
+ * PPC440 GPIO Configuration
+ */
+#define CFG_440_GPIO_TABLE { /*		GPIO	Alternate1	Alternate2	Alternate3 */ \
+{											\
+/* GPIO Core 0 */									\
+{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO0	EBC_ADDR(7)	DMA_REQ(2)	*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO1	EBC_ADDR(6)	DMA_ACK(2)	*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO2	EBC_ADDR(5)	DMA_EOT/TC(2)	*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO3	EBC_ADDR(4)	DMA_REQ(3)	*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO4	EBC_ADDR(3)	DMA_ACK(3)	*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO5	EBC_ADDR(2)	DMA_EOT/TC(3)	*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO6	EBC_CS_N(1)			*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO7	EBC_CS_N(2)			*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO8	EBC_CS_N(3)			*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO9	EBC_CS_N(4)			*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO10	EBC_CS_N(5)			*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO11	EBC_BUS_ERR			*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO12	ZII_p0Rxd(0)			*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO13	ZII_p0Rxd(1)			*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO14	ZII_p0Rxd(2)			*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO15	ZII_p0Rxd(3)			*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO16	ZII_p0Txd(0)			*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO17	ZII_p0Txd(1)			*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO18	ZII_p0Txd(2)			*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO19	ZII_p0Txd(3)			*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO20	ZII_p0Rx_er			*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO21	ZII_p0Rx_dv			*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO22	ZII_p0RxCrs			*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO23	ZII_p0Tx_er			*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO24	ZII_p0Tx_en			*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO25	ZII_p0Col			*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO26			USB2D_RXVALID	*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO27	EXT_EBC_REQ	USB2D_RXERROR	*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO28			USB2D_TXVALID	*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO29	EBC_EXT_HDLA	USB2D_PAD_SUSPNDM */	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO30	EBC_EXT_ACK	USB2D_XCVRSELECT*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO31	EBC_EXR_BUSREQ	USB2D_TERMSELECT*/	\
+},											\
+{											\
+/* GPIO Core 1 */									\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO32	USB2D_OPMODE0			*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO33	USB2D_OPMODE1			*/	\
+{ GPIO1_BASE, GPIO_OUT, GPIO_ALT3 }, /* GPIO34	UART0_DCD_N	UART1_DSR_CTS_N	UART2_SOUT*/ \
+{ GPIO1_BASE, GPIO_IN,  GPIO_ALT3 }, /* GPIO35	UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
+{ GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO36	UART0_8PIN_CTS_N		UART3_SIN*/ \
+{ GPIO1_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO37	UART0_RTS_N			*/	\
+{ GPIO1_BASE, GPIO_OUT, GPIO_ALT2 }, /* GPIO38	UART0_DTR_N	UART1_SOUT	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_ALT2 }, /* GPIO39	UART0_RI_N	UART1_SIN	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO40	UIC_IRQ(0)			*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO41	UIC_IRQ(1)			*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO42	UIC_IRQ(2)			*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO43	UIC_IRQ(3)			*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO44	UIC_IRQ(4)	DMA_ACK(1)	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO45	UIC_IRQ(6)	DMA_EOT/TC(1)	*/	\
+{ GPIO1_BASE, GPIO_BI,  GPIO_SEL },  /* GPIO46	UIC_IRQ(7)	DMA_REQ(0)	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO47	UIC_IRQ(8)	DMA_ACK(0)	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO48	UIC_IRQ(9)	DMA_EOT/TC(0)	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO49  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO50  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO51  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO52  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO53  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO54  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO55  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO56  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO57  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO58  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO59  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO60  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO61  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO62  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO63  Unselect via TraceSelect Bit	*/	\
+}											\
+}
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		(32<<10) /* For AMCC 440 CPUs			*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/nios2-epcs.h b/include/nios2-epcs.h
index 2c9522c..20e0c87 100644
--- a/include/nios2-epcs.h
+++ b/include/nios2-epcs.h
@@ -38,6 +38,11 @@ typedef struct epcs_devinfo_t {
 	unsigned char   prot_mask;	/* Protection mask */
 }epcs_devinfo_t;
 
+/* Resets the epcs controller -- to prevent (potential) soft-reset
+ * problems when booting from the epcs controller
+ */
+extern int epcs_reset (void);
+
 /* Returns the devinfo struct if EPCS device is found;
  * NULL otherwise.
  */
diff --git a/include/ppc440.h b/include/ppc440.h
index 018f7be..53f14b5 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -1357,56 +1357,106 @@
 /******************************************************************************
  * GPIO macro register defines
  ******************************************************************************/
+#define GPIO0			0
+#define GPIO1			1
+
 #if defined(CONFIG_440GP)
-#define GPIO_BASE0             (CFG_PERIPHERAL_BASE+0x00000700)
+#define GPIO0_BASE             (CFG_PERIPHERAL_BASE+0x00000700)
 
-#define GPIO0_OR               (GPIO_BASE0+0x0)
-#define GPIO0_TCR              (GPIO_BASE0+0x4)
-#define GPIO0_ODR              (GPIO_BASE0+0x18)
-#define GPIO0_IR               (GPIO_BASE0+0x1C)
+#define GPIO0_OR               (GPIO0_BASE+0x0)
+#define GPIO0_TCR              (GPIO0_BASE+0x4)
+#define GPIO0_ODR              (GPIO0_BASE+0x18)
+#define GPIO0_IR               (GPIO0_BASE+0x1C)
 #endif /* CONFIG_440GP */
 
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
-#define GPIO_BASE0             (CFG_PERIPHERAL_BASE+0x00000B00)
-#define GPIO_BASE1             (CFG_PERIPHERAL_BASE+0x00000C00)
-
-#define GPIO0_OR               (GPIO_BASE0+0x0)
-#define GPIO0_TCR              (GPIO_BASE0+0x4)
-#define GPIO0_OSRL             (GPIO_BASE0+0x8)
-#define GPIO0_OSRH             (GPIO_BASE0+0xC)
-#define GPIO0_TSRL             (GPIO_BASE0+0x10)
-#define GPIO0_TSRH             (GPIO_BASE0+0x14)
-#define GPIO0_ODR              (GPIO_BASE0+0x18)
-#define GPIO0_IR               (GPIO_BASE0+0x1C)
-#define GPIO0_RR1              (GPIO_BASE0+0x20)
-#define GPIO0_RR2              (GPIO_BASE0+0x24)
-#define GPIO0_RR3	       (GPIO_BASE0+0x28)
-#define GPIO0_ISR1L            (GPIO_BASE0+0x30)
-#define GPIO0_ISR1H            (GPIO_BASE0+0x34)
-#define GPIO0_ISR2L            (GPIO_BASE0+0x38)
-#define GPIO0_ISR2H            (GPIO_BASE0+0x3C)
-#define GPIO0_ISR3L            (GPIO_BASE0+0x40)
-#define GPIO0_ISR3H            (GPIO_BASE0+0x44)
-
-#define GPIO1_OR               (GPIO_BASE1+0x0)
-#define GPIO1_TCR              (GPIO_BASE1+0x4)
-#define GPIO1_OSRL             (GPIO_BASE1+0x8)
-#define GPIO1_OSRH             (GPIO_BASE1+0xC)
-#define GPIO1_TSRL             (GPIO_BASE1+0x10)
-#define GPIO1_TSRH             (GPIO_BASE1+0x14)
-#define GPIO1_ODR              (GPIO_BASE1+0x18)
-#define GPIO1_IR               (GPIO_BASE1+0x1C)
-#define GPIO1_RR1              (GPIO_BASE1+0x20)
-#define GPIO1_RR2              (GPIO_BASE1+0x24)
-#define GPIO1_RR3              (GPIO_BASE1+0x28)
-#define GPIO1_ISR1L            (GPIO_BASE1+0x30)
-#define GPIO1_ISR1H            (GPIO_BASE1+0x34)
-#define GPIO1_ISR2L            (GPIO_BASE1+0x38)
-#define GPIO1_ISR2H            (GPIO_BASE1+0x3C)
-#define GPIO1_ISR3L            (GPIO_BASE1+0x40)
-#define GPIO1_ISR3H            (GPIO_BASE1+0x44)
+#define GPIO0_BASE             (CFG_PERIPHERAL_BASE+0x00000B00)
+#define GPIO1_BASE             (CFG_PERIPHERAL_BASE+0x00000C00)
+
+/* Offsets */
+#define GPIOx_OR    0x00	/* GPIO Output Register */
+#define GPIOx_TCR   0x04	/* GPIO Three-State Control Register */
+#define GPIOx_OSL   0x08	/* GPIO Output Select Register (Bits 0-31) */
+#define GPIOx_OSH   0x0C	/* GPIO Ouput Select Register (Bits 32-63) */
+#define GPIOx_TSL   0x10	/* GPIO Three-State Select Register (Bits 0-31) */
+#define GPIOx_TSH   0x14	/* GPIO Three-State Select Register  (Bits 32-63) */
+#define GPIOx_ODR   0x18	/* GPIO Open drain Register */
+#define GPIOx_IR    0x1C	/* GPIO Input Register */
+#define GPIOx_RR1   0x20	/* GPIO Receive Register 1 */
+#define GPIOx_RR2   0x24	/* GPIO Receive Register 2 */
+#define GPIOx_RR3   0x28	/* GPIO Receive Register 3 */
+#define GPIOx_IS1L  0x30	/* GPIO Input Select Register 1 (Bits 0-31) */
+#define GPIOx_IS1H  0x34	/* GPIO Input Select Register 1 (Bits 32-63) */
+#define GPIOx_IS2L  0x38	/* GPIO Input Select Register 2 (Bits 0-31) */
+#define GPIOx_IS2H  0x3C	/* GPIO Input Select Register 2 (Bits 32-63) */
+#define GPIOx_IS3L  0x40	/* GPIO Input Select Register 3 (Bits 0-31) */
+#define GPIOx_IS3H  0x44	/* GPIO Input Select Register 3 (Bits 32-63) */
+
+#define GPIO_OS(x)	(x+GPIOx_OSL)	/* GPIO Output Register High or Low */
+#define GPIO_TS(x)	(x+GPIOx_TSL)	/* GPIO Three-state Control Reg High or Low */
+#define GPIO_IS1(x)	(x+GPIOx_IS1L)	/* GPIO Input register1 High or Low */
+#define GPIO_IS2(x)	(x+GPIOx_IS2L)	/* GPIO Input register2 High or Low */
+#define GPIO_IS3(x)	(x+GPIOx_IS3L)	/* GPIO Input register3 High or Low */
+
+#define GPIO0_OR               (GPIO0_BASE+0x0)
+#define GPIO0_TCR              (GPIO0_BASE+0x4)
+#define GPIO0_OSRL             (GPIO0_BASE+0x8)
+#define GPIO0_OSRH             (GPIO0_BASE+0xC)
+#define GPIO0_TSRL             (GPIO0_BASE+0x10)
+#define GPIO0_TSRH             (GPIO0_BASE+0x14)
+#define GPIO0_ODR              (GPIO0_BASE+0x18)
+#define GPIO0_IR               (GPIO0_BASE+0x1C)
+#define GPIO0_RR1              (GPIO0_BASE+0x20)
+#define GPIO0_RR2              (GPIO0_BASE+0x24)
+#define GPIO0_RR3	       (GPIO0_BASE+0x28)
+#define GPIO0_ISR1L            (GPIO0_BASE+0x30)
+#define GPIO0_ISR1H            (GPIO0_BASE+0x34)
+#define GPIO0_ISR2L            (GPIO0_BASE+0x38)
+#define GPIO0_ISR2H            (GPIO0_BASE+0x3C)
+#define GPIO0_ISR3L            (GPIO0_BASE+0x40)
+#define GPIO0_ISR3H            (GPIO0_BASE+0x44)
+
+#define GPIO1_OR               (GPIO1_BASE+0x0)
+#define GPIO1_TCR              (GPIO1_BASE+0x4)
+#define GPIO1_OSRL             (GPIO1_BASE+0x8)
+#define GPIO1_OSRH             (GPIO1_BASE+0xC)
+#define GPIO1_TSRL             (GPIO1_BASE+0x10)
+#define GPIO1_TSRH             (GPIO1_BASE+0x14)
+#define GPIO1_ODR              (GPIO1_BASE+0x18)
+#define GPIO1_IR               (GPIO1_BASE+0x1C)
+#define GPIO1_RR1              (GPIO1_BASE+0x20)
+#define GPIO1_RR2              (GPIO1_BASE+0x24)
+#define GPIO1_RR3              (GPIO1_BASE+0x28)
+#define GPIO1_ISR1L            (GPIO1_BASE+0x30)
+#define GPIO1_ISR1H            (GPIO1_BASE+0x34)
+#define GPIO1_ISR2L            (GPIO1_BASE+0x38)
+#define GPIO1_ISR2H            (GPIO1_BASE+0x3C)
+#define GPIO1_ISR3L            (GPIO1_BASE+0x40)
+#define GPIO1_ISR3H            (GPIO1_BASE+0x44)
 #endif
 
+#define GPIO_GROUP_MAX	    2
+#define GPIO_MAX	    32
+#define GPIO_ALT1_SEL	    0x40000000	    /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */
+#define GPIO_ALT2_SEL	    0x80000000	    /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */
+#define GPIO_ALT3_SEL	    0xC0000000	    /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */
+#define GPIO_MASK	    0xC0000000	    /* GPIO_MASK */
+#define GPIO_IN_SEL	    0x40000000	    /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */
+					    /* For the other GPIO number, you must shift */
+
+#ifndef __ASSEMBLY__
+
+typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t;
+typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
+
+typedef struct { unsigned long	add;	/* gpio core base address */
+	gpio_driver_t  in_out; /* Driver Setting */
+	gpio_select_t  alt_nb; /* Selected Alternate */
+} gpio_param_s;
+
+
+#endif /* __ASSEMBLY__ */
+
 /*
  * Macros for accessing the indirect EBC registers
  */