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| author | Eric Sun <jian.sun@freescale.com> | 2012-07-03 16:27:08 +0800 |
|---|---|---|
| committer | Eric Sun <jian.sun@freescale.com> | 2012-07-03 16:53:58 +0800 |
| commit | 34863332fbd5c9347ed57d9069bf17cc46ff79ba (patch) | |
| tree | 1070b42b6ee3c09e8cd2551bc954835239e35899 /include | |
| parent | b2185088753902a7ea7c04fe755f51383cdc6412 (diff) | |
| download | u-boot-imx-34863332fbd5c9347ed57d9069bf17cc46ff79ba.zip u-boot-imx-34863332fbd5c9347ed57d9069bf17cc46ff79ba.tar.gz u-boot-imx-34863332fbd5c9347ed57d9069bf17cc46ff79ba.tar.bz2 | |
ENGR00215633 MX6DL LPDDR2 : enable plugin mode of system boot
For MX6DL LPDDR2 board, in order to use both the 2 channels of the memory, the
"PL301_FAST2" must be set to 0x1. However this bit is not accessible using
DCD. Plugin mode must be utilized for this purpose.
The patch can be verified this way:
Enter U-boot console
> mw.l 0x80000000 0xC0 10
> mw.l 0x10000000 0xC1 10
> md.l 0x10000000 10
> md.l 0x80000000 10
Before the patch, 0x10000000 and 0x80000000 in fact point to the
same memory location. So the last 2 dump will show memory content of
both 0x000000C1
After the patch, 0x80000000 ponit to channel 0, 0x10000000 point to
channel 1. the last 2 dump will show memory content of 0x000000C0
and 0x000000C1 respectively
Signed-off-by: Eric Sun <jian.sun@freescale.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/mx6dl_arm2_lpddr2.h | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/include/configs/mx6dl_arm2_lpddr2.h b/include/configs/mx6dl_arm2_lpddr2.h index 94d1985..861b9ee 100644 --- a/include/configs/mx6dl_arm2_lpddr2.h +++ b/include/configs/mx6dl_arm2_lpddr2.h @@ -41,6 +41,8 @@ #undef CONFIG_ARCH_MMU /* disable MMU first */ #define CONFIG_L2_OFF /* disable L2 cache first*/ +#define CONFIG_FLASH_PLUG_IN /*Necessary to enable 2-channel mode*/ + #define CONFIG_MX6_HCLK_FREQ 24000000 #define CONFIG_DISPLAY_CPUINFO @@ -262,16 +264,16 @@ /*----------------------------------------------------------------------- * Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_NR_DRAM_BANKS 2 #define PHYS_SDRAM_1 CSD0_DDR_BASE_ADDR -#ifdef CONFIG_DDR_32BIT -#define PHYS_SDRAM_1_SIZE (1u * 1024 * 1024 * 1024) -#else -#define PHYS_SDRAM_1_SIZE (2u * 1024 * 1024 * 1024) -#endif +#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024) +#define PHYS_SDRAM_2 CSD1_DDR_BASE_ADDR +#define PHYS_SDRAM_2_SIZE (256 * 1024 * 1024) #define iomem_valid_addr(addr, size) \ - (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + ((addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) || \ + (addr >= PHYS_SDRAM_2 && addr <= (PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE))) +#define IRAM_FREE_START 0x00907000 /*----------------------------------------------------------------------- * FLASH and environment organization */ |