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| author | Andy Fleming <afleming@freescale.com> | 2007-08-15 20:03:34 -0500 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2007-08-16 12:12:51 +0200 |
| commit | b96c83d4ae475a70ef2635cd0e748174c44c8601 (patch) | |
| tree | ef1782f96eb6f75e8a7ebaeea5b72f89fc07c8ce /include | |
| parent | 3a79013e2adda53332dfd0b511066a805e929a9d (diff) | |
| download | u-boot-imx-b96c83d4ae475a70ef2635cd0e748174c44c8601.zip u-boot-imx-b96c83d4ae475a70ef2635cd0e748174c44c8601.tar.gz u-boot-imx-b96c83d4ae475a70ef2635cd0e748174c44c8601.tar.bz2 | |
Fix numerous bugs in the 8568 UEC support
Actually, fixed a large bug in the UEC for *all* platforms.
How did this ever work?
uec_init() did not follow the spec for eth_init(), and returned
0 on success. Switch it to return the link like tsec_init()
(and 0 on error)
The immap for the 8568 was defined based on MPC8568, rather than
CONFIG_MPC8568
CONFIG_QE was off
CONFIG_ETHPRIME was set to "Freescale GETH". Now is "FSL UEC0"
Fixed a comment about the ranges for CONFIG_ETHPRIME if TSEC_ENET is
enabled
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-ppc/immap_85xx.h | 2 | ||||
| -rw-r--r-- | include/configs/MPC8568MDS.h | 6 |
2 files changed, 4 insertions, 4 deletions
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 3d4816f..496fc72 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -1596,7 +1596,7 @@ typedef struct ccsr_gur { uint svr; /* 0xe00a4 - System version register */ char res10a[8]; uint rstcr; /* 0xe00b0 - Reset control register */ -#ifdef MPC8568 +#ifdef CONFIG_MPC8568 char res10b[76]; par_io_t qe_par_io[7]; /* 0xe0100 - 0xe01bf */ char res10c[3136]; diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 6b824ed..80ccda5 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -35,7 +35,7 @@ #define CONFIG_PCI #define CONFIG_TSEC_ENET /* tsec ethernet support */ -#undef CONFIG_QE /* Enable QE */ +#define CONFIG_QE /* Enable QE */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_DLL /* possible DLL fix needed */ @@ -348,7 +348,7 @@ extern unsigned long get_clock_freq(void); */ #define CONFIG_UEC_ETH #ifndef CONFIG_TSEC_ENET -#define CONFIG_ETHPRIME "Freescale GETH" +#define CONFIG_ETHPRIME "FSL UEC0" #endif #define CONFIG_PHY_MODE_NEED_CHANGE #define CONFIG_eTSEC_MDIO_BUS @@ -409,7 +409,7 @@ extern unsigned long get_clock_freq(void); #define TSEC1_FLAGS TSEC_GIGABIT #define TSEC2_FLAGS TSEC_GIGABIT -/* Options are: eTSEC[0-3] */ +/* Options are: eTSEC[0-1] */ #define CONFIG_ETHPRIME "eTSEC0" #endif /* CONFIG_TSEC_ENET */ |