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| author | Stefan Roese <sr@denx.de> | 2007-05-11 12:01:49 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-05-11 12:01:49 +0200 |
| commit | 61936667e86a250ae12fd2dc189d3588f0a59e0b (patch) | |
| tree | 3fbbd332d4dd0e6063ebe35beff682515f6e6723 /include | |
| parent | 343c48bd84606c4025c8a7c7263fda465d6e284c (diff) | |
| download | u-boot-imx-61936667e86a250ae12fd2dc189d3588f0a59e0b.zip u-boot-imx-61936667e86a250ae12fd2dc189d3588f0a59e0b.tar.gz u-boot-imx-61936667e86a250ae12fd2dc189d3588f0a59e0b.tar.bz2 | |
ppc4xx: Add mtcpr/mfcpr access macros
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include')
| -rw-r--r-- | include/ppc440.h | 20 |
1 files changed, 17 insertions, 3 deletions
diff --git a/include/ppc440.h b/include/ppc440.h index bc1d7aa..07f75de 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -1425,9 +1425,6 @@ /*----------------------------------------------------------------------------+ | Clock / Power-on-reset DCR's. +----------------------------------------------------------------------------*/ -#define CPR0_CFGADDR 0x00C -#define CPR0_CFGDATA 0x00D - #define CPR0_CLKUPD 0x20 #define CPR0_CLKUPD_BSY_MASK 0x80000000 #define CPR0_CLKUPD_BSY_COMPLETED 0x00000000 @@ -3314,6 +3311,23 @@ #define mtsdr(reg, data) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } while (0) #define mfsdr(reg, data) do { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } while (0) +/* + * All 44x except 440GP have CPR registers (indirect DCR) + */ +#if !defined(CONFIG_440GP) +#define CPR0_CFGADDR 0x00C +#define CPR0_CFGDATA 0x00D + +#define mtcpr(reg, data) do { \ + mtdcr(CPR0_CFGADDR, reg); \ + mtdcr(CPR0_CFGDATA, data); \ + } while (0) + +#define mfcpr(reg, data) do { \ + mtdcr(CPR0_CFGADDR, reg); \ + data = mfdcr(CPR0_CFGDATA); \ + } while (0) +#endif #ifndef __ASSEMBLY__ |