* Patch by Rishi Bhattacharya, 08 May 2004:

  Add support for TI OMAP5912 OSK Board

* Patch by Sam Song May, 07 May 2004:
  Fix typo of UPM table for rmu board

5 files changed, 264 insertions, 130 deletions

diff --git a/include/configs/h2_p2_dbg_board.h b/include/configs/h2_p2_dbg_board.h
index 8a5ec34..6082d2c 100644
--- a/include/configs/h2_p2_dbg_board.h
+++ b/include/configs/h2_p2_dbg_board.h
@@ -31,13 +31,11 @@
 #ifndef __INCLUDED_H2_P2_DBH_BOARD_H
 #define __INCLUDED_H2_P2_DBH_BOARD_H
 
-
 #include <asm/arch/sizes.h>
 
-
 /*
  * The Debug board is designed to function with the P2 Sample, H2
- * Sample and 1610 Innovator boards. The main difference AFAICT is 
+ * Sample and 1610 Innovator boards. The main difference AFAICT is
  * the chip selects used with each system ;
  *
  *   P2 Sample : CS1 of OMAP730 is used to select the CPLD & LAN regs
@@ -45,8 +43,6 @@
  *
  */
 
-
-
 /***************************************************************************
  * CPLD Registers
  **************************************************************************/
@@ -60,8 +56,6 @@
 #define H2DBG_LAN_RESET            0x0400001C
 #define H2DBG_ETH_REG_BASE         0x04000300
 
-
-
 /***************************************************************************
  * Ethernet Control Registers
  * These are for the LAN91C96 on the debug board
@@ -107,7 +101,7 @@
 #ifndef __ASSEMBLY__
 
 /*
- * A couple of utility inlines to aid debugging using the LED's on the 
+ * A couple of utility inlines to aid debugging using the LED's on the
  * debug board.
  */
 
@@ -122,7 +116,7 @@ static inline void set_led_state(int state)
 
 
 static inline void spin_up_leds()
-{                                  
+{
 	volatile int i, j, k;
 
 	for (k = 0; k < 2; k++) {
@@ -142,4 +136,3 @@ static inline void spin_up_leds()
 #endif    /* !  __ASSEMBLY__ */
 
 #endif    /* !  __INCLUDED_H2_P2_DBH_BOARD_H */
-
diff --git a/include/configs/omap5912osk.h b/include/configs/omap5912osk.h
new file mode 100644
index 0000000..43be807
--- /dev/null
+++ b/include/configs/omap5912osk.h
@@ -0,0 +1,176 @@
+/*
+ * (C) Copyright 2003
+ * Texas Instruments.
+ * Kshitij Gupta <kshitij@ti.com>
+ * Configuation settings for the TI OMAP Innovator board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * If we are developing, we might want to start armboot from ram
+ * so we MUST NOT initialize critical regs like mem-timing ...
+ */
+
+#define CONFIG_INIT_CRITICAL		/*undef for developing */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM926EJS	1	/* This is an arm926ejs CPU core  */
+#define CONFIG_OMAP	1			/* in a TI OMAP core    */
+#define CONFIG_OMAP1610	1		/* 5912 is same as 1610  */
+#define CONFIG_OSK_OMAP5912	1	/*  a OSK Board  */
+
+/* input clock of PLL */
+/* the OMAP5912 OSK has 12MHz input clock */
+#define CONFIG_SYS_CLK_FREQ	12000000
+
+#undef CONFIG_USE_IRQ	/* we don't need IRQ/FIQ stuff */
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs  */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN	(CFG_ENV_SIZE + 128*1024)
+
+/*
+ * Hardware drivers
+ */
+/*
+*/
+#define CONFIG_DRIVER_LAN91C96
+#define CONFIG_LAN91C96_BASE 0x04800300
+#define CONFIG_LAN91C96_EXT_PHY
+
+/*
+ * NS16550 Configuration
+ */
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	(-4)
+#define CFG_NS16550_CLK	(48000000)	/* can be 12M/32Khz or 48Mhz */
+#define CFG_NS16550_COM1	0xfffb0000	/* uart1, bluetooth uart
+						on helen */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1	1	/* we use SERIAL 1 on OMAP5912 OSK */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE	115200
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_DHCP)
+#define CONFIG_BOOTP_MASK	CONFIG_BOOTP_DEFAULT
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+#include <configs/omap1510.h>
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS	"mem=32M console=ttyS0,115200n8 noinitrd \
+				root=/dev/nfs rw nfsroot=157.87.82.48:\
+				/home/mwd/myfs/target ip=dhcp"
+#define CONFIG_NETMASK	255.255.254.0	/* talk on MY local net */
+#define CONFIG_IPADDR	156.117.97.156	/* static IP I currently own */
+#define CONFIG_SERVERIP	156.117.97.139	/* current IP of my dev pc */
+#define CONFIG_BOOTFILE	"uImage"	/* file to load */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	1	/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP	/* undef to save memory     */
+#define CFG_PROMPT	"OMAP5912 OSK # "	/* Monitor Command Prompt   */
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size  */
+/* Print Buffer Size */
+#define CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS	16		/* max number of command args   */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size    */
+
+#define CFG_MEMTEST_START	0x10000000	/* memtest works on */
+#define CFG_MEMTEST_END	0x12000000	/* 32 MB in DRAM    */
+
+#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR	0x10000000	/* default load address */
+
+/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by
+ * DPLL1. This time is further subdivided by a local divisor.
+ */
+#define CFG_TIMERBASE	0xFFFEC500	/* use timer 1 */
+#define CFG_PVT	7	/* 2^(pvt+1), divide by 256 */
+#define CFG_HZ	((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1	0x10000000	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x02000000	/* 32 MB */
+
+#define PHYS_FLASH_1	0x00000000	/* Flash Bank #1 */
+
+#define CFG_FLASH_BASE	PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define PHYS_FLASH_SIZE	0x02000000	/* 32MB */
+#define CFG_MAX_FLASH_SECT	(259)	/* max number of sectors on one chip */
+/* addr of environment */
+#define CFG_ENV_ADDR	(CFG_FLASH_BASE + 0x020000)
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(20*CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(20*CFG_HZ)	/* Timeout for Flash Write */
+
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE	0x20000	/* Total Size of Environment Sector */
+#define CFG_ENV_OFFSET	0x20000	/* environment starts here  */
+
+#endif							/* __CONFIG_H */
diff --git a/include/configs/omap730.h b/include/configs/omap730.h
index 5fbbeb0..03abcb3 100644
--- a/include/configs/omap730.h
+++ b/include/configs/omap730.h
@@ -28,15 +28,11 @@
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
-
 #ifndef __INCLUDED_OMAP730_H
 #define __INCLUDED_OMAP730_H
 
 #include <asm/arch/sizes.h>
 
-
-
-
 /***************************************************************************
  * OMAP730 Configuration Registers
  **************************************************************************/
@@ -87,9 +83,6 @@
 #define DEBUG2                            ((unsigned int)(0xFFFE10E4))
 #define DEBUG_DMA_IRQ                     ((unsigned int)(0xFFFE10E8))
 
-
-
-
 /***************************************************************************
  * OMAP730 EMIFS Registers                                       (TRM 2.5.7)
  **************************************************************************/
@@ -114,8 +107,6 @@
 #define FLASH_ACFG_2_1             (TCMIF_BASE + 0x58)
 #define FLASH_ACFG_3_1             (TCMIF_BASE + 0x5C)
 
-
-
 /***************************************************************************
  * OMAP730 Interrupt handlers
  **************************************************************************/
@@ -123,12 +114,10 @@
 #define OMAP_IH1_BASE		0xFFFECB00     /* MPU Level 1 IRQ handler */
 #define OMAP_IH2_BASE           0xfffe0000
 
-
-
 /***************************************************************************
  * OMAP730 Timers
  *
- * There are three general purpose OS timers in the 730 that can be 
+ * There are three general purpose OS timers in the 730 that can be
  * configured in autoreload or one-shot modes.
  **************************************************************************/
 
@@ -166,8 +155,6 @@
 #define MPUTIM_AR                 (1<<1)
 #define MPUTIM_ST                 (1<<0)
 
-
-
 /***************************************************************************
  * OMAP730 GPIO
  *
@@ -231,9 +218,6 @@
 #define GPIO_INTERRUPT_MASK_6        ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_MASK))
 #define GPIO_INTERRUPT_STATUS_6      ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_STATUS))
 
-
-
-
 /***************************************************************************
  * OMAP730 Watchdog timers
  **************************************************************************/
@@ -244,16 +228,13 @@
 #define WDTIM_READ                 (WDTIM_BASE + 0x04)    /* MPU_READ_TIMER */
 #define WDTIM_MODE                 (WDTIM_BASE + 0x08)    /* MPU_TIMER_MODE */
 
-
-
-
 /***************************************************************************
  * OMAP730 Interrupt Registers
  **************************************************************************/
 
 /* Interrupt Register offsets */
 
-#define IRQ_ITR                               0x00  
+#define IRQ_ITR                               0x00
 #define IRQ_MIR                               0x04
 #define IRQ_SIR_IRQ                           0x10
 #define IRQ_SIR_FIQ                           0x14
@@ -265,14 +246,12 @@
 #define REG_IHL1_MIR  (OMAP_IH1_BASE + IRQ_MIR)
 #define REG_IHL2_MIR  (OMAP_IH2_BASE + IRQ_MIR)
 
-
 /***************************************************************************
  * OMAP730 Intersystem Communication Register                      (TRM 4.5)
  **************************************************************************/
- 
- 
+
 #define ICR_BASE                   0xFFFBB800
- 
+
 #define M_ICR                      (ICR_BASE + 0x00)
 #define G_ICR                      (ICR_BASE + 0x02)
 #define M_CTL                      (ICR_BASE + 0x04)
@@ -282,6 +261,4 @@
 #define RM_BA                      (ICR_BASE + 0x0E)
 #define SSPI_TAS                   (ICR_BASE + 0x12)
 
-
-
 #endif /* ! __INCLUDED_OMAP730_H */
diff --git a/include/configs/omap730p2.h b/include/configs/omap730p2.h
index fe200c1..ace380f 100644
--- a/include/configs/omap730p2.h
+++ b/include/configs/omap730p2.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2003-2004 
+ * (C) Copyright 2003-2004
  * MPC Data Limited (http://www.mpc-data.co.uk)
  * Dave Peverley <dpeverley at mpc-data.co.uk>
  *
@@ -15,7 +15,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.		See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -27,141 +27,130 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-
 /*
  * If we are developing, we might want to start armboot from ram
  * so we MUST NOT initialize critical regs like mem-timing ...
  */
 
-#define CONFIG_INIT_CRITICAL                 /* undef for developing */
-
+#define CONFIG_INIT_CRITICAL		     /* undef for developing */
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 
-
 /*
  * High Level Configuration Options
  * (easy to change)
  */
 
-#define CONFIG_ARM926EJS           1         /* This is an arm926ejs CPU core  */
-#define CONFIG_OMAP                1         /* in a TI OMAP core    */
-#define CONFIG_OMAP730             1         /* which is in a 730  */
-#define CONFIG_P2_OMAP730          1         /*  a Perseus 2 Board  */
+#define CONFIG_ARM926EJS	   1	     /* This is an arm926ejs CPU core  */
+#define CONFIG_OMAP		   1	     /* in a TI OMAP core    */
+#define CONFIG_OMAP730		   1	     /* which is in a 730  */
+#define CONFIG_P2_OMAP730	   1	     /*	 a Perseus 2 Board  */
 
-
-/* 
- * Input clock of PLL 
- * The OMAP730 Perseus 2 has 13MHz input clock 
+/*
+ * Input clock of PLL
+ * The OMAP730 Perseus 2 has 13MHz input clock
  */
 
-#define CONFIG_SYS_CLK_FREQ        13000000
+#define CONFIG_SYS_CLK_FREQ	   13000000
 
-#undef CONFIG_USE_IRQ                        /* we don't need IRQ/FIQ stuff */
+#undef CONFIG_USE_IRQ			     /* we don't need IRQ/FIQ stuff */
 
 #define CONFIG_MISC_INIT_R
 
-#define CONFIG_CMDLINE_TAG         1         /* enable passing of ATAGs  */
+#define CONFIG_CMDLINE_TAG	   1	     /* enable passing of ATAGs	 */
 #define CONFIG_SETUP_MEMORY_TAGS   1
 
-
 /*
  * Size of malloc() pool
  */
 
-#define CFG_MALLOC_LEN             (CFG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE          128       /* size in bytes reserved for initial data */
-
+#define CFG_MALLOC_LEN		   (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	   128	     /* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
  */
 
 #define CONFIG_DRIVER_LAN91C96
-#define CONFIG_LAN91C96_BASE       0x04000300
+#define CONFIG_LAN91C96_BASE	   0x04000300
 #define CONFIG_LAN91C96_EXT_PHY
 
-
 /*
  * NS16550 Configuration
  */
 
 #define CFG_NS16550
 #define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE       (1)
-#define CFG_NS16550_CLK            (48000000)     /* can be 12M/32Khz or 48Mhz */
-#define CFG_NS16550_COM1           0xfffb0000     /* uart1, bluetooth uart
-                                                   * on perseus */
+#define CFG_NS16550_REG_SIZE	   (1)
+#define CFG_NS16550_CLK		   (48000000)	  /* can be 12M/32Khz or 48Mhz */
+#define CFG_NS16550_COM1	   0xfffb0000	  /* uart1, bluetooth uart
+						   * on perseus */
 
 /*
  * select serial console configuration
  */
 
-#define CONFIG_SERIAL1             1         /* we use SERIAL 1 on OMAP730 Perseus 2 */
+#define CONFIG_SERIAL1		   1	     /* we use SERIAL 1 on OMAP730 Perseus 2 */
 
+#define CONFIG_CONS_INDEX	   1
+#define CONFIG_BAUDRATE		   115200
+#define CFG_BAUDRATE_TABLE	   { 9600, 19200, 38400, 57600, 115200 }
 
-#define CONFIG_CONS_INDEX          1
-#define CONFIG_BAUDRATE            115200
-#define CFG_BAUDRATE_TABLE         { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_COMMANDS		   (CONFIG_CMD_DFL | CFG_CMD_DHCP)
+#define CONFIG_BOOTP_MASK	   CONFIG_BOOTP_DEFAULT
 
-#define CONFIG_COMMANDS            (CONFIG_CMD_DFL | CFG_CMD_DHCP)
-#define CONFIG_BOOTP_MASK          CONFIG_BOOTP_DEFAULT
-
-/* 
- * This must be included AFTER the definition of CONFIG_COMMANDS (if any) 
+/*
+ * This must be included AFTER the definition of CONFIG_COMMANDS (if any)
  */
 
 #include <cmd_confdefs.h>
 #include <configs/omap730.h>
 #include <configs/h2_p2_dbg_board.h>
 
-#define CONFIG_BOOTDELAY           3
-#define CONFIG_BOOTARGS            "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw ip=bootp"
+#define CONFIG_BOOTDELAY	   3
+#define CONFIG_BOOTARGS		   "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw ip=bootp"
 
-#define CONFIG_LOADADDR            0x10000000
+#define CONFIG_LOADADDR		   0x10000000
 
 #define CONFIG_ETHADDR
-#define CONFIG_NETMASK             255.255.255.0
-#define CONFIG_IPADDR              192.168.0.23
-#define CONFIG_SERVERIP            192.150.0.100
-#define CONFIG_BOOTFILE            "uImage"  /* File to load */
+#define CONFIG_NETMASK		   255.255.255.0
+#define CONFIG_IPADDR		   192.168.0.23
+#define CONFIG_SERVERIP		   192.150.0.100
+#define CONFIG_BOOTFILE		   "uImage"  /* File to load */
 
 #if defined (CONFIG_COMMANDS) && defined (CFG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE       115200    /* Speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX      1         /* Which serial port to use */
+#define CONFIG_KGDB_BAUDRATE	   115200    /* Speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	   1	     /* Which serial port to use */
 #endif
 
-
 /*
  * Miscellaneous configurable options
  */
 
-#define CFG_LONGHELP                                   /* undef to save memory     */
-#define CFG_PROMPT                 "OMAP730 P2 # "     /* Monitor Command Prompt   */
-#define CFG_CBSIZE                 256                 /* Console I/O Buffer Size  */
+#define CFG_LONGHELP				       /* undef to save memory	   */
+#define CFG_PROMPT		   "OMAP730 P2 # "     /* Monitor Command Prompt   */
+#define CFG_CBSIZE		   256		       /* Console I/O Buffer Size  */
 /* Print Buffer Size */
-#define CFG_PBSIZE                 (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
-#define CFG_MAXARGS                16                  /* max number of command args   */
-#define CFG_BARGSIZE               CFG_CBSIZE          /* Boot Argument Buffer Size    */
-
-#define CFG_MEMTEST_START          0x10000000          /* memtest works on */
-#define CFG_MEMTEST_END            0x12000000          /* 32 MB in DRAM    */
+#define CFG_PBSIZE		   (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS		   16		       /* max number of command args   */
+#define CFG_BARGSIZE		   CFG_CBSIZE	       /* Boot Argument Buffer Size    */
 
-#undef CFG_CLKS_IN_HZ                /* everything, incl board info, in Hz */
+#define CFG_MEMTEST_START	   0x10000000	       /* memtest works on */
+#define CFG_MEMTEST_END		   0x12000000	       /* 32 MB in DRAM	   */
 
-#define CFG_LOAD_ADDR              0x10000000          /* default load address */
+#undef CFG_CLKS_IN_HZ		     /* everything, incl board info, in Hz */
 
+#define CFG_LOAD_ADDR		   0x10000000	       /* default load address */
 
-/* The OMAP730 has 3 general purpose MPU timers, they can be driven by 
- * the RefClk (12Mhz) or by DPLL1. This time is further subdivided by a 
+/* The OMAP730 has 3 general purpose MPU timers, they can be driven by
+ * the RefClk (12Mhz) or by DPLL1. This time is further subdivided by a
  * local divisor.
  */
 
-#define CFG_TIMERBASE              0xFFFEC500          /* use timer 1 */
-#define CFG_PVT                    7                   /* 2^(pvt+1), divide by 256 */
-#define CFG_HZ                     ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
-
+#define CFG_TIMERBASE		   0xFFFEC500	       /* use timer 1 */
+#define CFG_PVT			   7		       /* 2^(pvt+1), divide by 256 */
+#define CFG_HZ			   ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
 
 /*-----------------------------------------------------------------------
  * Stack sizes
@@ -169,52 +158,46 @@
  * The stack sizes are set up in start.S using the settings below
  */
 
-#define CONFIG_STACKSIZE           (128*1024)     /* regular stack */
+#define CONFIG_STACKSIZE	   (128*1024)	  /* regular stack */
 #ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ       (4*1024)       /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ       (4*1024)       /* FIQ stack */
+#define CONFIG_STACKSIZE_IRQ	   (4*1024)	  /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	   (4*1024)	  /* FIQ stack */
 #endif
 
-
 /*-----------------------------------------------------------------------
  * Physical Memory Map
  */
 
-#define CONFIG_NR_DRAM_BANKS       1              /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1               0x10000000     /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE          0x02000000     /* 32 MB */
+#define CONFIG_NR_DRAM_BANKS	   1		  /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		   0x10000000	  /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	   0x02000000	  /* 32 MB */
 
 #if defined(CONFIG_CS0_BOOT)
-#define PHYS_FLASH_1               0x0C000000
+#define PHYS_FLASH_1		   0x0C000000
 #elif defined(CONFIG_CS3_BOOT)
-#define PHYS_FLASH_1               0x00000000
+#define PHYS_FLASH_1		   0x00000000
 #else
 #error Unknown Boot Chip-Select number
 #endif
 
-#define CFG_FLASH_BASE             PHYS_FLASH_1
-
-
+#define CFG_FLASH_BASE		   PHYS_FLASH_1
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
 
-#define CFG_MAX_FLASH_BANKS        1              /* max number of memory banks */
-#define PHYS_FLASH_SIZE            0x02000000     /* 32MB */
-#define CFG_MAX_FLASH_SECT         (259)          /* max number of sectors on one chip */
+#define CFG_MAX_FLASH_BANKS	   1		  /* max number of memory banks */
+#define PHYS_FLASH_SIZE		   0x02000000	  /* 32MB */
+#define CFG_MAX_FLASH_SECT	   (259)	  /* max number of sectors on one chip */
 /* addr of environment */
-#define CFG_ENV_ADDR               (CFG_FLASH_BASE + 0x020000)
-
+#define CFG_ENV_ADDR		   (CFG_FLASH_BASE + 0x020000)
 
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT        (20*CFG_HZ)   /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT        (20*CFG_HZ)   /* Timeout for Flash Write */
-
-#define CFG_ENV_IS_IN_FLASH        1
-#define CFG_ENV_SIZE               0x20000        /* Total Size of Environment Sector */
-#define CFG_ENV_OFFSET             0x20000        /* environment starts here  */
-
+#define CFG_FLASH_ERASE_TOUT	    (20*CFG_HZ)	  /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	    (20*CFG_HZ)	  /* Timeout for Flash Write */
 
+#define CFG_ENV_IS_IN_FLASH	   1
+#define CFG_ENV_SIZE		   0x20000	  /* Total Size of Environment Sector */
+#define CFG_ENV_OFFSET		   0x20000	  /* environment starts here  */
 
-#endif    /* ! __CONFIG_H */
+#endif	  /* ! __CONFIG_H */
diff --git a/include/flash.h b/include/flash.h
index 5221907..5576eb3 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -42,9 +42,9 @@ typedef struct {
 	ulong	erase_blk_tout;		/* maximum block erase timeout		*/
 	ulong	write_tout;		/* maximum write timeout		*/
 	ulong	buffer_write_tout;	/* maximum buffer write timeout		*/
-	ushort  vendor;                 /* the primary vendor id                */
-	ushort  cmd_reset;              /* Vendor specific reset command        */
-	ushort  interface;              /* used for x8/x16 adjustments          */
+	ushort	vendor;			/* the primary vendor id		*/
+	ushort	cmd_reset;		/* Vendor specific reset command	*/
+	ushort	interface;		/* used for x8/x16 adjustments		*/
 #endif
 } flash_info_t;
 
@@ -63,7 +63,7 @@ typedef struct {
 #define FLASH_CFI_BY32		0x04
 #define FLASH_CFI_BY64		0x08
 /* convert between bit value and numeric value */
-#define CFI_FLASH_SHIFT_WIDTH      3
+#define CFI_FLASH_SHIFT_WIDTH	3
 /*
  * Values for the flash device interface
  */
@@ -72,7 +72,7 @@ typedef struct {
 #define FLASH_CFI_X8X16		0x02
 
 /* convert between bit value and numeric value */
-#define CFI_FLASH_SHIFT_WIDTH      3
+#define CFI_FLASH_SHIFT_WIDTH	3
 /* Prototypes */
 
 extern unsigned long flash_init (void);
@@ -127,6 +127,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
 #define INTEL_ALT_MANU	0x00B000B0	/* alternate INTEL namufacturer ID	*/
 #define MX_MANUFACT	0x00C200C2	/* MXIC	   manuf. ID in D23..D16, D7..D0 */
 #define TOSH_MANUFACT	0x00980098	/* TOSHIBA manuf. ID in D23..D16, D7..D0 */
+#define MT2_MANUFACT	0x002C002C	/* alternate MICRON manufacturer ID*/
 
 					/* Micron Technologies (INTEL compat.)	*/
 #define MT_ID_28F400_T	0x44704470	/* 28F400B3 ID ( 4 M, top boot sector)	*/
@@ -241,6 +242,9 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
 #define INTEL_ID_28F640J3A  0x00170017	/*  64M = 128K x  64	*/
 #define INTEL_ID_28F128J3A  0x00180018	/* 128M = 128K x 128	*/
 #define INTEL_ID_28F256L18T 0x880D880D	/* 256M = 128K x 255 + 32k x 4 */
+#define INTEL_ID_28F256K3 0x88038803          /* 256M = 128K x 255 + 32k x 4 */
+#define INTEL_ID_28F128K3 0x88028802          /* 128M = 64K x 255 + 32k x 4 */
+#define INTEL_ID_28F64K3  0x88018801          /*  64M = 32K x 255 + 32k x 4 */
 
 #define INTEL_ID_28F160S3   0x00D000D0	/*  16M = 512K x  32 (64kB x 32)	*/
 #define INTEL_ID_28F320S3   0x00D400D4	/*  32M = 512K x  64 (64kB x 64)	*/
@@ -354,6 +358,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
 #define FLASH_MXLV320T	0x00AC		/* MX  29LV320MT   ( 32M = 2M x 16 )	*/
 /* Intel 28F256L18T 256M = 128K x 255 + 32k x 4	*/
 #define FLASH_28F256L18T 0x00B0
+#define FLASH_28F256K3	0x00A8
 #define FLASH_AMDL163T	0x00B2		/* AMD AM29DL163T (2M x 16 )			*/
 #define FLASH_AMDL163B	0x00B3