Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx

26 files changed, 2038 insertions, 3715 deletions

diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h
new file mode 100644
index 0000000..83931f1
--- /dev/null
+++ b/include/asm-ppc/ppc4xx-sdram.h
@@ -0,0 +1,1156 @@
+/*
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PPC4xx_SDRAM_H_
+#define _PPC4xx_SDRAM_H_
+
+#if defined(CONFIG_SDRAM_PPC4xx_IBM_SDRAM)
+
+/*
+ * SDRAM Controller
+ */
+/*
+ * XXX - ToDo: Revisit file to change all these lower case defines into
+ * upper case. Also needs to be done in the controller setup code too
+ * of course. sr, 2008-06-02
+ */
+#ifndef CONFIG_405EP
+#define mem_besra	0x00	/* bus error syndrome reg a		*/
+#define mem_besrsa	0x04	/* bus error syndrome reg set a		*/
+#define mem_besrb	0x08	/* bus error syndrome reg b		*/
+#define mem_besrsb	0x0c	/* bus error syndrome reg set b		*/
+#define mem_bear	0x10	/* bus error address reg		*/
+#endif
+#define mem_mcopt1	0x20	/* memory controller options 1		*/
+#define mem_status	0x24	/* memory status			*/
+#define mem_rtr		0x30	/* refresh timer reg			*/
+#define mem_pmit	0x34	/* power management idle timer		*/
+#define mem_mb0cf	0x40	/* memory bank 0 configuration		*/
+#define mem_mb1cf	0x44	/* memory bank 1 configuration		*/
+#ifndef CONFIG_405EP
+#define mem_mb2cf	0x48	/* memory bank 2 configuration		*/
+#define mem_mb3cf	0x4c	/* memory bank 3 configuration		*/
+#endif
+#define mem_sdtr1	0x80	/* timing reg 1				*/
+#ifndef CONFIG_405EP
+#define mem_ecccf	0x94	/* ECC configuration			*/
+#define mem_eccerr	0x98	/* ECC error status			*/
+#endif
+
+#endif /* CONFIG_SDRAM_PPC4xx_IBM_SDRAM */
+
+#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
+
+/*
+ * Memory controller registers
+ */
+#define SDRAM_CFG0	0x20	/* memory controller options 0		*/
+#define SDRAM_CFG1	0x21	/* memory controller options 1		*/
+
+/*
+ * XXX - ToDo: Revisit file to change all these lower case defines into
+ * upper case. Also needs to be done in the controller setup code too
+ * of course. sr, 2008-06-02
+ */
+#define mem_besr0_clr	0x0000	/* bus error status reg 0 (clr)		*/
+#define mem_besr0_set	0x0004	/* bus error status reg 0 (set)		*/
+#define mem_besr1_clr	0x0008	/* bus error status reg 1 (clr)		*/
+#define mem_besr1_set	0x000c	/* bus error status reg 1 (set)		*/
+#define mem_bear	0x0010	/* bus error address reg		*/
+#define mem_mirq_clr	0x0011	/* bus master interrupt (clr)		*/
+#define mem_mirq_set	0x0012	/* bus master interrupt (set)		*/
+#define mem_slio	0x0018	/* ddr sdram slave interface options	*/
+#define mem_cfg0	0x0020	/* ddr sdram options 0			*/
+#define mem_cfg1	0x0021	/* ddr sdram options 1			*/
+#define mem_devopt	0x0022	/* ddr sdram device options		*/
+#define mem_mcsts	0x0024	/* memory controller status		*/
+#define mem_rtr		0x0030	/* refresh timer register		*/
+#define mem_pmit	0x0034	/* power management idle timer		*/
+#define mem_uabba	0x0038	/* plb UABus base address		*/
+#define mem_b0cr	0x0040	/* ddr sdram bank 0 configuration	*/
+#define mem_b1cr	0x0044	/* ddr sdram bank 1 configuration	*/
+#define mem_b2cr	0x0048	/* ddr sdram bank 2 configuration	*/
+#define mem_b3cr	0x004c	/* ddr sdram bank 3 configuration	*/
+#define mem_tr0		0x0080	/* sdram timing register 0		*/
+#define mem_tr1		0x0081	/* sdram timing register 1		*/
+#define mem_clktr	0x0082	/* ddr clock timing register		*/
+#define mem_wddctr	0x0083	/* write data/dm/dqs clock timing reg	*/
+#define mem_dlycal	0x0084	/* delay line calibration register	*/
+#define mem_eccesr	0x0098	/* ECC error status			*/
+
+/*
+ * Memory Controller Options 0
+ */
+#define SDRAM_CFG0_DCEN		0x80000000	/* SDRAM Controller Enable	*/
+#define SDRAM_CFG0_MCHK_MASK	0x30000000	/* Memory data errchecking mask */
+#define SDRAM_CFG0_MCHK_NON	0x00000000	/* No ECC generation		*/
+#define SDRAM_CFG0_MCHK_GEN	0x20000000	/* ECC generation		*/
+#define SDRAM_CFG0_MCHK_CHK	0x30000000	/* ECC generation and checking	*/
+#define SDRAM_CFG0_RDEN		0x08000000	/* Registered DIMM enable	*/
+#define SDRAM_CFG0_PMUD		0x04000000	/* Page management unit		*/
+#define SDRAM_CFG0_DMWD_MASK	0x02000000	/* DRAM width mask		*/
+#define SDRAM_CFG0_DMWD_32	0x00000000	/* 32 bits			*/
+#define SDRAM_CFG0_DMWD_64	0x02000000	/* 64 bits			*/
+#define SDRAM_CFG0_UIOS_MASK	0x00C00000	/* Unused IO State		*/
+#define SDRAM_CFG0_PDP		0x00200000	/* Page deallocation policy	*/
+
+/*
+ * Memory Controller Options 1
+ */
+#define SDRAM_CFG1_SRE		0x80000000	/* Self-Refresh Entry		*/
+#define SDRAM_CFG1_PMEN		0x40000000	/* Power Management Enable	*/
+
+/*
+ * SDRAM DEVPOT Options
+ */
+#define SDRAM_DEVOPT_DLL	0x80000000
+#define SDRAM_DEVOPT_DS		0x40000000
+
+/*
+ * SDRAM MCSTS Options
+ */
+#define SDRAM_MCSTS_MRSC	0x80000000
+#define SDRAM_MCSTS_SRMS	0x40000000
+#define SDRAM_MCSTS_CIS		0x20000000
+
+/*
+ * SDRAM Refresh Timer Register
+ */
+#define SDRAM_RTR_RINT_MASK	  0xFFFF0000
+#define SDRAM_RTR_RINT_ENCODE(n)  (((n) << 16) & SDRAM_RTR_RINT_MASK)
+
+/*
+ * SDRAM UABus Base Address Reg
+ */
+#define SDRAM_UABBA_UBBA_MASK	0x0000000F
+
+/*
+ * Memory Bank 0-7 configuration
+ */
+#define SDRAM_BXCR_SDBA_MASK	0xff800000	  /* Base address	      */
+#define SDRAM_BXCR_SDSZ_MASK	0x000e0000	  /* Size		      */
+#define SDRAM_BXCR_SDSZ_8	0x00020000	  /*   8M		      */
+#define SDRAM_BXCR_SDSZ_16	0x00040000	  /*  16M		      */
+#define SDRAM_BXCR_SDSZ_32	0x00060000	  /*  32M		      */
+#define SDRAM_BXCR_SDSZ_64	0x00080000	  /*  64M		      */
+#define SDRAM_BXCR_SDSZ_128	0x000a0000	  /* 128M		      */
+#define SDRAM_BXCR_SDSZ_256	0x000c0000	  /* 256M		      */
+#define SDRAM_BXCR_SDSZ_512	0x000e0000	  /* 512M		      */
+#define SDRAM_BXCR_SDAM_MASK	0x0000e000	  /* Addressing mode	      */
+#define SDRAM_BXCR_SDAM_1	0x00000000	  /*   Mode 1		      */
+#define SDRAM_BXCR_SDAM_2	0x00002000	  /*   Mode 2		      */
+#define SDRAM_BXCR_SDAM_3	0x00004000	  /*   Mode 3		      */
+#define SDRAM_BXCR_SDAM_4	0x00006000	  /*   Mode 4		      */
+#define SDRAM_BXCR_SDBE		0x00000001	  /* Memory Bank Enable	      */
+
+/*
+ * SDRAM TR0 Options
+ */
+#define SDRAM_TR0_SDWR_MASK	0x80000000
+#define	 SDRAM_TR0_SDWR_2_CLK	0x00000000
+#define	 SDRAM_TR0_SDWR_3_CLK	0x80000000
+#define SDRAM_TR0_SDWD_MASK	0x40000000
+#define	 SDRAM_TR0_SDWD_0_CLK	0x00000000
+#define	 SDRAM_TR0_SDWD_1_CLK	0x40000000
+#define SDRAM_TR0_SDCL_MASK	0x01800000
+#define	 SDRAM_TR0_SDCL_2_0_CLK 0x00800000
+#define	 SDRAM_TR0_SDCL_2_5_CLK 0x01000000
+#define	 SDRAM_TR0_SDCL_3_0_CLK 0x01800000
+#define SDRAM_TR0_SDPA_MASK	0x000C0000
+#define	 SDRAM_TR0_SDPA_2_CLK	0x00040000
+#define	 SDRAM_TR0_SDPA_3_CLK	0x00080000
+#define	 SDRAM_TR0_SDPA_4_CLK	0x000C0000
+#define SDRAM_TR0_SDCP_MASK	0x00030000
+#define	 SDRAM_TR0_SDCP_2_CLK	0x00000000
+#define	 SDRAM_TR0_SDCP_3_CLK	0x00010000
+#define	 SDRAM_TR0_SDCP_4_CLK	0x00020000
+#define	 SDRAM_TR0_SDCP_5_CLK	0x00030000
+#define SDRAM_TR0_SDLD_MASK	0x0000C000
+#define	 SDRAM_TR0_SDLD_1_CLK	0x00000000
+#define	 SDRAM_TR0_SDLD_2_CLK	0x00004000
+#define SDRAM_TR0_SDRA_MASK	0x0000001C
+#define	 SDRAM_TR0_SDRA_6_CLK	0x00000000
+#define	 SDRAM_TR0_SDRA_7_CLK	0x00000004
+#define	 SDRAM_TR0_SDRA_8_CLK	0x00000008
+#define	 SDRAM_TR0_SDRA_9_CLK	0x0000000C
+#define	 SDRAM_TR0_SDRA_10_CLK	0x00000010
+#define	 SDRAM_TR0_SDRA_11_CLK	0x00000014
+#define	 SDRAM_TR0_SDRA_12_CLK	0x00000018
+#define	 SDRAM_TR0_SDRA_13_CLK	0x0000001C
+#define SDRAM_TR0_SDRD_MASK	0x00000003
+#define	 SDRAM_TR0_SDRD_2_CLK	0x00000001
+#define	 SDRAM_TR0_SDRD_3_CLK	0x00000002
+#define	 SDRAM_TR0_SDRD_4_CLK	0x00000003
+
+/*
+ * SDRAM TR1 Options
+ */
+#define SDRAM_TR1_RDSS_MASK	0xC0000000
+#define	 SDRAM_TR1_RDSS_TR0	0x00000000
+#define	 SDRAM_TR1_RDSS_TR1	0x40000000
+#define	 SDRAM_TR1_RDSS_TR2	0x80000000
+#define	 SDRAM_TR1_RDSS_TR3	0xC0000000
+#define SDRAM_TR1_RDSL_MASK	0x00C00000
+#define	 SDRAM_TR1_RDSL_STAGE1	0x00000000
+#define	 SDRAM_TR1_RDSL_STAGE2	0x00400000
+#define	 SDRAM_TR1_RDSL_STAGE3	0x00800000
+#define SDRAM_TR1_RDCD_MASK	0x00000800
+#define	 SDRAM_TR1_RDCD_RCD_0_0 0x00000000
+#define	 SDRAM_TR1_RDCD_RCD_1_2 0x00000800
+#define SDRAM_TR1_RDCT_MASK	0x000001FF
+#define	 SDRAM_TR1_RDCT_ENCODE(x)  (((x) << 0) & SDRAM_TR1_RDCT_MASK)
+#define	 SDRAM_TR1_RDCT_DECODE(x)  (((x) & SDRAM_TR1_RDCT_MASK) >> 0)
+#define	 SDRAM_TR1_RDCT_MIN	0x00000000
+#define	 SDRAM_TR1_RDCT_MAX	0x000001FF
+
+/*
+ * SDRAM WDDCTR Options
+ */
+#define SDRAM_WDDCTR_WRCP_MASK	0xC0000000
+#define	 SDRAM_WDDCTR_WRCP_0DEG	  0x00000000
+#define	 SDRAM_WDDCTR_WRCP_90DEG  0x40000000
+#define	 SDRAM_WDDCTR_WRCP_180DEG 0x80000000
+#define SDRAM_WDDCTR_DCD_MASK	0x000001FF
+
+/*
+ * SDRAM CLKTR Options
+ */
+#define SDRAM_CLKTR_CLKP_MASK	0xC0000000
+#define	 SDRAM_CLKTR_CLKP_0DEG	  0x00000000
+#define	 SDRAM_CLKTR_CLKP_90DEG	  0x40000000
+#define	 SDRAM_CLKTR_CLKP_180DEG  0x80000000
+#define SDRAM_CLKTR_DCDT_MASK	0x000001FF
+
+/*
+ * SDRAM DLYCAL Options
+ */
+#define SDRAM_DLYCAL_DLCV_MASK	0x000003FC
+#define	 SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
+#define	 SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
+
+#endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR */
+
+#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
+
+#define SDRAM_DLYCAL_DLCV_MASK		0x000003FC
+#define SDRAM_DLYCAL_DLCV_ENCODE(x)	(((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
+#define SDRAM_DLYCAL_DLCV_DECODE(x)	(((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
+
+/*
+ * Memory queue defines
+ */
+#define SDRAMQ_DCR_BASE	0x040
+
+#define SDRAM_R0BAS	(SDRAMQ_DCR_BASE+0x0)	/* rank 0 base address & size  */
+#define SDRAM_R1BAS	(SDRAMQ_DCR_BASE+0x1)	/* rank 1 base address & size  */
+#define SDRAM_R2BAS	(SDRAMQ_DCR_BASE+0x2)	/* rank 2 base address & size  */
+#define SDRAM_R3BAS	(SDRAMQ_DCR_BASE+0x3)	/* rank 3 base address & size  */
+#define SDRAM_CONF1HB	(SDRAMQ_DCR_BASE+0x5)	/* configuration 1 HB          */
+#define SDRAM_ERRSTATHB	(SDRAMQ_DCR_BASE+0x7)	/* error status HB             */
+#define SDRAM_ERRADDUHB	(SDRAMQ_DCR_BASE+0x8)	/* error address upper 32 HB   */
+#define SDRAM_ERRADDLHB	(SDRAMQ_DCR_BASE+0x9)	/* error address lower 32 HB   */
+#define SDRAM_PLBADDULL	(SDRAMQ_DCR_BASE+0xA)	/* PLB base address upper 32 LL */
+#define SDRAM_CONF1LL	(SDRAMQ_DCR_BASE+0xB)	/* configuration 1 LL          */
+#define SDRAM_ERRSTATLL	(SDRAMQ_DCR_BASE+0xC)	/* error status LL             */
+#define SDRAM_ERRADDULL	(SDRAMQ_DCR_BASE+0xD)	/* error address upper 32 LL   */
+#define SDRAM_ERRADDLLL	(SDRAMQ_DCR_BASE+0xE)	/* error address lower 32 LL   */
+#define SDRAM_CONFPATHB	(SDRAMQ_DCR_BASE+0xF)	/* configuration between paths */
+#define SDRAM_PLBADDUHB	(SDRAMQ_DCR_BASE+0x10)	/* PLB base address upper 32 LL */
+
+#if !defined(CONFIG_405EX)
+/*
+ * Memory Bank 0-7 configuration
+ */
+#if defined(CONFIG_440SPE) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define SDRAM_RXBAS_SDBA_MASK		0xFFE00000	/* Base address	*/
+#define SDRAM_RXBAS_SDBA_ENCODE(n)	((((u32)(n))&0xFFE00000)>>2)
+#define SDRAM_RXBAS_SDBA_DECODE(n)	((((u32)(n))&0xFFE00000)<<2)
+#endif /* CONFIG_440SPE */
+#if defined(CONFIG_440SP)
+#define SDRAM_RXBAS_SDBA_MASK		0xFF800000	/* Base address	*/
+#define SDRAM_RXBAS_SDBA_ENCODE(n)	((((u32)(n))&0xFF800000))
+#define SDRAM_RXBAS_SDBA_DECODE(n)	((((u32)(n))&0xFF800000))
+#endif /* CONFIG_440SP */
+#define SDRAM_RXBAS_SDSZ_MASK		0x0000FFC0	/* Size		*/
+#define SDRAM_RXBAS_SDSZ_ENCODE(n)	((((u32)(n))&0x3FF)<<6)
+#define SDRAM_RXBAS_SDSZ_DECODE(n)	((((u32)(n))>>6)&0x3FF)
+#define SDRAM_RXBAS_SDSZ_0		0x00000000	/*   0M		*/
+#define SDRAM_RXBAS_SDSZ_8		0x0000FFC0	/*   8M		*/
+#define SDRAM_RXBAS_SDSZ_16		0x0000FF80	/*  16M		*/
+#define SDRAM_RXBAS_SDSZ_32		0x0000FF00	/*  32M		*/
+#define SDRAM_RXBAS_SDSZ_64		0x0000FE00	/*  64M		*/
+#define SDRAM_RXBAS_SDSZ_128		0x0000FC00	/* 128M		*/
+#define SDRAM_RXBAS_SDSZ_256		0x0000F800	/* 256M		*/
+#define SDRAM_RXBAS_SDSZ_512		0x0000F000	/* 512M		*/
+#define SDRAM_RXBAS_SDSZ_1024		0x0000E000	/* 1024M	*/
+#define SDRAM_RXBAS_SDSZ_2048		0x0000C000	/* 2048M	*/
+#define SDRAM_RXBAS_SDSZ_4096		0x00008000	/* 4096M	*/
+#else /* CONFIG_405EX */
+/*
+ * XXX - ToDo:
+ * Revisit this file to check if all these 405EX defines are correct and
+ * can be used in the common 44x_spd_ddr2 code as well. sr, 2008-06-02
+ */
+#define SDRAM_RXBAS_SDSZ_MASK		PPC_REG_VAL(19, 0xF)
+#define SDRAM_RXBAS_SDSZ_4MB	   	PPC_REG_VAL(19, 0x0)
+#define SDRAM_RXBAS_SDSZ_8MB	   	PPC_REG_VAL(19, 0x1)
+#define SDRAM_RXBAS_SDSZ_16MB	   	PPC_REG_VAL(19, 0x2)
+#define SDRAM_RXBAS_SDSZ_32MB	   	PPC_REG_VAL(19, 0x3)
+#define SDRAM_RXBAS_SDSZ_64MB	   	PPC_REG_VAL(19, 0x4)
+#define SDRAM_RXBAS_SDSZ_128MB	   	PPC_REG_VAL(19, 0x5)
+#define SDRAM_RXBAS_SDSZ_256MB	   	PPC_REG_VAL(19, 0x6)
+#define SDRAM_RXBAS_SDSZ_512MB	   	PPC_REG_VAL(19, 0x7)
+#define SDRAM_RXBAS_SDSZ_1024MB	   	PPC_REG_VAL(19, 0x8)
+#define SDRAM_RXBAS_SDSZ_2048MB	   	PPC_REG_VAL(19, 0x9)
+#define SDRAM_RXBAS_SDSZ_4096MB		PPC_REG_VAL(19, 0xA)
+#define SDRAM_RXBAS_SDSZ_8192MB		PPC_REG_VAL(19, 0xB)
+#define SDRAM_RXBAS_SDSZ_8      	SDRAM_RXBAS_SDSZ_8MB
+#define SDRAM_RXBAS_SDSZ_16     	SDRAM_RXBAS_SDSZ_16MB
+#define SDRAM_RXBAS_SDSZ_32     	SDRAM_RXBAS_SDSZ_32MB
+#define SDRAM_RXBAS_SDSZ_64     	SDRAM_RXBAS_SDSZ_64MB
+#define SDRAM_RXBAS_SDSZ_128    	SDRAM_RXBAS_SDSZ_128MB
+#define SDRAM_RXBAS_SDSZ_256    	SDRAM_RXBAS_SDSZ_256MB
+#define SDRAM_RXBAS_SDSZ_512    	SDRAM_RXBAS_SDSZ_512MB
+#define SDRAM_RXBAS_SDSZ_1024		SDRAM_RXBAS_SDSZ_1024MB
+#define SDRAM_RXBAS_SDSZ_2048		SDRAM_RXBAS_SDSZ_2048MB
+#define SDRAM_RXBAS_SDSZ_4096		SDRAM_RXBAS_SDSZ_4096MB
+#define SDRAM_RXBAS_SDSZ_8192		SDRAM_RXBAS_SDSZ_8192MB
+#define SDRAM_RXBAS_SDAM_MODE0		PPC_REG_VAL(23, 0x0)
+#define SDRAM_RXBAS_SDAM_MODE1		PPC_REG_VAL(23, 0x1)
+#define SDRAM_RXBAS_SDAM_MODE2		PPC_REG_VAL(23, 0x2)
+#define SDRAM_RXBAS_SDAM_MODE3		PPC_REG_VAL(23, 0x3)
+#define SDRAM_RXBAS_SDAM_MODE4		PPC_REG_VAL(23, 0x4)
+#define SDRAM_RXBAS_SDAM_MODE5		PPC_REG_VAL(23, 0x5)
+#define SDRAM_RXBAS_SDAM_MODE6		PPC_REG_VAL(23, 0x6)
+#define SDRAM_RXBAS_SDAM_MODE7		PPC_REG_VAL(23, 0x7)
+#define SDRAM_RXBAS_SDAM_MODE8		PPC_REG_VAL(23, 0x8)
+#define SDRAM_RXBAS_SDAM_MODE9		PPC_REG_VAL(23, 0x9)
+#define SDRAM_RXBAS_SDBE_DISABLE	PPC_REG_VAL(31, 0x0)
+#define SDRAM_RXBAS_SDBE_ENABLE		PPC_REG_VAL(31, 0x1)
+#endif /* CONFIG_405EX */
+
+/*
+ * Memory controller registers
+ */
+#define SDRAM_MCSTAT	0x14	/* memory controller status                  */
+#define SDRAM_MCOPT1	0x20	/* memory controller options 1               */
+#define SDRAM_MCOPT2	0x21	/* memory controller options 2               */
+#define SDRAM_MODT0	0x22	/* on die termination for bank 0             */
+#define SDRAM_MODT1	0x23	/* on die termination for bank 1             */
+#define SDRAM_MODT2	0x24	/* on die termination for bank 2             */
+#define SDRAM_MODT3	0x25	/* on die termination for bank 3             */
+#define SDRAM_CODT	0x26	/* on die termination for controller         */
+#define SDRAM_VVPR	0x27	/* variable VRef programmming                */
+#define SDRAM_OPARS	0x28	/* on chip driver control setup              */
+#define SDRAM_OPART	0x29	/* on chip driver control trigger            */
+#define SDRAM_RTR	0x30	/* refresh timer                             */
+#define SDRAM_PMIT	0x34	/* power management idle timer               */
+#define SDRAM_MB0CF	0x40	/* memory bank 0 configuration               */
+#define SDRAM_MB1CF	0x44	/* memory bank 1 configuration               */
+#define SDRAM_MB2CF	0x48
+#define SDRAM_MB3CF	0x4C
+#define SDRAM_INITPLR0	0x50	/* manual initialization control             */
+#define SDRAM_INITPLR1	0x51	/* manual initialization control             */
+#define SDRAM_INITPLR2	0x52	/* manual initialization control             */
+#define SDRAM_INITPLR3	0x53	/* manual initialization control             */
+#define SDRAM_INITPLR4	0x54	/* manual initialization control             */
+#define SDRAM_INITPLR5	0x55	/* manual initialization control             */
+#define SDRAM_INITPLR6	0x56	/* manual initialization control             */
+#define SDRAM_INITPLR7	0x57	/* manual initialization control             */
+#define SDRAM_INITPLR8	0x58	/* manual initialization control             */
+#define SDRAM_INITPLR9	0x59	/* manual initialization control             */
+#define SDRAM_INITPLR10	0x5a	/* manual initialization control             */
+#define SDRAM_INITPLR11	0x5b	/* manual initialization control             */
+#define SDRAM_INITPLR12	0x5c	/* manual initialization control             */
+#define SDRAM_INITPLR13	0x5d	/* manual initialization control             */
+#define SDRAM_INITPLR14	0x5e	/* manual initialization control             */
+#define SDRAM_INITPLR15	0x5f	/* manual initialization control             */
+#define SDRAM_RQDC	0x70	/* read DQS delay control                    */
+#define SDRAM_RFDC	0x74	/* read feedback delay control               */
+#define SDRAM_RDCC	0x78	/* read data capture control                 */
+#define SDRAM_DLCR	0x7A	/* delay line calibration                    */
+#define SDRAM_CLKTR	0x80	/* DDR clock timing                          */
+#define SDRAM_WRDTR	0x81	/* write data, DQS, DM clock, timing         */
+#define SDRAM_SDTR1	0x85	/* DDR SDRAM timing 1                        */
+#define SDRAM_SDTR2	0x86	/* DDR SDRAM timing 2                        */
+#define SDRAM_SDTR3	0x87	/* DDR SDRAM timing 3                        */
+#define SDRAM_MMODE	0x88	/* memory mode                               */
+#define SDRAM_MEMODE	0x89	/* memory extended mode                      */
+#define SDRAM_ECCCR	0x98	/* ECC error status                          */
+#define SDRAM_CID	0xA4	/* core ID                                   */
+#define SDRAM_RID	0xA8	/* revision ID                               */
+#define SDRAM_RTSR	0xB1	/* run time status tracking                  */
+
+/*
+ * Memory Controller Status
+ */
+#define SDRAM_MCSTAT_MIC_MASK		0x80000000	/* Memory init status mask	*/
+#define SDRAM_MCSTAT_MIC_NOTCOMP	0x00000000	/* Mem init not complete	*/
+#define SDRAM_MCSTAT_MIC_COMP		0x80000000	/* Mem init complete		*/
+#define SDRAM_MCSTAT_SRMS_MASK		0x40000000	/* Mem self refresh stat mask	*/
+#define SDRAM_MCSTAT_SRMS_NOT_SF	0x00000000	/* Mem not in self refresh	*/
+#define SDRAM_MCSTAT_SRMS_SF		0x40000000	/* Mem in self refresh		*/
+#define SDRAM_MCSTAT_IDLE_MASK		0x20000000	/* Mem self refresh stat mask	*/
+#define SDRAM_MCSTAT_IDLE_NOT		0x00000000	/* Mem contr not idle		*/
+#define SDRAM_MCSTAT_IDLE		0x20000000	/* Mem contr idle		*/
+
+/*
+ * Memory Controller Options 1
+ */
+#define SDRAM_MCOPT1_MCHK_MASK		0x30000000 /* Memory data err check mask*/
+#define SDRAM_MCOPT1_MCHK_NON		0x00000000 /* No ECC generation		*/
+#define SDRAM_MCOPT1_MCHK_GEN		0x20000000 /* ECC generation		*/
+#define SDRAM_MCOPT1_MCHK_CHK		0x10000000 /* ECC generation and check	*/
+#define SDRAM_MCOPT1_MCHK_CHK_REP	0x30000000 /* ECC generation, chk, report*/
+#define SDRAM_MCOPT1_MCHK_CHK_DECODE(n)	((((u32)(n))>>28)&0x3)
+#define SDRAM_MCOPT1_RDEN_MASK		0x08000000 /* Registered DIMM mask	*/
+#define SDRAM_MCOPT1_RDEN		0x08000000 /* Registered DIMM enable	*/
+#define SDRAM_MCOPT1_PMU_MASK		0x06000000 /* Page management unit mask	*/
+#define SDRAM_MCOPT1_PMU_CLOSE		0x00000000 /* PMU Close			*/
+#define SDRAM_MCOPT1_PMU_OPEN		0x04000000 /* PMU Open			*/
+#define SDRAM_MCOPT1_PMU_AUTOCLOSE	0x02000000 /* PMU AutoClose		*/
+#define SDRAM_MCOPT1_DMWD_MASK		0x01000000 /* DRAM width mask		*/
+#define SDRAM_MCOPT1_DMWD_32		0x00000000 /* 32 bits			*/
+#define SDRAM_MCOPT1_DMWD_64		0x01000000 /* 64 bits			*/
+#define SDRAM_MCOPT1_UIOS_MASK		0x00C00000 /* Unused IO State		*/
+#define SDRAM_MCOPT1_BCNT_MASK		0x00200000 /* Bank count		*/
+#define SDRAM_MCOPT1_4_BANKS		0x00000000 /* 4 Banks			*/
+#define SDRAM_MCOPT1_8_BANKS		0x00200000 /* 8 Banks			*/
+#define SDRAM_MCOPT1_DDR_TYPE_MASK	0x00100000 /* DDR Memory Type mask	*/
+#define SDRAM_MCOPT1_DDR1_TYPE		0x00000000 /* DDR1 Memory Type		*/
+#define SDRAM_MCOPT1_DDR2_TYPE		0x00100000 /* DDR2 Memory Type		*/
+#define SDRAM_MCOPT1_QDEP		0x00020000 /* 4 commands deep		*/
+#define SDRAM_MCOPT1_RWOO_MASK		0x00008000 /* Out of Order Read mask	*/
+#define SDRAM_MCOPT1_RWOO_DISABLED	0x00000000 /* disabled			*/
+#define SDRAM_MCOPT1_RWOO_ENABLED	0x00008000 /* enabled			*/
+#define SDRAM_MCOPT1_WOOO_MASK		0x00004000 /* Out of Order Write mask	*/
+#define SDRAM_MCOPT1_WOOO_DISABLED	0x00000000 /* disabled			*/
+#define SDRAM_MCOPT1_WOOO_ENABLED	0x00004000 /* enabled			*/
+#define SDRAM_MCOPT1_DCOO_MASK		0x00002000 /* All Out of Order mask	*/
+#define SDRAM_MCOPT1_DCOO_DISABLED	0x00002000 /* disabled			*/
+#define SDRAM_MCOPT1_DCOO_ENABLED	0x00000000 /* enabled			*/
+#define SDRAM_MCOPT1_DREF_MASK		0x00001000 /* Deferred refresh mask	*/
+#define SDRAM_MCOPT1_DREF_NORMAL	0x00000000 /* normal refresh		*/
+#define SDRAM_MCOPT1_DREF_DEFER_4	0x00001000 /* defer up to 4 refresh cmd	*/
+
+/*
+ * Memory Controller Options 2
+ */
+#define SDRAM_MCOPT2_SREN_MASK		0x80000000 /* Self Test mask		*/
+#define SDRAM_MCOPT2_SREN_EXIT		0x00000000 /* Self Test exit		*/
+#define SDRAM_MCOPT2_SREN_ENTER		0x80000000 /* Self Test enter		*/
+#define SDRAM_MCOPT2_PMEN_MASK		0x40000000 /* Power Management mask	*/
+#define SDRAM_MCOPT2_PMEN_DISABLE	0x00000000 /* disable			*/
+#define SDRAM_MCOPT2_PMEN_ENABLE	0x40000000 /* enable			*/
+#define SDRAM_MCOPT2_IPTR_MASK		0x20000000 /* Init Trigger Reg mask	*/
+#define SDRAM_MCOPT2_IPTR_IDLE		0x00000000 /* idle			*/
+#define SDRAM_MCOPT2_IPTR_EXECUTE	0x20000000 /* execute preloaded init	*/
+#define SDRAM_MCOPT2_XSRP_MASK		0x10000000 /* Exit Self Refresh Prevent	*/
+#define SDRAM_MCOPT2_XSRP_ALLOW		0x00000000 /* allow self refresh exit	*/
+#define SDRAM_MCOPT2_XSRP_PREVENT	0x10000000 /* prevent self refresh exit	*/
+#define SDRAM_MCOPT2_DCEN_MASK		0x08000000 /* SDRAM Controller Enable	*/
+#define SDRAM_MCOPT2_DCEN_DISABLE	0x00000000 /* SDRAM Controller Enable	*/
+#define SDRAM_MCOPT2_DCEN_ENABLE	0x08000000 /* SDRAM Controller Enable	*/
+#define SDRAM_MCOPT2_ISIE_MASK		0x04000000 /* Init Seq Interruptable mas*/
+#define SDRAM_MCOPT2_ISIE_DISABLE	0x00000000 /* disable			*/
+#define SDRAM_MCOPT2_ISIE_ENABLE	0x04000000 /* enable			*/
+
+/*
+ * SDRAM Refresh Timer Register
+ */
+#define SDRAM_RTR_RINT_MASK		0xFFF80000
+#define SDRAM_RTR_RINT_ENCODE(n)	((((u32)(n))&0xFFF8)<<16)
+#define SDRAM_RTR_RINT_DECODE(n)	((((u32)(n))>>16)&0xFFF8)
+
+/*
+ * SDRAM Read DQS Delay Control Register
+ */
+#define SDRAM_RQDC_RQDE_MASK		0x80000000
+#define SDRAM_RQDC_RQDE_DISABLE		0x00000000
+#define SDRAM_RQDC_RQDE_ENABLE		0x80000000
+#define SDRAM_RQDC_RQFD_MASK		0x000001FF
+#define SDRAM_RQDC_RQFD_ENCODE(n)	((((u32)(n))&0x1FF)<<0)
+
+#define SDRAM_RQDC_RQFD_MAX		0x1FF
+
+/*
+ * SDRAM Read Data Capture Control Register
+ */
+#define SDRAM_RDCC_RDSS_MASK		0xC0000000
+#define SDRAM_RDCC_RDSS_T1		0x00000000
+#define SDRAM_RDCC_RDSS_T2		0x40000000
+#define SDRAM_RDCC_RDSS_T3		0x80000000
+#define SDRAM_RDCC_RDSS_T4		0xC0000000
+#define SDRAM_RDCC_RSAE_MASK		0x00000001
+#define SDRAM_RDCC_RSAE_DISABLE		0x00000001
+#define SDRAM_RDCC_RSAE_ENABLE		0x00000000
+
+/*
+ * SDRAM Read Feedback Delay Control Register
+ */
+#define SDRAM_RFDC_ARSE_MASK		0x80000000
+#define SDRAM_RFDC_ARSE_DISABLE		0x80000000
+#define SDRAM_RFDC_ARSE_ENABLE		0x00000000
+#define SDRAM_RFDC_RFOS_MASK		0x007F0000
+#define SDRAM_RFDC_RFOS_ENCODE(n)	((((u32)(n))&0x7F)<<16)
+#define SDRAM_RFDC_RFFD_MASK		0x000007FF
+#define SDRAM_RFDC_RFFD_ENCODE(n)	((((u32)(n))&0x7FF)<<0)
+
+#define SDRAM_RFDC_RFFD_MAX		0x7FF
+
+/*
+ * SDRAM Delay Line Calibration Register
+ */
+#define SDRAM_DLCR_DCLM_MASK		0x80000000
+#define SDRAM_DLCR_DCLM_MANUEL		0x80000000
+#define SDRAM_DLCR_DCLM_AUTO		0x00000000
+#define SDRAM_DLCR_DLCR_MASK		0x08000000
+#define SDRAM_DLCR_DLCR_CALIBRATE	0x08000000
+#define SDRAM_DLCR_DLCR_IDLE		0x00000000
+#define SDRAM_DLCR_DLCS_MASK		0x07000000
+#define SDRAM_DLCR_DLCS_NOT_RUN		0x00000000
+#define SDRAM_DLCR_DLCS_IN_PROGRESS	0x01000000
+#define SDRAM_DLCR_DLCS_COMPLETE	0x02000000
+#define SDRAM_DLCR_DLCS_CONT_DONE	0x03000000
+#define SDRAM_DLCR_DLCS_ERROR		0x04000000
+#define SDRAM_DLCR_DLCV_MASK		0x000001FF
+#define SDRAM_DLCR_DLCV_ENCODE(n)	((((u32)(n))&0x1FF)<<0)
+#define SDRAM_DLCR_DLCV_DECODE(n)	((((u32)(n))>>0)&0x1FF)
+
+/*
+ * SDRAM Controller On Die Termination Register
+ */
+#define SDRAM_CODT_ODT_ON			0x80000000
+#define SDRAM_CODT_ODT_OFF			0x00000000
+#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK		0x00000020
+#define SDRAM_CODT_DQS_2_5_V_DDR1		0x00000000
+#define SDRAM_CODT_DQS_1_8_V_DDR2		0x00000020
+#define SDRAM_CODT_DQS_MASK			0x00000010
+#define SDRAM_CODT_DQS_DIFFERENTIAL		0x00000000
+#define SDRAM_CODT_DQS_SINGLE_END		0x00000010
+#define SDRAM_CODT_CKSE_DIFFERENTIAL		0x00000000
+#define SDRAM_CODT_CKSE_SINGLE_END		0x00000008
+#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END	0x00000004
+#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END	0x00000002
+#define SDRAM_CODT_IO_HIZ			0x00000000
+#define SDRAM_CODT_IO_NMODE			0x00000001
+
+/*
+ * SDRAM Mode Register
+ */
+#define SDRAM_MMODE_WR_MASK		0x00000E00
+#define SDRAM_MMODE_WR_DDR1		0x00000000
+#define SDRAM_MMODE_WR_DDR2_3_CYC	0x00000400
+#define SDRAM_MMODE_WR_DDR2_4_CYC	0x00000600
+#define SDRAM_MMODE_WR_DDR2_5_CYC	0x00000800
+#define SDRAM_MMODE_WR_DDR2_6_CYC	0x00000A00
+#define SDRAM_MMODE_DCL_MASK		0x00000070
+#define SDRAM_MMODE_DCL_DDR1_2_0_CLK	0x00000020
+#define SDRAM_MMODE_DCL_DDR1_2_5_CLK	0x00000060
+#define SDRAM_MMODE_DCL_DDR1_3_0_CLK	0x00000030
+#define SDRAM_MMODE_DCL_DDR2_2_0_CLK	0x00000020
+#define SDRAM_MMODE_DCL_DDR2_3_0_CLK	0x00000030
+#define SDRAM_MMODE_DCL_DDR2_4_0_CLK	0x00000040
+#define SDRAM_MMODE_DCL_DDR2_5_0_CLK	0x00000050
+#define SDRAM_MMODE_DCL_DDR2_6_0_CLK	0x00000060
+#define SDRAM_MMODE_DCL_DDR2_7_0_CLK	0x00000070
+
+/*
+ * SDRAM Extended Mode Register
+ */
+#define SDRAM_MEMODE_DIC_MASK		0x00000002
+#define SDRAM_MEMODE_DIC_NORMAL		0x00000000
+#define SDRAM_MEMODE_DIC_WEAK		0x00000002
+#define SDRAM_MEMODE_DLL_MASK		0x00000001
+#define SDRAM_MEMODE_DLL_DISABLE	0x00000001
+#define SDRAM_MEMODE_DLL_ENABLE		0x00000000
+#define SDRAM_MEMODE_RTT_MASK		0x00000044
+#define SDRAM_MEMODE_RTT_DISABLED	0x00000000
+#define SDRAM_MEMODE_RTT_75OHM		0x00000004
+#define SDRAM_MEMODE_RTT_150OHM		0x00000040
+#define SDRAM_MEMODE_DQS_MASK		0x00000400
+#define SDRAM_MEMODE_DQS_DISABLE	0x00000400
+#define SDRAM_MEMODE_DQS_ENABLE		0x00000000
+
+/*
+ * SDRAM Clock Timing Register
+ */
+#define SDRAM_CLKTR_CLKP_MASK		0xC0000000
+#define SDRAM_CLKTR_CLKP_0_DEG		0x00000000
+#define SDRAM_CLKTR_CLKP_180_DEG_ADV	0x80000000
+#define SDRAM_CLKTR_CLKP_90_DEG_ADV	0x40000000
+#define SDRAM_CLKTR_CLKP_270_DEG_ADV	0xC0000000
+
+/*
+ * SDRAM Write Timing Register
+ */
+#define SDRAM_WRDTR_LLWP_MASK		0x10000000
+#define SDRAM_WRDTR_LLWP_DIS		0x10000000
+#define SDRAM_WRDTR_LLWP_1_CYC		0x00000000
+#define SDRAM_WRDTR_WTR_MASK		0x0E000000
+#define SDRAM_WRDTR_WTR_0_DEG		0x06000000
+#define SDRAM_WRDTR_WTR_90_DEG_ADV	0x04000000
+#define SDRAM_WRDTR_WTR_180_DEG_ADV	0x02000000
+#define SDRAM_WRDTR_WTR_270_DEG_ADV	0x00000000
+
+/*
+ * SDRAM SDTR1 Options
+ */
+#define SDRAM_SDTR1_LDOF_MASK		0x80000000
+#define SDRAM_SDTR1_LDOF_1_CLK		0x00000000
+#define SDRAM_SDTR1_LDOF_2_CLK		0x80000000
+#define SDRAM_SDTR1_RTW_MASK		0x00F00000
+#define SDRAM_SDTR1_RTW_2_CLK		0x00200000
+#define SDRAM_SDTR1_RTW_3_CLK		0x00300000
+#define SDRAM_SDTR1_WTWO_MASK		0x000F0000
+#define SDRAM_SDTR1_WTWO_0_CLK		0x00000000
+#define SDRAM_SDTR1_WTWO_1_CLK		0x00010000
+#define SDRAM_SDTR1_RTRO_MASK		0x0000F000
+#define SDRAM_SDTR1_RTRO_1_CLK		0x00001000
+#define SDRAM_SDTR1_RTRO_2_CLK		0x00002000
+
+/*
+ * SDRAM SDTR2 Options
+ */
+#define SDRAM_SDTR2_RCD_MASK		0xF0000000
+#define SDRAM_SDTR2_RCD_1_CLK		0x10000000
+#define SDRAM_SDTR2_RCD_2_CLK		0x20000000
+#define SDRAM_SDTR2_RCD_3_CLK		0x30000000
+#define SDRAM_SDTR2_RCD_4_CLK		0x40000000
+#define SDRAM_SDTR2_RCD_5_CLK		0x50000000
+#define SDRAM_SDTR2_WTR_MASK		0x0F000000
+#define SDRAM_SDTR2_WTR_1_CLK		0x01000000
+#define SDRAM_SDTR2_WTR_2_CLK		0x02000000
+#define SDRAM_SDTR2_WTR_3_CLK		0x03000000
+#define SDRAM_SDTR2_WTR_4_CLK		0x04000000
+#define SDRAM_SDTR3_WTR_ENCODE(n)	((((u32)(n))&0xF)<<24)
+#define SDRAM_SDTR2_XSNR_MASK		0x00FF0000
+#define SDRAM_SDTR2_XSNR_8_CLK		0x00080000
+#define SDRAM_SDTR2_XSNR_16_CLK		0x00100000
+#define SDRAM_SDTR2_XSNR_32_CLK		0x00200000
+#define SDRAM_SDTR2_XSNR_64_CLK		0x00400000
+#define SDRAM_SDTR2_WPC_MASK		0x0000F000
+#define SDRAM_SDTR2_WPC_2_CLK		0x00002000
+#define SDRAM_SDTR2_WPC_3_CLK		0x00003000
+#define SDRAM_SDTR2_WPC_4_CLK		0x00004000
+#define SDRAM_SDTR2_WPC_5_CLK		0x00005000
+#define SDRAM_SDTR2_WPC_6_CLK		0x00006000
+#define SDRAM_SDTR3_WPC_ENCODE(n)	((((u32)(n))&0xF)<<12)
+#define SDRAM_SDTR2_RPC_MASK		0x00000F00
+#define SDRAM_SDTR2_RPC_2_CLK		0x00000200
+#define SDRAM_SDTR2_RPC_3_CLK		0x00000300
+#define SDRAM_SDTR2_RPC_4_CLK		0x00000400
+#define SDRAM_SDTR2_RP_MASK		0x000000F0
+#define SDRAM_SDTR2_RP_3_CLK		0x00000030
+#define SDRAM_SDTR2_RP_4_CLK		0x00000040
+#define SDRAM_SDTR2_RP_5_CLK		0x00000050
+#define SDRAM_SDTR2_RP_6_CLK		0x00000060
+#define SDRAM_SDTR2_RP_7_CLK		0x00000070
+#define SDRAM_SDTR2_RRD_MASK		0x0000000F
+#define SDRAM_SDTR2_RRD_2_CLK		0x00000002
+#define SDRAM_SDTR2_RRD_3_CLK		0x00000003
+
+/*
+ * SDRAM SDTR3 Options
+ */
+#define SDRAM_SDTR3_RAS_MASK		0x1F000000
+#define SDRAM_SDTR3_RAS_ENCODE(n)	((((u32)(n))&0x1F)<<24)
+#define SDRAM_SDTR3_RC_MASK		0x001F0000
+#define SDRAM_SDTR3_RC_ENCODE(n)	((((u32)(n))&0x1F)<<16)
+#define SDRAM_SDTR3_XCS_MASK		0x00001F00
+#define SDRAM_SDTR3_XCS			0x00000D00
+#define SDRAM_SDTR3_RFC_MASK		0x0000003F
+#define SDRAM_SDTR3_RFC_ENCODE(n)	((((u32)(n))&0x3F)<<0)
+
+/*
+ * Memory Bank 0-1 configuration
+ */
+#define SDRAM_BXCF_M_AM_MASK		0x00000F00	/* Addressing mode	*/
+#define SDRAM_BXCF_M_AM_0		0x00000000	/*   Mode 0		*/
+#define SDRAM_BXCF_M_AM_1		0x00000100	/*   Mode 1		*/
+#define SDRAM_BXCF_M_AM_2		0x00000200	/*   Mode 2		*/
+#define SDRAM_BXCF_M_AM_3		0x00000300	/*   Mode 3		*/
+#define SDRAM_BXCF_M_AM_4		0x00000400	/*   Mode 4		*/
+#define SDRAM_BXCF_M_AM_5		0x00000500	/*   Mode 5		*/
+#define SDRAM_BXCF_M_AM_6		0x00000600	/*   Mode 6		*/
+#define SDRAM_BXCF_M_AM_7		0x00000700	/*   Mode 7		*/
+#define SDRAM_BXCF_M_AM_8		0x00000800	/*   Mode 8		*/
+#define SDRAM_BXCF_M_AM_9		0x00000900	/*   Mode 9		*/
+#define SDRAM_BXCF_M_BE_MASK		0x00000001	/* Memory Bank Enable	*/
+#define SDRAM_BXCF_M_BE_DISABLE		0x00000000	/* Memory Bank Enable	*/
+#define SDRAM_BXCF_M_BE_ENABLE		0x00000001	/* Memory Bank Enable	*/
+
+#define SDRAM_RTSR_TRK1SM_MASK		0xC0000000	/* Tracking State Mach 1*/
+#define SDRAM_RTSR_TRK1SM_ATBASE	0x00000000	/* atbase state		*/
+#define SDRAM_RTSR_TRK1SM_MISSED	0x40000000	/* missed state		*/
+#define SDRAM_RTSR_TRK1SM_ATPLS1	0x80000000	/* atpls1 state		*/
+#define SDRAM_RTSR_TRK1SM_RESET		0xC0000000	/* reset  state		*/
+
+#define SDR0_MFR_FIXD			0x10000000	/* Workaround for PCI/DMA */
+
+#endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR2 */
+
+#if defined(CONFIG_SDRAM_PPC4xx_DENALI_DDR2)
+/*
+ * SDRAM Controller
+ */
+#define DDR0_00				0x00
+#define DDR0_00_INT_ACK_MASK		0x7F000000	/* Write only */
+#define DDR0_00_INT_ACK_ALL		0x7F000000
+#define DDR0_00_INT_ACK_ENCODE(n)	((((u32)(n))&0x7F)<<24)
+#define DDR0_00_INT_ACK_DECODE(n)	((((u32)(n))>>24)&0x7F)
+/* Status */
+#define DDR0_00_INT_STATUS_MASK		0x00FF0000	/* Read only */
+/* Bit0. A single access outside the defined PHYSICAL memory space detected. */
+#define DDR0_00_INT_STATUS_BIT0		0x00010000
+/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */
+#define DDR0_00_INT_STATUS_BIT1		0x00020000
+/* Bit2. Single correctable ECC event detected */
+#define DDR0_00_INT_STATUS_BIT2		0x00040000
+/* Bit3. Multiple correctable ECC events detected. */
+#define DDR0_00_INT_STATUS_BIT3		0x00080000
+/* Bit4. Single uncorrectable ECC event detected. */
+#define DDR0_00_INT_STATUS_BIT4		0x00100000
+/* Bit5. Multiple uncorrectable ECC events detected. */
+#define DDR0_00_INT_STATUS_BIT5		0x00200000
+/* Bit6. DRAM initialization complete. */
+#define DDR0_00_INT_STATUS_BIT6		0x00400000
+/* Bit7. Logical OR of all lower bits. */
+#define DDR0_00_INT_STATUS_BIT7		0x00800000
+
+#define DDR0_00_INT_STATUS_ENCODE(n)	((((u32)(n))&0xFF)<<16)
+#define DDR0_00_INT_STATUS_DECODE(n)	((((u32)(n))>>16)&0xFF)
+#define DDR0_00_DLL_INCREMENT_MASK	0x00007F00
+#define DDR0_00_DLL_INCREMENT_ENCODE(n)	((((u32)(n))&0x7F)<<8)
+#define DDR0_00_DLL_INCREMENT_DECODE(n)	((((u32)(n))>>8)&0x7F)
+#define DDR0_00_DLL_START_POINT_MASK	0x0000007F
+#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((u32)(n))&0x7F)<<0)
+#define DDR0_00_DLL_START_POINT_DECODE(n) ((((u32)(n))>>0)&0x7F)
+
+#define DDR0_01				0x01
+#define DDR0_01_PLB0_DB_CS_LOWER_MASK	0x1F000000
+#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((u32)(n))&0x1F)<<24)
+#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((u32)(n))>>24)&0x1F)
+#define DDR0_01_PLB0_DB_CS_UPPER_MASK	0x001F0000
+#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((u32)(n))&0x1F)<<16)
+#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((u32)(n))>>16)&0x1F)
+#define DDR0_01_OUT_OF_RANGE_TYPE_MASK	0x00000700	/* Read only */
+#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((u32)(n))&0x7)<<8)
+#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((u32)(n))>>8)&0x7)
+#define DDR0_01_INT_MASK_MASK		0x000000FF
+#define DDR0_01_INT_MASK_ENCODE(n)	((((u32)(n))&0xFF)<<0)
+#define DDR0_01_INT_MASK_DECODE(n)	((((u32)(n))>>0)&0xFF)
+#define DDR0_01_INT_MASK_ALL_ON		0x000000FF
+#define DDR0_01_INT_MASK_ALL_OFF	0x00000000
+
+#define DDR0_02				0x02
+#define DDR0_02_MAX_CS_REG_MASK		0x02000000	/* Read only */
+#define DDR0_02_MAX_CS_REG_ENCODE(n)	((((u32)(n))&0x2)<<24)
+#define DDR0_02_MAX_CS_REG_DECODE(n)	((((u32)(n))>>24)&0x2)
+#define DDR0_02_MAX_COL_REG_MASK	0x000F0000	/* Read only */
+#define DDR0_02_MAX_COL_REG_ENCODE(n)	((((u32)(n))&0xF)<<16)
+#define DDR0_02_MAX_COL_REG_DECODE(n)	((((u32)(n))>>16)&0xF)
+#define DDR0_02_MAX_ROW_REG_MASK	0x00000F00	/* Read only */
+#define DDR0_02_MAX_ROW_REG_ENCODE(n)	((((u32)(n))&0xF)<<8)
+#define DDR0_02_MAX_ROW_REG_DECODE(n)	((((u32)(n))>>8)&0xF)
+#define DDR0_02_START_MASK		0x00000001
+#define DDR0_02_START_ENCODE(n)		((((u32)(n))&0x1)<<0)
+#define DDR0_02_START_DECODE(n)		((((u32)(n))>>0)&0x1)
+#define DDR0_02_START_OFF		0x00000000
+#define DDR0_02_START_ON		0x00000001
+
+#define DDR0_03				0x03
+#define DDR0_03_BSTLEN_MASK		0x07000000
+#define DDR0_03_BSTLEN_ENCODE(n)	((((u32)(n))&0x7)<<24)
+#define DDR0_03_BSTLEN_DECODE(n)	((((u32)(n))>>24)&0x7)
+#define DDR0_03_CASLAT_MASK		0x00070000
+#define DDR0_03_CASLAT_ENCODE(n)	((((u32)(n))&0x7)<<16)
+#define DDR0_03_CASLAT_DECODE(n)	((((u32)(n))>>16)&0x7)
+#define DDR0_03_CASLAT_LIN_MASK		0x00000F00
+#define DDR0_03_CASLAT_LIN_ENCODE(n)	((((u32)(n))&0xF)<<8)
+#define DDR0_03_CASLAT_LIN_DECODE(n)	((((u32)(n))>>8)&0xF)
+#define DDR0_03_INITAREF_MASK		0x0000000F
+#define DDR0_03_INITAREF_ENCODE(n)	((((u32)(n))&0xF)<<0)
+#define DDR0_03_INITAREF_DECODE(n)	((((u32)(n))>>0)&0xF)
+
+#define DDR0_04				0x04
+#define DDR0_04_TRC_MASK		0x1F000000
+#define DDR0_04_TRC_ENCODE(n)		((((u32)(n))&0x1F)<<24)
+#define DDR0_04_TRC_DECODE(n)		((((u32)(n))>>24)&0x1F)
+#define DDR0_04_TRRD_MASK		0x00070000
+#define DDR0_04_TRRD_ENCODE(n)		((((u32)(n))&0x7)<<16)
+#define DDR0_04_TRRD_DECODE(n)		((((u32)(n))>>16)&0x7)
+#define DDR0_04_TRTP_MASK		0x00000700
+#define DDR0_04_TRTP_ENCODE(n)		((((u32)(n))&0x7)<<8)
+#define DDR0_04_TRTP_DECODE(n)		((((u32)(n))>>8)&0x7)
+
+#define DDR0_05				0x05
+#define DDR0_05_TMRD_MASK		0x1F000000
+#define DDR0_05_TMRD_ENCODE(n)		((((u32)(n))&0x1F)<<24)
+#define DDR0_05_TMRD_DECODE(n)		((((u32)(n))>>24)&0x1F)
+#define DDR0_05_TEMRS_MASK		0x00070000
+#define DDR0_05_TEMRS_ENCODE(n)		((((u32)(n))&0x7)<<16)
+#define DDR0_05_TEMRS_DECODE(n)		((((u32)(n))>>16)&0x7)
+#define DDR0_05_TRP_MASK		0x00000F00
+#define DDR0_05_TRP_ENCODE(n)		((((u32)(n))&0xF)<<8)
+#define DDR0_05_TRP_DECODE(n)		((((u32)(n))>>8)&0xF)
+#define DDR0_05_TRAS_MIN_MASK		0x000000FF
+#define DDR0_05_TRAS_MIN_ENCODE(n)	((((u32)(n))&0xFF)<<0)
+#define DDR0_05_TRAS_MIN_DECODE(n)	((((u32)(n))>>0)&0xFF)
+
+#define DDR0_06				0x06
+#define DDR0_06_WRITEINTERP_MASK	0x01000000
+#define DDR0_06_WRITEINTERP_ENCODE(n)	((((u32)(n))&0x1)<<24)
+#define DDR0_06_WRITEINTERP_DECODE(n)	((((u32)(n))>>24)&0x1)
+#define DDR0_06_TWTR_MASK		0x00070000
+#define DDR0_06_TWTR_ENCODE(n)		((((u32)(n))&0x7)<<16)
+#define DDR0_06_TWTR_DECODE(n)		((((u32)(n))>>16)&0x7)
+#define DDR0_06_TDLL_MASK		0x0000FF00
+#define DDR0_06_TDLL_ENCODE(n)		((((u32)(n))&0xFF)<<8)
+#define DDR0_06_TDLL_DECODE(n)		((((u32)(n))>>8)&0xFF)
+#define DDR0_06_TRFC_MASK		0x0000007F
+#define DDR0_06_TRFC_ENCODE(n)		((((u32)(n))&0x7F)<<0)
+#define DDR0_06_TRFC_DECODE(n)		((((u32)(n))>>0)&0x7F)
+
+#define DDR0_07				0x07
+#define DDR0_07_NO_CMD_INIT_MASK	0x01000000
+#define DDR0_07_NO_CMD_INIT_ENCODE(n)	((((u32)(n))&0x1)<<24)
+#define DDR0_07_NO_CMD_INIT_DECODE(n)	((((u32)(n))>>24)&0x1)
+#define DDR0_07_TFAW_MASK		0x001F0000
+#define DDR0_07_TFAW_ENCODE(n)		((((u32)(n))&0x1F)<<16)
+#define DDR0_07_TFAW_DECODE(n)		((((u32)(n))>>16)&0x1F)
+#define DDR0_07_AUTO_REFRESH_MODE_MASK	0x00000100
+#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((u32)(n))&0x1)<<8)
+#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((u32)(n))>>8)&0x1)
+#define DDR0_07_AREFRESH_MASK		0x00000001
+#define DDR0_07_AREFRESH_ENCODE(n)	((((u32)(n))&0x1)<<0)
+#define DDR0_07_AREFRESH_DECODE(n)	((((u32)(n))>>0)&0x1)
+
+#define DDR0_08				0x08
+#define DDR0_08_WRLAT_MASK		0x07000000
+#define DDR0_08_WRLAT_ENCODE(n)		((((u32)(n))&0x7)<<24)
+#define DDR0_08_WRLAT_DECODE(n)		((((u32)(n))>>24)&0x7)
+#define DDR0_08_TCPD_MASK		0x00FF0000
+#define DDR0_08_TCPD_ENCODE(n)		((((u32)(n))&0xFF)<<16)
+#define DDR0_08_TCPD_DECODE(n)		((((u32)(n))>>16)&0xFF)
+#define DDR0_08_DQS_N_EN_MASK		0x00000100
+#define DDR0_08_DQS_N_EN_ENCODE(n)	((((u32)(n))&0x1)<<8)
+#define DDR0_08_DQS_N_EN_DECODE(n)	((((u32)(n))>>8)&0x1)
+#define DDR0_08_DDRII_SDRAM_MODE_MASK	0x00000001
+#define DDR0_08_DDRII_ENCODE(n)		((((u32)(n))&0x1)<<0)
+#define DDR0_08_DDRII_DECODE(n)		((((u32)(n))>>0)&0x1)
+
+#define DDR0_09				0x09
+#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000
+#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((u32)(n))&0x1F)<<24)
+#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((u32)(n))>>24)&0x1F)
+#define DDR0_09_RTT_0_MASK		0x00030000
+#define DDR0_09_RTT_0_ENCODE(n)		((((u32)(n))&0x3)<<16)
+#define DDR0_09_RTT_0_DECODE(n)		((((u32)(n))>>16)&0x3)
+#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK  0x00007F00
+#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((u32)(n))&0x7F)<<8)
+#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((u32)(n))>>8)&0x7F)
+#define DDR0_09_WR_DQS_SHIFT_MASK	0x0000007F
+#define DDR0_09_WR_DQS_SHIFT_ENCODE(n)	((((u32)(n))&0x7F)<<0)
+#define DDR0_09_WR_DQS_SHIFT_DECODE(n)	((((u32)(n))>>0)&0x7F)
+
+#define DDR0_10				0x0A
+#define DDR0_10_WRITE_MODEREG_MASK	0x00010000	/* Write only */
+#define DDR0_10_WRITE_MODEREG_ENCODE(n)	((((u32)(n))&0x1)<<16)
+#define DDR0_10_WRITE_MODEREG_DECODE(n)	((((u32)(n))>>16)&0x1)
+#define DDR0_10_CS_MAP_MASK		0x00000300
+#define DDR0_10_CS_MAP_NO_MEM		0x00000000
+#define DDR0_10_CS_MAP_RANK0_INSTALLED	0x00000100
+#define DDR0_10_CS_MAP_RANK1_INSTALLED	0x00000200
+#define DDR0_10_CS_MAP_ENCODE(n)	((((u32)(n))&0x3)<<8)
+#define DDR0_10_CS_MAP_DECODE(n)	((((u32)(n))>>8)&0x3)
+#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK  0x0000001F
+#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((u32)(n))&0x1F)<<0)
+#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((u32)(n))>>0)&0x1F)
+
+#define DDR0_11				0x0B
+#define DDR0_11_SREFRESH_MASK		0x01000000
+#define DDR0_11_SREFRESH_ENCODE(n)	((((u32)(n))&0x1)<<24)
+#define DDR0_11_SREFRESH_DECODE(n)	((((u32)(n))>>24)&0x1F)
+#define DDR0_11_TXSNR_MASK		0x00FF0000
+#define DDR0_11_TXSNR_ENCODE(n)		((((u32)(n))&0xFF)<<16)
+#define DDR0_11_TXSNR_DECODE(n)		((((u32)(n))>>16)&0xFF)
+#define DDR0_11_TXSR_MASK		0x0000FF00
+#define DDR0_11_TXSR_ENCODE(n)		((((u32)(n))&0xFF)<<8)
+#define DDR0_11_TXSR_DECODE(n)		((((u32)(n))>>8)&0xFF)
+
+#define DDR0_12				0x0C
+#define DDR0_12_TCKE_MASK		0x0000007
+#define DDR0_12_TCKE_ENCODE(n)		((((u32)(n))&0x7)<<0)
+#define DDR0_12_TCKE_DECODE(n)		((((u32)(n))>>0)&0x7)
+
+#define DDR0_14				0x0E
+#define DDR0_14_DLL_BYPASS_MODE_MASK	0x01000000
+#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((u32)(n))&0x1)<<24)
+#define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((u32)(n))>>24)&0x1)
+#define DDR0_14_REDUC_MASK		0x00010000
+#define DDR0_14_REDUC_64BITS		0x00000000
+#define DDR0_14_REDUC_32BITS		0x00010000
+#define DDR0_14_REDUC_ENCODE(n)		((((u32)(n))&0x1)<<16)
+#define DDR0_14_REDUC_DECODE(n)		((((u32)(n))>>16)&0x1)
+#define DDR0_14_REG_DIMM_ENABLE_MASK	0x00000100
+#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((u32)(n))&0x1)<<8)
+#define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((u32)(n))>>8)&0x1)
+
+#define DDR0_17				0x11
+#define DDR0_17_DLL_DQS_DELAY_0_MASK	0x7F000000
+#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((u32)(n))&0x7F)<<24)
+#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((u32)(n))>>24)&0x7F)
+#define DDR0_17_DLLLOCKREG_MASK		0x00010000	/* Read only */
+#define DDR0_17_DLLLOCKREG_LOCKED	0x00010000
+#define DDR0_17_DLLLOCKREG_UNLOCKED	0x00000000
+#define DDR0_17_DLLLOCKREG_ENCODE(n)	((((u32)(n))&0x1)<<16)
+#define DDR0_17_DLLLOCKREG_DECODE(n)	((((u32)(n))>>16)&0x1)
+#define DDR0_17_DLL_LOCK_MASK		0x00007F00	/* Read only */
+#define DDR0_17_DLL_LOCK_ENCODE(n)	((((u32)(n))&0x7F)<<8)
+#define DDR0_17_DLL_LOCK_DECODE(n)	((((u32)(n))>>8)&0x7F)
+
+#define DDR0_18				0x12
+#define DDR0_18_DLL_DQS_DELAY_X_MASK	0x7F7F7F7F
+#define DDR0_18_DLL_DQS_DELAY_4_MASK	0x7F000000
+#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((u32)(n))&0x7F)<<24)
+#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((u32)(n))>>24)&0x7F)
+#define DDR0_18_DLL_DQS_DELAY_3_MASK	0x007F0000
+#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((u32)(n))&0x7F)<<16)
+#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((u32)(n))>>16)&0x7F)
+#define DDR0_18_DLL_DQS_DELAY_2_MASK	0x00007F00
+#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((u32)(n))&0x7F)<<8)
+#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((u32)(n))>>8)&0x7F)
+#define DDR0_18_DLL_DQS_DELAY_1_MASK	0x0000007F
+#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((u32)(n))&0x7F)<<0)
+#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((u32)(n))>>0)&0x7F)
+
+#define DDR0_19				0x13
+#define DDR0_19_DLL_DQS_DELAY_X_MASK	0x7F7F7F7F
+#define DDR0_19_DLL_DQS_DELAY_8_MASK	0x7F000000
+#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((u32)(n))&0x7F)<<24)
+#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((u32)(n))>>24)&0x7F)
+#define DDR0_19_DLL_DQS_DELAY_7_MASK	0x007F0000
+#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((u32)(n))&0x7F)<<16)
+#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((u32)(n))>>16)&0x7F)
+#define DDR0_19_DLL_DQS_DELAY_6_MASK	0x00007F00
+#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((u32)(n))&0x7F)<<8)
+#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((u32)(n))>>8)&0x7F)
+#define DDR0_19_DLL_DQS_DELAY_5_MASK	0x0000007F
+#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((u32)(n))&0x7F)<<0)
+#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((u32)(n))>>0)&0x7F)
+
+#define DDR0_20				0x14
+#define DDR0_20_DLL_DQS_BYPASS_3_MASK	0x7F000000
+#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((u32)(n))&0x7F)<<24)
+#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((u32)(n))>>24)&0x7F)
+#define DDR0_20_DLL_DQS_BYPASS_2_MASK	0x007F0000
+#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((u32)(n))&0x7F)<<16)
+#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((u32)(n))>>16)&0x7F)
+#define DDR0_20_DLL_DQS_BYPASS_1_MASK	0x00007F00
+#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((u32)(n))&0x7F)<<8)
+#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((u32)(n))>>8)&0x7F)
+#define DDR0_20_DLL_DQS_BYPASS_0_MASK	0x0000007F
+#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((u32)(n))&0x7F)<<0)
+#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((u32)(n))>>0)&0x7F)
+
+#define DDR0_21				0x15
+#define DDR0_21_DLL_DQS_BYPASS_7_MASK	0x7F000000
+#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((u32)(n))&0x7F)<<24)
+#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((u32)(n))>>24)&0x7F)
+#define DDR0_21_DLL_DQS_BYPASS_6_MASK	0x007F0000
+#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((u32)(n))&0x7F)<<16)
+#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((u32)(n))>>16)&0x7F)
+#define DDR0_21_DLL_DQS_BYPASS_5_MASK	0x00007F00
+#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((u32)(n))&0x7F)<<8)
+#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((u32)(n))>>8)&0x7F)
+#define DDR0_21_DLL_DQS_BYPASS_4_MASK	0x0000007F
+#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((u32)(n))&0x7F)<<0)
+#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((u32)(n))>>0)&0x7F)
+
+#define DDR0_22				0x16
+#define DDR0_22_CTRL_RAW_MASK		0x03000000
+#define DDR0_22_CTRL_RAW_ECC_DISABLE	0x00000000
+#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY	0x01000000
+#define DDR0_22_CTRL_RAW_NO_ECC_RAM	0x02000000
+#define DDR0_22_CTRL_RAW_ECC_ENABLE	0x03000000
+#define DDR0_22_CTRL_RAW_ENCODE(n)	((((u32)(n))&0x3)<<24)
+#define DDR0_22_CTRL_RAW_DECODE(n)	((((u32)(n))>>24)&0x3)
+#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000
+#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((u32)(n))&0x7F)<<16)
+#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((u32)(n))>>16)&0x7F)
+#define DDR0_22_DQS_OUT_SHIFT_MASK	0x00007F00
+#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n)	((((u32)(n))&0x7F)<<8)
+#define DDR0_22_DQS_OUT_SHIFT_DECODE(n)	((((u32)(n))>>8)&0x7F)
+#define DDR0_22_DLL_DQS_BYPASS_8_MASK	0x0000007F
+#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((u32)(n))&0x7F)<<0)
+#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((u32)(n))>>0)&0x7F)
+
+#define DDR0_23				0x17
+#define DDR0_23_ODT_RD_MAP_CS0_MASK	0x03000000
+#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((u32)(n))&0x3)<<24)
+#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((u32)(n))>>24)&0x3)
+#define DDR0_23_ECC_C_SYND_MASK		0x00FF0000	/* Read only */
+#define DDR0_23_ECC_C_SYND_ENCODE(n)	((((u32)(n))&0xFF)<<16)
+#define DDR0_23_ECC_C_SYND_DECODE(n)	((((u32)(n))>>16)&0xFF)
+#define DDR0_23_ECC_U_SYND_MASK		0x0000FF00	/* Read only */
+#define DDR0_23_ECC_U_SYND_ENCODE(n)	((((u32)(n))&0xFF)<<8)
+#define DDR0_23_ECC_U_SYND_DECODE(n)	((((u32)(n))>>8)&0xFF)
+#define DDR0_23_FWC_MASK		0x00000001	/* Write only */
+#define DDR0_23_FWC_ENCODE(n)		((((u32)(n))&0x1)<<0)
+#define DDR0_23_FWC_DECODE(n)		((((u32)(n))>>0)&0x1)
+
+#define DDR0_24				0x18
+#define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000
+#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((u32)(n))&0x3)<<24)
+#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((u32)(n))>>24)&0x3)
+#define DDR0_24_ODT_WR_MAP_CS1_MASK	0x00030000
+#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((u32)(n))&0x3)<<16)
+#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((u32)(n))>>16)&0x3)
+#define DDR0_24_ODT_RD_MAP_CS1_MASK	0x00000300
+#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((u32)(n))&0x3)<<8)
+#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((u32)(n))>>8)&0x3)
+#define DDR0_24_ODT_WR_MAP_CS0_MASK	0x00000003
+#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((u32)(n))&0x3)<<0)
+#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((u32)(n))>>0)&0x3)
+
+#define DDR0_25				0x19
+#define DDR0_25_VERSION_MASK		0xFFFF0000	/* Read only */
+#define DDR0_25_VERSION_ENCODE(n)	((((u32)(n))&0xFFFF)<<16)
+#define DDR0_25_VERSION_DECODE(n)	((((u32)(n))>>16)&0xFFFF)
+#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK  0x000003FF	/* Read only */
+#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((u32)(n))&0x3FF)<<0)
+#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((u32)(n))>>0)&0x3FF)
+
+#define DDR0_26				0x1A
+#define DDR0_26_TRAS_MAX_MASK		0xFFFF0000
+#define DDR0_26_TRAS_MAX_ENCODE(n)	((((u32)(n))&0xFFFF)<<16)
+#define DDR0_26_TRAS_MAX_DECODE(n)	((((u32)(n))>>16)&0xFFFF)
+#define DDR0_26_TREF_MASK		0x00003FFF
+#define DDR0_26_TREF_ENCODE(n)		((((u32)(n))&0x3FFF)<<0)
+#define DDR0_26_TREF_DECODE(n)		((((u32)(n))>>0)&0x3FFF)
+
+#define DDR0_27				0x1B
+#define DDR0_27_EMRS_DATA_MASK		0x3FFF0000
+#define DDR0_27_EMRS_DATA_ENCODE(n)	((((u32)(n))&0x3FFF)<<16)
+#define DDR0_27_EMRS_DATA_DECODE(n)	((((u32)(n))>>16)&0x3FFF)
+#define DDR0_27_TINIT_MASK		0x0000FFFF
+#define DDR0_27_TINIT_ENCODE(n)		((((u32)(n))&0xFFFF)<<0)
+#define DDR0_27_TINIT_DECODE(n)		((((u32)(n))>>0)&0xFFFF)
+
+#define DDR0_28				0x1C
+#define DDR0_28_EMRS3_DATA_MASK		0x3FFF0000
+#define DDR0_28_EMRS3_DATA_ENCODE(n)	((((u32)(n))&0x3FFF)<<16)
+#define DDR0_28_EMRS3_DATA_DECODE(n)	((((u32)(n))>>16)&0x3FFF)
+#define DDR0_28_EMRS2_DATA_MASK		0x00003FFF
+#define DDR0_28_EMRS2_DATA_ENCODE(n)	((((u32)(n))&0x3FFF)<<0)
+#define DDR0_28_EMRS2_DATA_DECODE(n)	((((u32)(n))>>0)&0x3FFF)
+
+#define DDR0_31				0x1F
+#define DDR0_31_XOR_CHECK_BITS_MASK	0x0000FFFF
+#define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((u32)(n))&0xFFFF)<<0)
+#define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((u32)(n))>>0)&0xFFFF)
+
+#define DDR0_32				0x20
+#define DDR0_32_OUT_OF_RANGE_ADDR_MASK	0xFFFFFFFF	/* Read only */
+#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
+#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_33				0x21
+#define DDR0_33_OUT_OF_RANGE_ADDR_MASK	0x00000001	/* Read only */
+#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((u32)(n))&0x1)<<0)
+#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((u32)(n))>>0)&0x1)
+
+#define DDR0_34				0x22
+#define DDR0_34_ECC_U_ADDR_MASK		0xFFFFFFFF	/* Read only */
+#define DDR0_34_ECC_U_ADDR_ENCODE(n)	((((u32)(n))&0xFFFFFFFF)<<0)
+#define DDR0_34_ECC_U_ADDR_DECODE(n)	((((u32)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_35				0x23
+#define DDR0_35_ECC_U_ADDR_MASK		0x00000001	/* Read only */
+#define DDR0_35_ECC_U_ADDR_ENCODE(n)	((((u32)(n))&0x1)<<0)
+#define DDR0_35_ECC_U_ADDR_DECODE(n)	((((u32)(n))>>0)&0x1)
+
+#define DDR0_36				0x24
+#define DDR0_36_ECC_U_DATA_MASK		0xFFFFFFFF	/* Read only */
+#define DDR0_36_ECC_U_DATA_ENCODE(n)	((((u32)(n))&0xFFFFFFFF)<<0)
+#define DDR0_36_ECC_U_DATA_DECODE(n)	((((u32)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_37				0x25
+#define DDR0_37_ECC_U_DATA_MASK		0xFFFFFFFF	/* Read only */
+#define DDR0_37_ECC_U_DATA_ENCODE(n)	((((u32)(n))&0xFFFFFFFF)<<0)
+#define DDR0_37_ECC_U_DATA_DECODE(n)	((((u32)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_38				0x26
+#define DDR0_38_ECC_C_ADDR_MASK		0xFFFFFFFF	/* Read only */
+#define DDR0_38_ECC_C_ADDR_ENCODE(n)	((((u32)(n))&0xFFFFFFFF)<<0)
+#define DDR0_38_ECC_C_ADDR_DECODE(n)	((((u32)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_39				0x27
+#define DDR0_39_ECC_C_ADDR_MASK		0x00000001	/* Read only */
+#define DDR0_39_ECC_C_ADDR_ENCODE(n)	((((u32)(n))&0x1)<<0)
+#define DDR0_39_ECC_C_ADDR_DECODE(n)	((((u32)(n))>>0)&0x1)
+
+#define DDR0_40				0x28
+#define DDR0_40_ECC_C_DATA_MASK		0xFFFFFFFF	/* Read only */
+#define DDR0_40_ECC_C_DATA_ENCODE(n)	((((u32)(n))&0xFFFFFFFF)<<0)
+#define DDR0_40_ECC_C_DATA_DECODE(n)	((((u32)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_41				0x29
+#define DDR0_41_ECC_C_DATA_MASK		0xFFFFFFFF	/* Read only */
+#define DDR0_41_ECC_C_DATA_ENCODE(n)	((((u32)(n))&0xFFFFFFFF)<<0)
+#define DDR0_41_ECC_C_DATA_DECODE(n)	((((u32)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_42				0x2A
+#define DDR0_42_ADDR_PINS_MASK		0x07000000
+#define DDR0_42_ADDR_PINS_ENCODE(n)	((((u32)(n))&0x7)<<24)
+#define DDR0_42_ADDR_PINS_DECODE(n)	((((u32)(n))>>24)&0x7)
+#define DDR0_42_CASLAT_LIN_GATE_MASK	0x0000000F
+#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((u32)(n))&0xF)<<0)
+#define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((u32)(n))>>0)&0xF)
+
+#define DDR0_43				0x2B
+#define DDR0_43_TWR_MASK		0x07000000
+#define DDR0_43_TWR_ENCODE(n)		((((u32)(n))&0x7)<<24)
+#define DDR0_43_TWR_DECODE(n)		((((u32)(n))>>24)&0x7)
+#define DDR0_43_APREBIT_MASK		0x000F0000
+#define DDR0_43_APREBIT_ENCODE(n)	((((u32)(n))&0xF)<<16)
+#define DDR0_43_APREBIT_DECODE(n)	((((u32)(n))>>16)&0xF)
+#define DDR0_43_COLUMN_SIZE_MASK	0x00000700
+#define DDR0_43_COLUMN_SIZE_ENCODE(n)	((((u32)(n))&0x7)<<8)
+#define DDR0_43_COLUMN_SIZE_DECODE(n)	((((u32)(n))>>8)&0x7)
+#define DDR0_43_EIGHT_BANK_MODE_MASK	0x00000001
+#define DDR0_43_EIGHT_BANK_MODE_8_BANKS	0x00000001
+#define DDR0_43_EIGHT_BANK_MODE_4_BANKS	0x00000000
+#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((u32)(n))&0x1)<<0)
+#define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((u32)(n))>>0)&0x1)
+
+#define DDR0_44				0x2C
+#define DDR0_44_TRCD_MASK		0x000000FF
+#define DDR0_44_TRCD_ENCODE(n)		((((u32)(n))&0xFF)<<0)
+#define DDR0_44_TRCD_DECODE(n)		((((u32)(n))>>0)&0xFF)
+
+#endif /* CONFIG_SDRAM_PPC4xx_DENALI_DDR2 */
+
+#endif /* _PPC4xx_SDRAM_H_ */
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 61a0d05..139e686 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -460,17 +460,19 @@
 #define SPRN_PID2	0x27a	/* Process ID Register 2 */
 #define SPRN_MCSR	0x23c	/* Machine Check Syndrome register */
 #define SPRN_MCAR	0x23d	/* Machine Check Address register */
-#ifdef CONFIG_440
 #define MCSR_MCS	0x80000000	/* Machine Check Summary */
 #define MCSR_IB		0x40000000	/* Instruction PLB Error */
+#if defined(CONFIG_440)
 #define MCSR_DRB	0x20000000	/* Data Read PLB Error */
 #define MCSR_DWB	0x10000000	/* Data Write PLB Error */
+#else
+#define MCSR_DB		0x20000000	/* Data PLB Error */
+#endif /* defined(CONFIG_440) */
 #define MCSR_TLBP	0x08000000	/* TLB Parity Error */
 #define MCSR_ICP	0x04000000	/* I-Cache Parity Error */
 #define MCSR_DCSP	0x02000000	/* D-Cache Search Parity Error */
 #define MCSR_DCFP	0x01000000	/* D-Cache Flush Parity Error */
 #define MCSR_IMPE	0x00800000	/* Imprecise Machine Check Exception */
-#endif
 #define ESR_ST		0x00800000	/* Store Operation */
 
 #if defined(CONFIG_MPC86xx)
diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h
index b248639..fd49f56 100644
--- a/include/configs/CPCI4052.h
+++ b/include/configs/CPCI4052.h
@@ -88,32 +88,17 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_BSP
 #define CONFIG_CMD_EEPROM
 
-
-#if 0 /* test-only */
-#define CONFIG_NETCONSOLE
-#define CONFIG_NET_MULTI
-
-#ifdef CONFIG_NET_MULTI
-#define CONFIG_PHY1_ADDR	1	/* PHY address: for NetConsole	*/
-#endif
-#endif
-
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 
 #define CONFIG_SUPPORT_VFAT
 
-#if 0 /* test-only */
-#define CONFIG_AUTO_UPDATE      1       /* autoupdate via compactflash  */
-#endif
-
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
@@ -256,29 +241,6 @@
 
 #define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
-
-/*
- * JFFS2 partitions
- */
-
-/* No command line, one static partition, use whole device */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-
-/* Use first bank for JFFS2, second bank contains U-Boot.
- *
- * Note: fake mtd_id's used, no linux mtd map file.
- */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		"nor0=cpci4052-0"
-#define MTDPARTS_DEFAULT	"mtdparts=cpci4052-0:-(jffs2)"
-*/
-
 #if 0 /* Use NVRAM for environment variables */
 /*-----------------------------------------------------------------------
  * NVRAM organization
diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h
index 1e9597d..55dd629 100644
--- a/include/configs/CPCI405AB.h
+++ b/include/configs/CPCI405AB.h
@@ -88,7 +88,6 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PING
@@ -238,27 +237,6 @@
 
 #define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
-/*
- * JFFS2 partitions
- */
-/* No command line, one static partition */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-
-/* Use first bank for JFFS2, second bank contains U-Boot.
- *
- * Note: fake mtd_id's used, no linux mtd map file.
- */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		"nor0=cpci405ab-0"
-#define MTDPARTS_DEFAULT	"mtdparts=cpci405ab-0:-(jffs2)"
-*/
-
 /*-----------------------------------------------------------------------
  * I2C EEPROM (CAT24WC32) for environment
  */
diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h
index a8029ea..6b585be 100644
--- a/include/configs/CPCI405DT.h
+++ b/include/configs/CPCI405DT.h
@@ -87,23 +87,12 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_BSP
 #define CONFIG_CMD_EEPROM
 
-
-#if 0 /* test-only */
-#define CONFIG_NETCONSOLE
-#define CONFIG_NET_MULTI
-
-#ifdef CONFIG_NET_MULTI
-#define CONFIG_PHY1_ADDR	1	/* PHY address: for NetConsole	*/
-#endif
-#endif
-
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 
@@ -260,27 +249,6 @@
 
 #define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
-/*
- * JFFS2 partitions
- */
-/* No command line, one static partition */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-
-/* Use first bank for JFFS2, second bank contains U-Boot.
- *
- * Note: fake mtd_id's used, no linux mtd map file.
- */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT		"nor0=cpci405dt-0"
-#define MTDPARTS_DEFAULT	"mtdparts=cpci405dt-0:-(jffs2)"
-*/
-
 #if 0 /* Use NVRAM for environment variables */
 /*-----------------------------------------------------------------------
  * NVRAM organization
@@ -416,7 +384,6 @@
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
-
 /*
  * Internal Definitions
  *
diff --git a/include/configs/acadia.h b/include/configs/acadia.h
index bbf726d..9092a7c 100644
--- a/include/configs/acadia.h
+++ b/include/configs/acadia.h
@@ -34,6 +34,13 @@
 #define CONFIG_ACADIA		1		/* Board is Acadia	*/
 #define CONFIG_4xx		1		/* ... PPC4xx family	*/
 #define CONFIG_405EZ		1		/* Specifc 405EZ support*/
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		acadia
+#include "amcc-common.h"
+
 /* Detect Acadia PLL input clock automatically via CPLD bit		*/
 #define CONFIG_SYS_CLK_FREQ    ((in8(CFG_CPLD_BASE + 0) == 0x0c) ? \
 				66666666 : 33333000)
@@ -59,16 +66,11 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE		0x00000000
 #define CFG_FLASH_BASE		0xfe000000
 #define CFG_CPLD_BASE		0x80000000
 #define CFG_NAND_ADDR		0xd0000000
 #define CFG_USB_HOST		0xef603000	/* USB OHCI 1.1 controller	*/
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(0xFFFFFFFF - CFG_MONITOR_BASE + 1)
-#define CFG_MALLOC_LEN		(512 * 1024)/* Reserve 512 kB for malloc()	*/
-
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer
  *----------------------------------------------------------------------*/
@@ -89,12 +91,6 @@
  *----------------------------------------------------------------------*/
 #undef	CFG_EXT_SERIAL_CLOCK			/* external serial clock */
 #define CFG_BASE_BAUD		691200
-#define CONFIG_BAUDRATE		115200
-#define CONFIG_SERIAL_MULTI     1
-
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE	\
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
 
 /*-----------------------------------------------------------------------
  * Environment
@@ -202,10 +198,7 @@
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C		1		/* I2C with hardware support	*/
-#undef	CONFIG_SOFT_I2C				/* I2C bit-banged		*/
 #define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
 
 #define CFG_I2C_MULTI_EEPROMS
 #define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
@@ -222,77 +215,24 @@
 #define CFG_DTT_LOW_TEMP	-30
 #define CFG_DTT_HYSTERESIS	3
 
-#if 0 /* test-only... */
-/*-----------------------------------------------------------------------
- * SPI stuff - Define to include SPI control
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SPI
-#endif
-
 /*-----------------------------------------------------------------------
  * Ethernet
  *----------------------------------------------------------------------*/
-#define CONFIG_MII		1	/* MII PHY management		*/
 #define	CONFIG_PHY_ADDR		0	/* PHY address			*/
-#define CONFIG_NET_MULTI	1
-#define CFG_RX_ETH_BUFFER	16	/* # of rx buffers & descriptors*/
 #define CONFIG_HAS_ETH0		1
 
-#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define xstr(s) str(s)
-#define str(s) #s
-
+/*
+ * Default environment variables
+ */
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"hostname=acadia\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
-		"bootm\0"						\
-	"rootpath=/opt/eldk/ppc_4xx\0"				\
-	"bootfile=acadia/uImage\0"					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_PPC						\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	CONFIG_AMCC_DEF_ENV_NAND_UPD					\
 	"kernel_addr=fff10000\0"					\
 	"ramdisk_addr=fff20000\0"					\
-	"initrd_high=30000000\0"					\
-	"load=tftp 200000 acadia/u-boot.bin\0"				\
-	"update=protect off " xstr(CFG_MONITOR_BASE) " FFFFFFFF;"	\
-		"era " xstr(CFG_MONITOR_BASE) " FFFFFFFF;"		\
-		"cp.b ${fileaddr} " xstr(CFG_MONITOR_BASE) " ${filesize};" \
-		"setenv filesize;saveenv\0"				\
-	"upd=run load update\0"						\
-	"nload=tftp 200000 acadia/u-boot-nand.bin\0"			\
-	"nupdate=nand erase 0 60000;nand write 200000 0 60000;"		\
-		"setenv filesize;saveenv\0"				\
-	"nupd=run nload nupdate\0"					\
 	"kozio=bootm ffc60000\0"					\
 	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_USB_OHCI
 #define CONFIG_USB_STORAGE
@@ -305,35 +245,10 @@
 #define CONFIG_SUPPORT_VFAT
 
 /*
- * BOOTP options
+ * Commands additional to the ones defined in amcc-common.h
  */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DTT
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_USB
 
 /*
@@ -344,43 +259,6 @@
 #undef CONFIG_CMD_IMLS
 #endif
 
-#undef CONFIG_WATCHDOG					/* watchdog disabled		*/
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- *----------------------------------------------------------------------*/
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	        16	/* max number of command args	*/
-#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000 /* memtest works on		*/
-#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR		0x100000  /* default load address	*/
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-
-#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks	*/
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_LOOPW            1       /* enable loopw command         */
-#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
 /*-----------------------------------------------------------------------
  * NAND FLASH
  *----------------------------------------------------------------------*/
@@ -493,21 +371,4 @@
 #define CFG_GPIO1_TSRL		0x00000000
 #define CFG_GPIO1_TSRH		0x00000000
 
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#if defined(CONFIG_CMD_KGDB)
-  #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-  #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/alpr.h b/include/configs/alpr.h
index 3e906c4..fb6feb5 100644
--- a/include/configs/alpr.h
+++ b/include/configs/alpr.h
@@ -33,7 +33,6 @@
 #define CONFIG_4xx		1	    /* ... PPC4xx family	*/
 #define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_pre_init	*/
 #define CONFIG_LAST_STAGE_INIT	1	    /* call last_stage_init()	*/
-#undef	CFG_DRAM_TEST			    /* Disable-takes long time! */
 #define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
 #define CONFIG_4xx_DCACHE		/* Enable i- and d-cache	*/
 
diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h
new file mode 100644
index 0000000..1f27d78
--- /dev/null
+++ b/include/configs/amcc-common.h
@@ -0,0 +1,259 @@
+/*
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Common configuration options for all AMCC boards
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __AMCC_COMMON_H
+#define __AMCC_COMMON_H
+
+#define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
+#define CFG_MONITOR_BASE	TEXT_BASE	/* Start of U-Boot	*/
+#define CFG_MONITOR_LEN		(0xFFFFFFFF - CFG_MONITOR_BASE + 1)
+#define CFG_MALLOC_LEN		(1 << 20)	/* Reserved for malloc	*/
+
+/*
+ * UART
+ */
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SERIAL_MULTI
+#define CFG_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+/*
+ * I2C
+ */
+#define CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * Ethernet/EMAC/PHY
+ */
+#define CONFIG_MII			/* MII PHY management		*/
+#define CONFIG_NET_MULTI
+#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
+#if defined(CONFIG_440)
+#define CFG_RX_ETH_BUFFER	32	/* number of eth rx buffers	*/
+#else
+#define CFG_RX_ETH_BUFFER	16	/* number of eth rx buffers	*/
+#endif
+
+/*
+ * Commands
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#if defined(CONFIG_440)
+#define CONFIG_CMD_CACHE
+#endif
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE /* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000 /* memtest works on		*/
+#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000  /* default load address	*/
+#define CFG_EXTBDINFO			/* To use extended board_into (bd_t) */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+
+#define CONFIG_CMDLINE_EDITING		/* add command line history	*/
+#define CONFIG_AUTO_COMPLETE		/* add autocompletion support	*/
+#define CONFIG_LOOPW			/* enable loopw command         */
+#define CONFIG_MX_CYCLIC		/* enable mdc/mwc commands      */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 	/* include version env variable */
+#define CFG_CONSOLE_INFO_QUIET		/* don't print console @ startup*/
+
+#define CFG_HUSH_PARSER			/* Use the HUSH parser		*/
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#define CONFIG_LOADS_ECHO		/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE		/* allow baudrate change	*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_SUBNETMASK
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Internal Definitions
+ */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port*/
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use	*/
+#endif
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+
+/*
+ * Booting and default environment
+ */
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+/*
+ * Only very few boards have default console not on ttyS0 (like Taishan)
+ */
+#if !defined(CONFIG_USE_TTY)
+#define CONFIG_USE_TTY	ttyS0
+#endif
+
+/*
+ * Only some 4xx PPC's are equipped with an FPU
+ */
+#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define CONFIG_AMCC_DEF_ENV_ROOTPATH	"rootpath=/opt/eldk/ppc_4xxFP\0"
+#else
+#define CONFIG_AMCC_DEF_ENV_ROOTPATH	"rootpath=/opt/eldk/ppc_4xx\0"
+#endif
+
+/*
+ * Only some boards need to extend the bootargs by some additional
+ * parameters (like Makalu)
+ */
+#if !defined(CONFIG_ADDMISC)
+#define CONFIG_ADDMISC	"addmisc=setenv bootargs ${bootargs}\0"
+#endif
+
+#define xstr(s)	str(s)
+#define str(s)	#s
+
+/*
+ * General common environment variables shared on all AMCC eval boards
+ */
+#define CONFIG_AMCC_DEF_ENV						\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs}"				\
+		" console=" xstr(CONFIG_USE_TTY) ",${baudrate}\0"	\
+	CONFIG_ADDMISC							\
+	"initrd_high=30000000\0"					\
+	"kernel_addr_r=400000\0"					\
+	"fdt_addr_r=800000\0"						\
+	"hostname=" xstr(CONFIG_HOSTNAME) "\0"				\
+	"bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0"			\
+	CONFIG_AMCC_DEF_ENV_ROOTPATH
+
+/*
+ * Default environment for arch/powerpc booting
+ * for boards that are ported to arch/powerpc
+ */
+#define CONFIG_AMCC_DEF_ENV_POWERPC					\
+	"flash_self=run ramargs addip addtty addmisc;"			\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
+	"flash_nfs=run nfsargs addip addtty addmisc;"			\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
+		"tftp ${fdt_addr_r} ${fdt_file}; "			\
+		"run nfsargs addip addtty addmisc;"			\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"fdt_file=" xstr(CONFIG_HOSTNAME) "/" xstr(CONFIG_HOSTNAME) ".dtb\0"
+
+/*
+ * Default environment for arch/ppc booting,
+ * for boards that are not ported to arch/powerpc yet
+ */
+#define CONFIG_AMCC_DEF_ENV_PPC						\
+	"flash_self=run ramargs addip addtty addmisc;"			\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"flash_nfs=run nfsargs addip addtty addmisc;"			\
+		"bootm ${kernel_addr}\0"				\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
+		"run nfsargs addip addtty addmisc;"			\
+		"bootm ${kernel_addr_r}\0"
+
+/*
+ * Default environment for arch/ppc booting (old version),
+ * for boards that are ported to arch/ppc and arch/powerpc
+ */
+#define CONFIG_AMCC_DEF_ENV_PPC_OLD					\
+	"flash_self_old=run ramargs addip addtty addmisc;"		\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"flash_nfs_old=run nfsargs addip addtty addmisc;"		\
+		"bootm ${kernel_addr}\0"				\
+	"net_nfs_old=tftp ${kernel_addr_r} ${bootfile};"		\
+		"run nfsargs addip addtty addmisc;"			\
+		"bootm ${kernel_addr_r}\0"
+
+#define CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"load=tftp 200000 " xstr(CONFIG_HOSTNAME) "/u-boot.bin\0"	\
+	"update=protect off " xstr(CFG_MONITOR_BASE) " FFFFFFFF;"	\
+		"era " xstr(CFG_MONITOR_BASE) " FFFFFFFF;"		\
+		"cp.b ${fileaddr} " xstr(CFG_MONITOR_BASE) " ${filesize};" \
+		"setenv filesize;saveenv\0"				\
+	"upd=run load update\0"						\
+
+#define CONFIG_AMCC_DEF_ENV_NAND_UPD					\
+	"nload=tftp 200000 " xstr(CONFIG_HOSTNAME) "/u-boot-nand.bin\0"	\
+	"nupdate=nand erase 0 100000;nand write 200000 0 100000;"	\
+		"setenv filesize;saveenv\0"				\
+	"nupd=run nload nupdate\0"
+
+#endif /* __AMCC_COMMON_H */
diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h
index 2f0df8a..41058f8 100644
--- a/include/configs/bamboo.h
+++ b/include/configs/bamboo.h
@@ -36,6 +36,12 @@
 #define CONFIG_4xx		1	/* ... PPC4xx family	        */
 #define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
 
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		bamboo
+#include "amcc-common.h"
+
 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f	*/
 
 /*
@@ -49,10 +55,6 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN		(384 * 1024)	/* Reserve 384 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_SDRAM_BASE	        0x00000000	    /* _must_ be 0	*/
 #define CFG_FLASH_BASE	        0xfff00000	    /* start of FLASH	*/
 #define CFG_PCI_MEMBASE	        0xa0000000	    /* mapped pci memory*/
 #define CFG_PCI_MEMBASE1        CFG_PCI_MEMBASE  + 0x10000000
@@ -84,14 +86,9 @@
  * Serial Port
  *----------------------------------------------------------------------*/
 #define CFG_EXT_SERIAL_CLOCK	11059200 /* use external 11.059MHz clk	*/
-#define CONFIG_BAUDRATE		115200
-#define CONFIG_SERIAL_MULTI     1
 /* define this if you want console on UART1 */
 #undef CONFIG_UART1_CONSOLE
 
-#define CFG_BAUDRATE_TABLE  \
-    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
 /*-----------------------------------------------------------------------
  * NVRAM/RTC
  *
@@ -223,15 +220,11 @@
 #define SPD_EEPROM_ADDRESS	{CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51}
 #define CFG_MBYTES_SDRAM	(64)	/* 64MB fixed size for early-sdram-init */
 #define CONFIG_PROG_SDRAM_TLB
-#undef  CFG_DRAM_TEST
 
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C		1	    /* I2C with hardware support	*/
-#undef	CONFIG_SOFT_I2C			    /* I2C bit-banged		*/
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
 
 #define CFG_I2C_MULTI_EEPROMS
 #define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
@@ -245,54 +238,20 @@
 #define CFG_ENV_OFFSET		0x0
 #endif /* CFG_ENV_IS_IN_EEPROM */
 
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
+/*
+ * Default environment variables
+ */
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"hostname=bamboo\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
-	        "bootm\0"						\
-	"rootpath=/opt/eldk/ppc_4xx\0"					\
-	"bootfile=/tftpboot/bamboo/uImage\0"				\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	CONFIG_AMCC_DEF_ENV_NAND_UPD					\
 	"kernel_addr=fff00000\0"					\
 	"ramdisk_addr=fff10000\0"					\
-	"initrd_high=30000000\0"					\
-	"load=tftp 100000 /tftpboot/bamboo/u-boot.bin\0"		\
-	"update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;"	\
-		"cp.b 100000 fffa0000 60000;"			        \
-		"setenv filesize;saveenv\0"				\
-	"upd=run load update\0"						\
 	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define CONFIG_BAUDRATE		115200
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_HAS_ETH0
-#define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address, See schematics	*/
 #define CONFIG_PHY1_ADDR        1
 
@@ -300,16 +259,6 @@
 #define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
 #endif /* CONFIG_BAMBOO_NAND */
 
-#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
-#define CONFIG_NET_MULTI        1       /* required for netconsole      */
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-
 #ifdef CONFIG_440EP
 /* USB */
 #define CONFIG_USB_OHCI
@@ -319,77 +268,27 @@
 #define USB_2_0_DEVICE
 #endif /*CONFIG_440EP*/
 
-
 /*
- * BOOTP options
+ * Commands additional to the ones defined in amcc-common.h
  */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_SNTP
+#define CONFIG_CMD_USB
 
 #ifdef CONFIG_BAMBOO_NAND
 #define CONFIG_CMD_NAND
 #endif
 
-
 #define CONFIG_SUPPORT_VFAT
 
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	        16	/* max number of command args	*/
-#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000 /* memtest works on	        */
-#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-#define CONFIG_LYNXKDI          1       /* support kdi files            */
-
-#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_LOOPW            1       /* enable loopw command         */
-#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -408,28 +307,4 @@
 #define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
 #define CFG_PCI_SUBSYS_ID       0xcafe	/* Whatever */
 
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h
index 75dd4e7..acce82f 100644
--- a/include/configs/bubinga.h
+++ b/include/configs/bubinga.h
@@ -37,6 +37,12 @@
 #define CONFIG_4xx		1	/* ...member of PPC4xx family   */
 #define CONFIG_BUBINGA	        1	/* ...on a BUBINGA board	*/
 
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		bubinga
+#include "amcc-common.h"
+
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
 
 #define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
@@ -80,118 +86,35 @@
 #define CFG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
 #endif
 
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
+/*
+ * Default environment variables
+ */
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"hostname=bubinga\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
-	        "bootm\0"						\
-	"rootpath=/opt/eldk/ppc_4xx\0"					\
-	"bootfile=/tftpboot/bubinga/uImage\0"				\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_PPC						\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
 	"kernel_addr=fff80000\0"					\
 	"ramdisk_addr=fff90000\0"					\
-	"initrd_high=30000000\0"					\
-	"load=tftp 100000 /tftpboot/bubinga/u-boot.bin\0"		\
-	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
-		"cp.b 100000 fffc0000 40000;"			        \
-		"setenv filesize;saveenv\0"				\
-	"upd=run load update\0"						\
 	""
-#define CONFIG_BOOTCOMMAND	"run net_nfs"
-
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define CONFIG_BAUDRATE		115200
 
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII		1	/* MII PHY management		*/
 #define	CONFIG_PHY_ADDR		1	/* PHY address			*/
 #define CONFIG_HAS_ETH0
 #define CONFIG_HAS_ETH1
 #define CONFIG_PHY1_ADDR	2	/* EMAC1 PHY address		*/
-#define CONFIG_NET_MULTI	1
-#define CFG_RX_ETH_BUFFER	16	/* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
 
 #define CONFIG_RTC_DS174x	1	/* use DS1743 RTC in Bubinga	*/
 
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
 /*
- * Command line configuration.
+ * Commands additional to the ones defined in amcc-common.h
  */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_SNTP
 
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
 #define CONFIG_SPD_EEPROM      1       /* use SPD EEPROM for setup    */
 
 /*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-/*
  * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
  * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
  * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
@@ -205,29 +128,11 @@
 #undef  CFG_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
 #define CFG_BASE_BAUD       691200
 
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE  \
-    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_LOOPW            1       /* enable loopw command         */
-#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-
 /*-----------------------------------------------------------------------
  * I2C stuff
  *-----------------------------------------------------------------------
  */
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
-#undef  CONFIG_SOFT_I2C			/* I2C bit-banged		*/
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
 
 #define CFG_I2C_NOPROBES	{ 0x69 }	/* avoid iprobe hangup (why?) */
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	6	/* 24C02 requires 5ms delay */
@@ -272,21 +177,9 @@
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
 #define CFG_SRAM_BASE		0xFFF00000
 #define CFG_FLASH_BASE		0xFFF80000
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
-#define CFG_MONITOR_BASE	(-CFG_MONITOR_LEN)
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
@@ -423,21 +316,4 @@
 #define FPGA_REG1_OFFB_FLASH  0x02       /* Off board flash                   */
 #define FPGA_REG1_SRAM_BOOT   0x01       /* SRAM at 0xFFF80000 not Flash      */
 
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
index 3dd577a..ac2e5d9 100644
--- a/include/configs/canyonlands.h
+++ b/include/configs/canyonlands.h
@@ -30,12 +30,19 @@
 /* This config file is used for Canyonlands (460EX) and Glacier (460GT)	*/
 #ifndef CONFIG_CANYONLANDS
 #define CONFIG_460GT		1	/* Specific PPC460GT		*/
+#define CONFIG_HOSTNAME		glacier
 #else
 #define CONFIG_460EX		1	/* Specific PPC460EX		*/
+#define CONFIG_HOSTNAME		canyonlands
 #endif
 #define CONFIG_440		1
 #define CONFIG_4xx		1	/* ... PPC4xx family */
 
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#include "amcc-common.h"
+
 #define CONFIG_SYS_CLK_FREQ	66666667	/* external freq to pll	*/
 
 #define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_early_init_f */
@@ -47,8 +54,6 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0	*/
-
 #define CFG_PCI_MEMBASE		0x80000000	/* mapped PCI memory	*/
 #define CFG_PCI_BASE		0xd0000000	/* internal PCI regs	*/
 #define CFG_PCI_TARGBASE	CFG_PCI_MEMBASE
@@ -86,10 +91,6 @@
 
 #define CFG_AHB_BASE		0xE2000000	/* internal AHB peripherals	*/
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(384 * 1024)	/* Reserve 384 kB for Monitor */
-#define CFG_MALLOC_LEN		(512 * 1024)	/* Reserve 512 kB for malloc()*/
-
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in OCM)
  *----------------------------------------------------------------------*/
@@ -102,13 +103,8 @@
 /*-----------------------------------------------------------------------
  * Serial Port
  *----------------------------------------------------------------------*/
-#define CONFIG_BAUDRATE		115200
-#define CONFIG_SERIAL_MULTI	1
 #undef CONFIG_UART1_CONSOLE	/* define this if you want console on UART1 */
 
-#define CFG_BAUDRATE_TABLE  \
-    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
 /*-----------------------------------------------------------------------
  * Environment
  *----------------------------------------------------------------------*/
@@ -242,10 +238,7 @@
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C		1	    /* I2C with hardware support	*/
-#undef	CONFIG_SOFT_I2C			    /* I2C bit-banged		*/
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_SPEED		400000	/* I2C speed			*/
 
 #define CFG_I2C_MULTI_EEPROMS
 #define CFG_I2C_EEPROM_ADDR		(0xa8>>1)
@@ -270,7 +263,6 @@
  * Ethernet
  *----------------------------------------------------------------------*/
 #define CONFIG_IBM_EMAC4_V4	1
-#define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address, See schematics	*/
 #define CONFIG_PHY1_ADDR	1
 #define CONFIG_HAS_ETH0
@@ -282,14 +274,11 @@
 #define CONFIG_HAS_ETH2
 #define CONFIG_HAS_ETH3
 #endif
-#define CONFIG_NET_MULTI	1
 
 #define CONFIG_PHY_RESET	1	/* reset phy upon startup	*/
 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
 #define CONFIG_PHY_DYNAMIC_ANEG	1
 
-#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
-
 /*-----------------------------------------------------------------------
  * USB-OHCI
  *----------------------------------------------------------------------*/
@@ -305,104 +294,30 @@
 #define CFG_USB_OHCI_MAX_ROOT_PORTS 15
 #endif
 
-/*-----------------------------------------------------------------------
- * Default environment
- *----------------------------------------------------------------------*/
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-/* Setup some board specific values for the default environment variables */
-#ifdef CONFIG_CANYONLANDS
-#define CONFIG_HOSTNAME		canyonlands
-#define CFG_BOOTFILE		"bootfile=canyonlands/uImage\0"
-#define CFG_DTBFILE		"fdt_file=canyonlands/canyonlands.dtb\0"
-#define CFG_ROOTPATH		"rootpath=/opt/eldk/ppc_4xxFP\0"
-#else
-#define CONFIG_HOSTNAME		glacier
-#define CFG_BOOTFILE		"bootfile=glacier/uImage\0"
-#define CFG_DTBFILE		"fdt_file=glacier/glacier.dtb\0"
-#define CFG_ROOTPATH		"rootpath=/opt/eldk/ppc_4xx\0"
-#endif
-
+/*
+ * Default environment variables
+ */
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
-	CFG_BOOTFILE							\
-	CFG_DTBFILE							\
-	CFG_ROOTPATH							\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
-	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
-		"tftp ${fdt_addr_r} ${fdt_file}; "			\
-		"run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
-	"kernel_addr_r=400000\0"					\
-	"fdt_addr_r=800000\0"						\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	CONFIG_AMCC_DEF_ENV_NAND_UPD					\
 	"kernel_addr=fc000000\0"					\
 	"fdt_addr=fc1e0000\0"						\
 	"ramdisk_addr=fc200000\0"					\
-	"initrd_high=30000000\0"					\
-	"load=tftp 200000 ${hostname}/u-boot.bin\0"			\
-	"update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;"	\
-		"cp.b ${fileaddr} fffa0000 ${filesize};"		\
-		"setenv filesize;saveenv\0"				\
-	"upd=run load update\0"						\
-	"nload=tftp 200000 ${hostname}/u-boot-nand.bin\0"		\
-	"nupdate=nand erase 0 100000;nand write 200000 0 100000;"	\
-		"setenv filesize;saveenv\0"				\
-	"nupd=run nload nupdate\0"					\
 	"pciconfighost=1\0"						\
 	"pcie_mode=RP:RP\0"						\
 	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE		/* allow baudrate change	*/
 
 /*
- * BOOTP options
+ * Commands additional to the ones defined in amcc-common.h
  */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_SUBNETMASK
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DTT
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
 #ifdef CONFIG_460EX
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
@@ -415,41 +330,6 @@
 #define CONFIG_ISO_PARTITION
 
 /*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- *----------------------------------------------------------------------*/
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE /* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000 /* memtest works on		*/
-#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR		0x100000  /* default load address	*/
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_AUTO_COMPLETE	1	/* add autocompletion support	*/
-#define CONFIG_LOOPW		1	/* enable loopw command         */
-#define CONFIG_MX_CYCLIC	1	/* enable mdc/mwc commands      */
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
-
-#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
-#endif
-
-/*-----------------------------------------------------------------------
  * PCI stuff
  *----------------------------------------------------------------------*/
 /* General PCI */
@@ -465,21 +345,6 @@
 #define CFG_PCI_SUBSYS_VENDORID 0x1014	/* IBM				*/
 #define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever			*/
 
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*
- * Internal Definitions
- */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  *----------------------------------------------------------------------*/
@@ -671,8 +536,4 @@
 }
 #endif
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/ebony.h b/include/configs/ebony.h
index ba68fd4..df444d8 100644
--- a/include/configs/ebony.h
+++ b/include/configs/ebony.h
@@ -35,10 +35,15 @@
 #define CONFIG_440		1	    /* ... PPC440 family	*/
 #define CONFIG_4xx		1	    /* ... PPC4xx family	*/
 #define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
-#undef	CFG_DRAM_TEST			    /* Disable-takes long time! */
 #define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
 
 /*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		ebony
+#include "amcc-common.h"
+
+/*
  * Define here the location of the environment variables (FLASH or NVRAM).
  * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
  *       supported for backward compatibility.
@@ -55,7 +60,6 @@
  *----------------------------------------------------------------------*/
 #define CFG_SDRAM_BASE	    0x00000000	    /* _must_ be 0		*/
 #define CFG_FLASH_BASE	    0xff800000	    /* start of FLASH		*/
-#define CFG_MONITOR_BASE    0xfffc0000	    /* start of monitor		*/
 #define CFG_PCI_MEMBASE	    0x80000000	    /* mapped pci memory	*/
 #define CFG_PERIPHERAL_BASE 0xe0000000	    /* internal peripherals	*/
 #define CFG_ISRAM_BASE	    0xc0000000	    /* internal SRAM		*/
@@ -74,18 +78,11 @@
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN	    (256 * 1024)    /* Reserve 256 kB for Mon	*/
-#define CFG_MALLOC_LEN	    (128 * 1024)    /* Reserve 128 kB for malloc*/
-
 /*-----------------------------------------------------------------------
  * Serial Port
  *----------------------------------------------------------------------*/
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
 #define CFG_EXT_SERIAL_CLOCK	(1843200 * 6)	/* Ext clk @ 11.059 MHz */
-#define CONFIG_BAUDRATE		115200
-
-#define CFG_BAUDRATE_TABLE  \
-    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
 
 /*-----------------------------------------------------------------------
  * NVRAM/RTC
@@ -141,10 +138,7 @@
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C		1	    /* I2C with hardware support	*/
-#undef	CONFIG_SOFT_I2C			    /* I2C bit-banged		*/
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
 
 #define CFG_I2C_MULTI_EEPROMS
 #define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
@@ -153,125 +147,31 @@
 #define CFG_EEPROM_PAGE_WRITE_BITS 3
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
 
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
+/*
+ * Default environment variables
+ */
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"hostname=ebony\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
-	        "bootm\0"						\
-	"rootpath=/opt/eldk/ppc_4xx\0"					\
-	"bootfile=/tftpboot/ebony/uImage\0"				\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
 	"kernel_addr=ff800000\0"					\
 	"ramdisk_addr=ff810000\0"					\
-	"initrd_high=30000000\0"					\
-	"load=tftp 100000 /tftpboot/ebony/u-boot.bin\0"		        \
-	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
-		"cp.b 100000 fffc0000 40000;"			        \
-		"setenv filesize;saveenv\0"				\
-	"upd=run load update\0"						\
 	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
 
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define CONFIG_BAUDRATE		115200
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		8	/* PHY address			*/
 #define CONFIG_HAS_ETH0
 #define CONFIG_HAS_ETH1
 #define CONFIG_PHY1_ADDR	9	/* EMAC1 PHY address		*/
-#define CONFIG_NET_MULTI	1
-#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
-
 
 /*
- * BOOTP options
+ * Commands additional to the ones defined in amcc-common.h
  */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_SNTP
 
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_LOOPW            1       /* enable loopw command         */
-#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-
 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------
@@ -288,28 +188,4 @@
 #define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
 #define CFG_PCI_SUBSYS_DEVICEID 0xcafe  /* Whatever */
 
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/katmai.h b/include/configs/katmai.h
index cce883f..d3789bd 100644
--- a/include/configs/katmai.h
+++ b/include/configs/katmai.h
@@ -37,8 +37,14 @@
 #define CONFIG_4xx			1	/* ... PPC4xx family	*/
 #define CONFIG_440			1	/* ... PPC440 family	*/
 #define CONFIG_440SPE			1	/* Specifc SPe support	*/
-#undef	CFG_DRAM_TEST				/* Disable-takes long time */
 #define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll	*/
+#define CFG_4xx_RESET_TYPE	0x2	/* use chip reset on this board	*/
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		katmai
+#include "amcc-common.h"
 
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_pre_init		*/
 #define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/
@@ -48,7 +54,6 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
 #define CFG_FLASH_BASE		0xff000000	/* start of FLASH	*/
 #define CFG_PERIPHERAL_BASE	0xa0000000	/* internal peripherals	*/
 #define CFG_ISRAM_BASE		0x90000000	/* internal SRAM	*/
@@ -78,10 +83,6 @@
 
 #define CFG_ACE_BASE		0xfe000000	/* Xilinx ACE controller - Compact Flash */
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define CFG_MONITOR_LEN		(0xFFFFFFFF - CFG_MONITOR_BASE + 1)
-#define CFG_MALLOC_LEN		(512 * 1024)	/* Reserve 512 kB for malloc */
-
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in internal SRAM)
  *----------------------------------------------------------------------*/
@@ -98,12 +99,8 @@
 /*-----------------------------------------------------------------------
  * Serial Port
  *----------------------------------------------------------------------*/
-#define CONFIG_SERIAL_MULTI	1
 #undef CONFIG_UART1_CONSOLE
 #undef CFG_EXT_SERIAL_CLOCK
-#define CONFIG_BAUDRATE		115200
-#define CFG_BAUDRATE_TABLE  \
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 
 /*-----------------------------------------------------------------------
  * DDR SDRAM
@@ -117,10 +114,7 @@
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
-#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
 #define CFG_I2C_SPEED		100000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
 
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_I2C_CMD_TREE
@@ -172,139 +166,36 @@
  *----------------------------------------------------------------------*/
 #define	CFG_ENV_IS_IN_FLASH	1	/* Environment uses flash	*/
 
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define xstr(s) str(s)
-#define str(s) #s
-
+/*
+ * Default environment variables
+ */
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"hostname=katmai\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
-		"bootm\0"						\
-	"net_nfs_fdt=tftp 200000 ${bootfile};"				\
-		"tftp ${fdt_addr} ${fdt_file};"				\
-		"run nfsargs addip addtty;"				\
-		"bootm 200000 - ${fdt_addr}\0"				\
-	"rootpath=/opt/eldk/ppc_4xx\0"					\
-	"bootfile=katmai/uImage\0"					\
-	"fdt_file=katmai/katmai.dtb\0"					\
-	"fdt_addr=400000\0"						\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
 	"kernel_addr=fff10000\0"					\
 	"ramdisk_addr=fff20000\0"					\
-	"initrd_high=30000000\0"					\
-	"load=tftp 200000 katmai/u-boot.bin\0"				\
-	"update=protect off " xstr(CFG_MONITOR_BASE) " FFFFFFFF;"	\
-		"era " xstr(CFG_MONITOR_BASE) " FFFFFFFF;"		\
-		"cp.b ${fileaddr} " xstr(CFG_MONITOR_BASE) " ${filesize};" \
-		"setenv filesize;saveenv\0"				\
-	"upd=run load update\0"						\
 	"kozio=bootm ffc60000\0"					\
 	"pciconfighost=1\0"						\
 	"pcie_mode=RP:RP:RP\0"						\
 	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
 
 /*
- * Command line configuration.
+ * Commands additional to the ones defined in amcc-common.h
  */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_DTT
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_SNTP
 
 #define	CONFIG_IBM_EMAC4_V4	1	/* 440SPe has this EMAC version	*/
-#define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
 #define CONFIG_HAS_ETH0
 #define CONFIG_PHY_RESET        1	/* reset phy upon startup	*/
 #define CONFIG_PHY_RESET_DELAY	1000
 #define CONFIG_CIS8201_PHY	1	/* Enable 'special' RGMII mode for Cicada phy */
 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
-#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
-#define CONFIG_NET_MULTI		/* needed for NetConsole	*/
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP				/* undef to save memory		*/
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
-
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on		*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM		*/
-
-#define CFG_LOAD_ADDR		0x100000	/* default load address		*/
-#define CFG_EXTBDINFO		1		/* To use extended board_into (bd_t) */
-
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_LOOPW            1       /* enable loopw command         */
-#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-
-#define CFG_4xx_RESET_TYPE	0x2	/* use chip reset on this board	*/
 
 /*-----------------------------------------------------------------------
  * FLASH related
@@ -436,28 +327,4 @@
 #define CFG_GPIO_TCR		GPIO_VAL(CFG_GPIO_RS232_FORCEOFF)
 #define CFG_GPIO_ODR		0
 
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/*Initial Memory map for Linux*/
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM	0x02		/* Software reboot */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h
index a596768..9c1a3a4 100644
--- a/include/configs/kilauea.h
+++ b/include/configs/kilauea.h
@@ -1,4 +1,7 @@
 /*
+ * Copyright (c) 2008 Nuovation System Designs, LLC
+ *   Grant Erickson <gerickson@nuovations.com>
+ *
  * (C) Copyright 2007
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
@@ -36,6 +39,12 @@
 #define CONFIG_405EX		1		/* Specifc 405EX support*/
 #define CONFIG_SYS_CLK_FREQ	33333333	/* ext frequency to pll	*/
 
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		kilauea
+#include "amcc-common.h"
+
 #define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
 #define CONFIG_MISC_INIT_R	1		/* Call misc_init_r	*/
 #define CONFIG_BOARD_EMAC_COUNT
@@ -44,43 +53,70 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE		0x00000000
 #define CFG_FLASH_BASE		0xFC000000
 #define CFG_NAND_ADDR		0xF8000000
 #define CFG_FPGA_BASE		0xF0000000
 #define CFG_PERIPHERAL_BASE	0xEF600000      /* internal peripherals*/
-#define CFG_MONITOR_LEN		(384 * 1024)	/* Reserve 384 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(512 * 1024)	/* Reserve 512 kB for malloc()	*/
-#define CFG_MONITOR_BASE	(TEXT_BASE)
 
 /*-----------------------------------------------------------------------
- * Initial RAM & stack pointer
- *----------------------------------------------------------------------*/
-#define CFG_INIT_RAM_ADDR	0x02000000	/* inside of SDRAM	*/
-#define CFG_INIT_RAM_END	(4 << 10)
+ * Initial RAM & Stack Pointer Configuration Options
+ *
+ *   There are traditionally three options for the primordial
+ *   (i.e. initial) stack usage on the 405-series:
+ *
+ *      1) On-chip Memory (OCM) (i.e. SRAM)
+ *      2) Data cache
+ *      3) SDRAM
+ *
+ *   For the 405EX(r), there is no OCM, so we are left with (2) or (3)
+ *   the latter of which is less than desireable since it requires
+ *   setting up the SDRAM and ECC in assembly code.
+ *
+ *   To use (2), define 'CFG_INIT_DCACHE_CS' to be an unused chip
+ *   select on the External Bus Controller (EBC) and then select a
+ *   value for 'CFG_INIT_RAM_ADDR' outside of the range of valid,
+ *   physical SDRAM. Otherwise, undefine 'CFG_INIT_DCACHE_CS' and
+ *   select a value for 'CFG_INIT_RAM_ADDR' within the range of valid,
+ *   physical SDRAM to use (3).
+ *-----------------------------------------------------------------------*/
+
+#define CFG_INIT_DCACHE_CS	4
+
+#if defined(CFG_INIT_DCACHE_CS)
+#define CFG_INIT_RAM_ADDR	(CFG_SDRAM_BASE + ( 1 << 30))	/*  1 GiB */
+#else
+#define CFG_INIT_RAM_ADDR	(CFG_SDRAM_BASE + (32 << 20))	/* 32 MiB */
+#endif /* defined(CFG_INIT_DCACHE_CS) */
+
+#define CFG_INIT_RAM_END        (4 << 10)			/*  4 KiB */
 #define CFG_GBL_DATA_SIZE	256		/* num bytes initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-/* reserve some memory for POST and BOOT limit info */
-#define CFG_INIT_SP_OFFSET	(CFG_GBL_DATA_OFFSET - 16)
 
-/* extra data in init-ram */
-#define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 4)
-#define CFG_POST_MAGIC		(CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 8)
-#define CFG_POST_VAL		(CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 12)
-#define CFG_OCM_DATA_ADDR	CFG_INIT_RAM_ADDR /* for commproc.c	*/
+/*
+ * If the data cache is being used for the primordial stack and global
+ * data area, the POST word must be placed somewhere else. The General
+ * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
+ * its compare and mask register contents across reset, so it is used
+ * for the POST word.
+ */
+
+#if defined(CFG_INIT_DCACHE_CS)
+# define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+# define CFG_POST_ALT_WORD_ADDR	(CFG_PERIPHERAL_BASE + GPT0_COMP6)
+#else
+# define CFG_INIT_EXTRA_SIZE	16
+# define CFG_INIT_SP_OFFSET	(CFG_GBL_DATA_OFFSET - CFG_INIT_EXTRA_SIZE)
+# define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 4)
+# define CFG_OCM_DATA_ADDR	CFG_INIT_RAM_ADDR
+#endif /* defined(CFG_INIT_DCACHE_CS) */
 
 /*-----------------------------------------------------------------------
  * Serial Port
  *----------------------------------------------------------------------*/
 #define CFG_EXT_SERIAL_CLOCK	11059200	/* ext. 11.059MHz clk	*/
-#define CONFIG_BAUDRATE		115200
-#define CONFIG_SERIAL_MULTI     1
 /* define this if you want console on UART1 */
 #undef CONFIG_UART1_CONSOLE
 
-#define CFG_BAUDRATE_TABLE						\
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
 /*-----------------------------------------------------------------------
  * Environment
  *----------------------------------------------------------------------*/
@@ -131,9 +167,9 @@
  * This NAND U-Boot (NUB) is a special U-Boot version which can be started
  * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
  *
- * On 440EPx the SPL is copied to SDRAM before the NAND controller is
- * set up. While still running from cache, I experienced problems accessing
- * the NAND controller.	sr - 2006-08-25
+ * On 405EX the SPL is copied to SDRAM before the NAND controller is
+ * set up. While still running from location 0xfffff000...0xffffffff the
+ * NAND controller cannot be accessed since it is attached to CS0 too.
  */
 #define CFG_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location			*/
 #define CFG_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size			*/
@@ -187,12 +223,54 @@
  *----------------------------------------------------------------------*/
 #define CFG_MBYTES_SDRAM        (256)		/* 256MB			*/
 
+#define	CFG_SDRAM0_MB0CF_BASE	((  0 << 20) + CFG_SDRAM_BASE)
+
+/* DDR1/2 SDRAM Device Control Register Data Values */
+#define CFG_SDRAM0_MB0CF	((CFG_SDRAM0_MB0CF_BASE >> 3)	| \
+				 SDRAM_RXBAS_SDSZ_256MB		| \
+				 SDRAM_RXBAS_SDAM_MODE7		| \
+				 SDRAM_RXBAS_SDBE_ENABLE)
+#define CFG_SDRAM0_MB1CF	SDRAM_RXBAS_SDBE_DISABLE
+#define CFG_SDRAM0_MB2CF	SDRAM_RXBAS_SDBE_DISABLE
+#define CFG_SDRAM0_MB3CF	SDRAM_RXBAS_SDBE_DISABLE
+#define CFG_SDRAM0_MCOPT1	0x04322000
+#define CFG_SDRAM0_MCOPT2	0x00000000
+#define CFG_SDRAM0_MODT0	0x01800000
+#define CFG_SDRAM0_MODT1	0x00000000
+#define CFG_SDRAM0_CODT		0x0080f837
+#define CFG_SDRAM0_RTR		0x06180000
+#define CFG_SDRAM0_INITPLR0	0xa8380000
+#define CFG_SDRAM0_INITPLR1	0x81900400
+#define CFG_SDRAM0_INITPLR2	0x81020000
+#define CFG_SDRAM0_INITPLR3	0x81030000
+#define CFG_SDRAM0_INITPLR4	0x81010404
+#define CFG_SDRAM0_INITPLR5	0x81000542
+#define CFG_SDRAM0_INITPLR6	0x81900400
+#define CFG_SDRAM0_INITPLR7	0x8D080000
+#define CFG_SDRAM0_INITPLR8	0x8D080000
+#define CFG_SDRAM0_INITPLR9	0x8D080000
+#define CFG_SDRAM0_INITPLR10	0x8D080000
+#define CFG_SDRAM0_INITPLR11	0x81000442
+#define CFG_SDRAM0_INITPLR12	0x81010780
+#define CFG_SDRAM0_INITPLR13	0x81010400
+#define CFG_SDRAM0_INITPLR14	0x00000000
+#define CFG_SDRAM0_INITPLR15	0x00000000
+#define CFG_SDRAM0_RQDC		0x80000038
+#define CFG_SDRAM0_RFDC		0x00000209
+#define CFG_SDRAM0_RDCC		0x40000000
+#define CFG_SDRAM0_DLCR		0x030000a5
+#define CFG_SDRAM0_CLKTR	0x80000000
+#define CFG_SDRAM0_WRDTR	0x00000000
+#define CFG_SDRAM0_SDTR1	0x80201000
+#define CFG_SDRAM0_SDTR2	0x32204232
+#define CFG_SDRAM0_SDTR3	0x080b0d1a
+#define CFG_SDRAM0_MMODE	0x00000442
+#define CFG_SDRAM0_MEMODE	0x00000404
+
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
 
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	6	/* 24C02 requires 5ms delay */
 #define CFG_I2C_EEPROM_ADDR	0x52	/* I2C boot EEPROM (24C02BN)	*/
@@ -212,7 +290,6 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_M88E1111_PHY	1
 #define CONFIG_IBM_EMAC4_V4	1
-#define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
 
 #define CONFIG_PHY_RESET	1	/* reset phy upon startup	*/
@@ -220,107 +297,37 @@
 
 #define CONFIG_HAS_ETH0		1
 
-#define CONFIG_NET_MULTI	1
 #define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"   */
 #define CONFIG_PHY1_ADDR	2
 
-#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
+/*
+ * Default environment variables
+ */
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	CONFIG_AMCC_DEF_ENV_NAND_UPD					\
 	"logversion=2\0"						\
-	"netdev=eth0\0"							\
-	"hostname=kilauea\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
-	"flash_self_old=run ramargs addip addtty;"			\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
-	"flash_nfs_old=run nfsargs addip addtty;"			\
-		"bootm ${kernel_addr}\0"				\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
-	"net_nfs_old=tftp ${kernel_addr_r} ${bootfile};"		\
-		"run nfsargs addip addtty;bootm ${kernel_addr_r}\0"	\
-	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
-		"tftp ${fdt_addr_r} ${fdt_file}; "			\
-		"run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
-	"rootpath=/opt/eldk/ppc_4xx\0"					\
-	"bootfile=kilauea/uImage\0"					\
-	"fdt_file=kilauea/kilauea.dtb\0"				\
-	"kernel_addr_r=400000\0"					\
-	"fdt_addr_r=800000\0"						\
 	"kernel_addr=fc000000\0"					\
 	"fdt_addr=fc1e0000\0"						\
 	"ramdisk_addr=fc200000\0"					\
-	"initrd_high=30000000\0"					\
-	"load=tftp 200000 kilauea/u-boot.bin\0"				\
-	"update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;"	\
-		"cp.b ${fileaddr} fffa0000 ${filesize};"		\
-		"setenv filesize;saveenv\0"				\
-	"upd=run load update\0"						\
-	"nload=tftp 200000 kilauea/u-boot-nand.bin\0"			\
-	"nupdate=nand erase 0 60000;nand write 200000 0 60000;"		\
-		"setenv filesize;saveenv\0"				\
-	"nupd=run nload nupdate\0"					\
 	"pciconfighost=1\0"						\
 	"pcie_mode=RP:RP\0"						\
 	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE		/* allow baudrate change	*/
 
 /*
- * BOOTP options
+ * Commands additional to the ones defined in amcc-common.h
  */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_SUBNETMASK
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_DTT
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
 #define CONFIG_CMD_LOG
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_SNTP
 
 /* POST support */
-#define CONFIG_POST		(CFG_POST_MEMORY	| \
-				 CFG_POST_CACHE		| \
+#define CONFIG_POST		(CFG_POST_CACHE		| \
 				 CFG_POST_CPU		| \
 				 CFG_POST_ETHER		| \
 				 CFG_POST_I2C		| \
@@ -335,37 +342,6 @@
 
 #define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
 
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- *----------------------------------------------------------------------*/
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	        16	/* max number of command args	*/
-#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000 /* memtest works on		*/
-#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR		0x100000  /* default load address	*/
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-
-#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks	*/
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_LOOPW            1       /* enable loopw command         */
-#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
-
 /*-----------------------------------------------------------------------
  * PCI stuff
  *----------------------------------------------------------------------*/
@@ -394,13 +370,6 @@
 /* base address of inbound PCIe window */
 #define CFG_PCIE_INBOUND_BASE	0x0000000000000000ULL
 
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  *----------------------------------------------------------------------*/
@@ -429,7 +398,7 @@
 
 /* Memory Bank 2 (FPGA) initialization						*/
 #define CFG_EBC_PB2AP           0x9400C800
-#define CFG_EBC_PB2CR           0xF0018000 /*  BAS=0x800,BS=1MB,BU=R/W,BW=8bit	*/
+#define CFG_EBC_PB2CR		(CFG_FPGA_BASE | 0x18000)
 
 #define CFG_EBC_CFG		0x7FC00000 /*  EBC0_CFG */
 
@@ -474,19 +443,6 @@
 }												\
 }
 
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-
 /*-----------------------------------------------------------------------
  * Some Kilauea stuff..., mainly fpga registers
  */
@@ -522,8 +478,4 @@
 #define CFG_FPGA_USER_LED0		0x00000200
 #define CFG_FPGA_USER_LED1		0x00000100
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/luan.h b/include/configs/luan.h
index 37151d3..805cc59 100644
--- a/include/configs/luan.h
+++ b/include/configs/luan.h
@@ -37,6 +37,12 @@
 #define CONFIG_440		1
 #define CONFIG_SYS_CLK_FREQ	33333333 /* external freq to pll	*/
 
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		luan
+#include "amcc-common.h"
+
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
 #define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
 
@@ -44,11 +50,6 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc  */
-#define CFG_MONITOR_BASE	(-CFG_MONITOR_LEN)
-#define CFG_SDRAM_BASE	        0x00000000	/* MUST be zero */
-
 #define CFG_LARGE_FLASH		0xffc00000	/* 4MB flash address CS0 */
 #define CFG_SMALL_FLASH		0xff900000	/* 1MB flash address CS2 */
 #define CFG_SRAM_BASE		0xff800000	/* 1MB SRAM  address CS2 */
@@ -68,7 +69,6 @@
 #define CFG_FLASH_BASE		CFG_SMALL_FLASH
 #endif
 
-#undef CFG_DRAM_TEST
 #if CFG_SRAM_BASE
 #define CFG_KBYTES_SDRAM	1024*2
 #else
@@ -88,13 +88,8 @@
  * Serial Port
  *----------------------------------------------------------------------*/
 #define CFG_EXT_SERIAL_CLOCK	11059200 /* external 11.059MHz clk */
-#define CONFIG_BAUDRATE		115200
-#undef  CONFIG_SERIAL_MULTI
 #undef  CONFIG_UART1_CONSOLE		/* define if you want console on UART1 */
 
-#define CFG_BAUDRATE_TABLE  \
-    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
 /*-----------------------------------------------------------------------
  * Environment
  *----------------------------------------------------------------------*/
@@ -139,10 +134,7 @@
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
-#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
 
 #define CFG_I2C_MULTI_EEPROMS
 #define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
@@ -151,61 +143,22 @@
 #define CFG_EEPROM_PAGE_WRITE_BITS 3
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
 
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"hostname=luan\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=$(serverip):$(rootpath)\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs $(bootargs) "				\
-		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
-		":$(hostname):$(netdev):off panic=1\0"			\
-	"addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm $(kernel_addr)\0"				\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
-	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;"     \
-	        "bootm\0"						\
-	"rootpath=/opt/eldk/ppc_4xx\0"					\
-	"bootfile=/tftpboot/luan/uImage\0"				\
+/*
+ * Default environment variables
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_PPC						\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
 	"kernel_addr=fc000000\0"					\
 	"ramdisk_addr=fc100000\0"					\
-	"initrd_high=30000000\0"					\
-	"load=tftp 100000 /tftpboot/luan/u-boot.bin\0"			\
-	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
-		"cp.b 100000 fffc0000 40000;"			        \
-		"setenv filesize;saveenv\0"				\
-	"upd=run load update\0"						\
 	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_HAS_ETH0
-#define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		1
 #define CONFIG_CIS8201_PHY	1	/* Enable 'special' RGMII mode for Cicada phy */
 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
 
-#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
-#define CONFIG_NET_MULTI		/* needed for NetConsole	*/
-
 #ifdef DEBUG
 #define CONFIG_PANIC_HANG
 #else
@@ -213,60 +166,11 @@
 #endif
 
 /*
- * BOOTP options
+ * Commands additional to the ones defined in amcc-common.h
  */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_SDRAM
 
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	        16	/* max number of command args	*/
-#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000 /* memtest works on	        */
-#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR		0x100000 /* default load address */
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-#undef  CONFIG_LYNXKDI			/* support kdi files            */
-
-#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_LOOPW            1       /* enable loopw command         */
-#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-
 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------
@@ -287,28 +191,4 @@
 
 #endif
 
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/makalu.h b/include/configs/makalu.h
index af066f3..65b240e 100644
--- a/include/configs/makalu.h
+++ b/include/configs/makalu.h
@@ -1,4 +1,7 @@
 /*
+ * Copyright (c) 2008 Nuovation System Designs, LLC
+ *   Grant Erickson <gerickson@nuovations.com>
+ *
  * (C) Copyright 2007-2008
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
@@ -36,6 +39,13 @@
 #define CONFIG_405EX		1		/* Specifc 405EX support*/
 #define CONFIG_SYS_CLK_FREQ	33330000	/* ext frequency to pll	*/
 
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME	makalu
+#define CONFIG_ADDMISC	"addmisc=setenv bootargs ${bootargs} rtc-x1205.probe=0,0x6f\0"
+#include "amcc-common.h"
+
 #define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
 #define CONFIG_MISC_INIT_R	1		/* Call misc_init_r	*/
 
@@ -43,42 +53,69 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE		0x00000000
 #define CFG_FLASH_BASE		0xFC000000
 #define CFG_FPGA_BASE		0xF0000000
 #define CFG_PERIPHERAL_BASE	0xEF600000      /* internal peripherals*/
-#define CFG_MONITOR_LEN		(384 * 1024)	/* Reserve 384 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(512 * 1024)	/* Reserve 512 kB for malloc()	*/
-#define CFG_MONITOR_BASE	(TEXT_BASE)
 
 /*-----------------------------------------------------------------------
- * Initial RAM & stack pointer
- *----------------------------------------------------------------------*/
-#define CFG_INIT_RAM_ADDR	0x02000000	/* inside of SDRAM	*/
-#define CFG_INIT_RAM_END	(4 << 10)
+ * Initial RAM & Stack Pointer Configuration Options
+ *
+ *   There are traditionally three options for the primordial
+ *   (i.e. initial) stack usage on the 405-series:
+ *
+ *      1) On-chip Memory (OCM) (i.e. SRAM)
+ *      2) Data cache
+ *      3) SDRAM
+ *
+ *   For the 405EX(r), there is no OCM, so we are left with (2) or (3)
+ *   the latter of which is less than desireable since it requires
+ *   setting up the SDRAM and ECC in assembly code.
+ *
+ *   To use (2), define 'CFG_INIT_DCACHE_CS' to be an unused chip
+ *   select on the External Bus Controller (EBC) and then select a
+ *   value for 'CFG_INIT_RAM_ADDR' outside of the range of valid,
+ *   physical SDRAM. Otherwise, undefine 'CFG_INIT_DCACHE_CS' and
+ *   select a value for 'CFG_INIT_RAM_ADDR' within the range of valid,
+ *   physical SDRAM to use (3).
+ *-----------------------------------------------------------------------*/
+
+#define CFG_INIT_DCACHE_CS	4
+
+#if defined(CFG_INIT_DCACHE_CS)
+#define CFG_INIT_RAM_ADDR	(CFG_SDRAM_BASE + ( 1 << 30))	/*  1 GiB */
+#else
+#define CFG_INIT_RAM_ADDR	(CFG_SDRAM_BASE + (32 << 20))	/* 32 MiB */
+#endif /* defined(CFG_INIT_DCACHE_CS) */
+
+#define CFG_INIT_RAM_END        (4 << 10)			/*  4 KiB */
 #define CFG_GBL_DATA_SIZE	256		/* num bytes initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-/* reserve some memory for POST and BOOT limit info */
-#define CFG_INIT_SP_OFFSET	(CFG_GBL_DATA_OFFSET - 16)
 
-/* extra data in init-ram */
-#define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 4)
-#define CFG_POST_MAGIC		(CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 8)
-#define CFG_POST_VAL		(CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 12)
-#define CFG_OCM_DATA_ADDR	CFG_INIT_RAM_ADDR /* for commproc.c	*/
+/*
+ * If the data cache is being used for the primordial stack and global
+ * data area, the POST word must be placed somewhere else. The General
+ * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
+ * its compare and mask register contents across reset, so it is used
+ * for the POST word.
+ */
+
+#if defined(CFG_INIT_DCACHE_CS)
+# define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+# define CFG_POST_ALT_WORD_ADDR	(CFG_PERIPHERAL_BASE + GPT0_COMP6)
+#else
+# define CFG_INIT_EXTRA_SIZE	16
+# define CFG_INIT_SP_OFFSET	(CFG_GBL_DATA_OFFSET - CFG_INIT_EXTRA_SIZE)
+# define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 4)
+# define CFG_OCM_DATA_ADDR	CFG_INIT_RAM_ADDR
+#endif /* defined(CFG_INIT_DCACHE_CS) */
 
 /*-----------------------------------------------------------------------
  * Serial Port
  *----------------------------------------------------------------------*/
 #undef CFG_EXT_SERIAL_CLOCK			/* no ext. clk		*/
-#define CONFIG_BAUDRATE		115200
-#define CONFIG_SERIAL_MULTI     1
 /* define this if you want console on UART1 */
 #undef CONFIG_UART1_CONSOLE
 
-#define CFG_BAUDRATE_TABLE						\
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
 /*-----------------------------------------------------------------------
  * Environment
  *----------------------------------------------------------------------*/
@@ -113,14 +150,60 @@
 /*-----------------------------------------------------------------------
  * DDR SDRAM
  *----------------------------------------------------------------------*/
-#define CFG_MBYTES_SDRAM	256
+#define CFG_MBYTES_SDRAM        (256)		/* 256MB			*/
+
+#define	CFG_SDRAM0_MB0CF_BASE	((  0 << 20) + CFG_SDRAM_BASE)
+#define	CFG_SDRAM0_MB1CF_BASE	((128 << 20) + CFG_SDRAM_BASE)
+
+/* DDR1/2 SDRAM Device Control Register Data Values */
+#define CFG_SDRAM0_MB0CF	((CFG_SDRAM0_MB0CF_BASE >> 3)	| \
+				 SDRAM_RXBAS_SDSZ_128MB 	| \
+				 SDRAM_RXBAS_SDAM_MODE2 	| \
+				 SDRAM_RXBAS_SDBE_ENABLE)
+#define CFG_SDRAM0_MB1CF	((CFG_SDRAM0_MB1CF_BASE >> 3)	| \
+				 SDRAM_RXBAS_SDSZ_128MB 	| \
+				 SDRAM_RXBAS_SDAM_MODE2 	| \
+				 SDRAM_RXBAS_SDBE_ENABLE)
+#define CFG_SDRAM0_MB2CF	SDRAM_RXBAS_SDBE_DISABLE
+#define CFG_SDRAM0_MB3CF	SDRAM_RXBAS_SDBE_DISABLE
+#define CFG_SDRAM0_MCOPT1	0x04322000
+#define CFG_SDRAM0_MCOPT2	0x00000000
+#define CFG_SDRAM0_MODT0	0x01800000
+#define CFG_SDRAM0_MODT1	0x00000000
+#define CFG_SDRAM0_CODT		0x0080f837
+#define CFG_SDRAM0_RTR		0x06180000
+#define CFG_SDRAM0_INITPLR0	0xa8380000
+#define CFG_SDRAM0_INITPLR1	0x81900400
+#define CFG_SDRAM0_INITPLR2	0x81020000
+#define CFG_SDRAM0_INITPLR3	0x81030000
+#define CFG_SDRAM0_INITPLR4	0x81010404
+#define CFG_SDRAM0_INITPLR5	0x81000542
+#define CFG_SDRAM0_INITPLR6	0x81900400
+#define CFG_SDRAM0_INITPLR7	0x8D080000
+#define CFG_SDRAM0_INITPLR8	0x8D080000
+#define CFG_SDRAM0_INITPLR9	0x8D080000
+#define CFG_SDRAM0_INITPLR10	0x8D080000
+#define CFG_SDRAM0_INITPLR11	0x81000442
+#define CFG_SDRAM0_INITPLR12	0x81010780
+#define CFG_SDRAM0_INITPLR13	0x81010400
+#define CFG_SDRAM0_INITPLR14	0x00000000
+#define CFG_SDRAM0_INITPLR15	0x00000000
+#define CFG_SDRAM0_RQDC		0x80000038
+#define CFG_SDRAM0_RFDC		0x00000209
+#define CFG_SDRAM0_RDCC		0x40000000
+#define CFG_SDRAM0_DLCR		0x030000a5
+#define CFG_SDRAM0_CLKTR	0x80000000
+#define CFG_SDRAM0_WRDTR	0x00000000
+#define CFG_SDRAM0_SDTR1	0x80201000
+#define CFG_SDRAM0_SDTR2	0x32204232
+#define CFG_SDRAM0_SDTR3	0x080b0d1a
+#define CFG_SDRAM0_MMODE	0x00000442
+#define CFG_SDRAM0_MEMODE	0x00000404
 
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
 
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	6	/* 24C02 requires 5ms delay */
 #define CFG_I2C_EEPROM_ADDR	0x52	/* I2C boot EEPROM (24C02BN)	*/
@@ -140,7 +223,6 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_M88E1111_PHY	1
 #define CONFIG_IBM_EMAC4_V4	1
-#define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		6	/* PHY address, See schematics	*/
 
 #define CONFIG_PHY_RESET	1	/* reset phy upon startup	*/
@@ -148,104 +230,35 @@
 
 #define CONFIG_HAS_ETH0		1
 
-#define CONFIG_NET_MULTI	1
 #define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"   */
 #define CONFIG_PHY1_ADDR	0
 
-#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
+/*
+ * Default environment variables
+ */
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"logversion=2\0"						\
-	"netdev=eth0\0"							\
-	"hostname=makalu\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
-	"addmisc=setenv bootargs ${bootargs} rtc-x1205.probe=0,0x6f\0"	\
-	"flash_self_old=run ramargs addip addtty addmisc;"		\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"flash_self=run ramargs addip addtty addmisc;"			\
-		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
-	"flash_nfs_old=run nfsargs addip addtty addmisc;"		\
-		"bootm ${kernel_addr}\0"				\
-	"flash_nfs=run nfsargs addip addtty addmisc;"			\
-		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
-	"net_nfs_old=tftp ${kernel_addr_r} ${bootfile};"		\
-		"run nfsargs addip addtty addmisc;"			\
-		"bootm ${kernel_addr_r}\0"				\
-	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
-		"tftp ${fdt_addr_r} ${fdt_file}; "			\
-		"run nfsargs addip addtty addmisc;"			\
-		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
-	"rootpath=/opt/eldk/ppc_4xx\0"					\
-	"bootfile=makalu/uImage\0"					\
-	"fdt_file=makalu/makalu.dtb\0"					\
-	"kernel_addr_r=400000\0"					\
-	"fdt_addr_r=800000\0"						\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
 	"kernel_addr=fc000000\0"					\
 	"fdt_addr=fc1e0000\0"						\
 	"ramdisk_addr=fc200000\0"					\
-	"initrd_high=30000000\0"					\
-	"load=tftp 200000 makalu/u-boot.bin\0"				\
-	"update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;"	\
-		"cp.b ${fileaddr} fffa0000 ${filesize};"		\
-		"setenv filesize;saveenv\0"				\
-	"upd=run load update\0"						\
 	"pciconfighost=1\0"						\
 	"pcie_mode=RP:RP\0"						\
 	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE		/* allow baudrate change	*/
 
 /*
- * BOOTP options
+ * Commands additional to the ones defined in amcc-common.h
  */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_SUBNETMASK
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
 #define CONFIG_CMD_DTT
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
 #define CONFIG_CMD_LOG
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_SNTP
 
 /* POST support */
-#define CONFIG_POST		(CFG_POST_MEMORY	| \
-				 CFG_POST_CACHE		| \
+#define CONFIG_POST		(CFG_POST_CACHE		| \
 				 CFG_POST_CPU		| \
 				 CFG_POST_ETHER		| \
 				 CFG_POST_I2C		| \
@@ -260,37 +273,6 @@
 
 #define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
 
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- *----------------------------------------------------------------------*/
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	        16	/* max number of command args	*/
-#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000 /* memtest works on		*/
-#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR		0x100000  /* default load address	*/
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-
-#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks	*/
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_LOOPW            1       /* enable loopw command         */
-#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
-
 /*-----------------------------------------------------------------------
  * PCI stuff
  *----------------------------------------------------------------------*/
@@ -319,13 +301,6 @@
 /* base address of inbound PCIe window */
 #define CFG_PCIE_INBOUND_BASE	0x0000000000000000ULL
 
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  *----------------------------------------------------------------------*/
@@ -384,21 +359,4 @@
 #define CFG_GPIO_PCIE_CLKREQ	27
 #define CFG_GPIO_PCIE_WAKE	28
 
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h
index be2b3ec..407aae7 100644
--- a/include/configs/ocotea.h
+++ b/include/configs/ocotea.h
@@ -44,16 +44,19 @@
 #define CONFIG_440		1	    /* ... PPC440 family	*/
 #define CONFIG_4xx		1	    /* ... PPC4xx family	*/
 #define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_pre_init	*/
-#undef	CFG_DRAM_TEST			    /* Disable-takes long time! */
 #define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
 
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		ocotea
+#include "amcc-common.h"
+
 /*-----------------------------------------------------------------------
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE	    0x00000000	    /* _must_ be 0		*/
 #define CFG_FLASH_BASE	    0xff800000	    /* start of FLASH		*/
-#define CFG_MONITOR_BASE    0xfffc0000	    /* start of monitor		*/
 #define CFG_PCI_MEMBASE	    0x80000000	    /* mapped pci memory	*/
 #define CFG_PERIPHERAL_BASE 0xe0000000	    /* internal peripherals	*/
 #define CFG_ISRAM_BASE	    0xc0000000	    /* internal SRAM		*/
@@ -75,18 +78,11 @@
 #define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 0x4)
 #define CFG_INIT_SP_OFFSET	CFG_POST_WORD_ADDR
 
-#define CFG_MONITOR_LEN	    (256 * 1024)    /* Reserve 256 kB for Mon	*/
-#define CFG_MALLOC_LEN	    (128 * 1024)    /* Reserve 128 kB for malloc*/
-
 /*-----------------------------------------------------------------------
  * Serial Port
  *----------------------------------------------------------------------*/
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
 #define CFG_EXT_SERIAL_CLOCK	(1843200 * 6)	/* Ext clk @ 11.059 MHz */
-#define CONFIG_BAUDRATE		115200
-
-#define CFG_BAUDRATE_TABLE  \
-    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 
 /*-----------------------------------------------------------------------
  * Environment
@@ -156,10 +152,7 @@
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C		1	    /* I2C with hardware support	*/
-#undef	CONFIG_SOFT_I2C			    /* I2C bit-banged		*/
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
 
 #define CFG_I2C_MULTI_EEPROMS
 #define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
@@ -168,54 +161,17 @@
 #define CFG_EEPROM_PAGE_WRITE_BITS 3
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
 
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
+/*
+ * Default environment variables
+ */
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"hostname=ocotea\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
-	        "bootm\0"						\
-	"rootpath=/opt/eldk/ppc_4xx\0"					\
-	"bootfile=/tftpboot/ocotea/uImage\0"				\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_PPC						\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
 	"kernel_addr=fff00000\0"					\
 	"ramdisk_addr=fff10000\0"					\
-	"initrd_high=30000000\0"					\
-	"load=tftp 100000 /tftpboot/ocotea/u-boot.bin\0"		\
-	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
-		"cp.b 100000 fffc0000 40000;"			        \
-		"setenv filesize;saveenv\0"				\
-	"upd=run load update\0"						\
 	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
 
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define CONFIG_BAUDRATE		115200
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_NET_MULTI	1
 #define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
 #define CONFIG_PHY1_ADDR	2
 #define CONFIG_PHY2_ADDR	0x10
@@ -228,73 +184,15 @@
 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
 #define CONFIG_PHY_RESET        1       /* reset phy upon startup         */
 #define CONFIG_PHY_RESET_DELAY	1000
-#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
-
 
 /*
- * BOOTP options
+ * Commands additional to the ones defined in amcc-common.h
  */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_SNTP
 
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_LOOPW            1       /* enable loopw command         */
-#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-
 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------
@@ -311,28 +209,4 @@
 #define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
 #define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
 
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index 48251f3..f4eefae 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -34,11 +34,19 @@
 /* This config file is used for Sequoia (440EPx) and Rainier (440GRx)	*/
 #ifndef CONFIG_RAINIER
 #define CONFIG_440EPX		1	/* Specific PPC440EPx		*/
+#define CONFIG_HOSTNAME		sequoia
 #else
 #define CONFIG_440GRX		1	/* Specific PPC440GRx		*/
+#define CONFIG_HOSTNAME		rainier
 #endif
 #define CONFIG_440		1	/* ... PPC440 family		*/
 #define CONFIG_4xx		1	/* ... PPC4xx family		*/
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#include "amcc-common.h"
+
 /* Detect Sequoia PLL input clock automatically via CPLD bit		*/
 #define CONFIG_SYS_CLK_FREQ    ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \
 				33333333 : 33000000)
@@ -64,19 +72,9 @@
  * Base addresses -- Note these are effective addresses where the actual
  * resources get mapped (not physical addresses).
  */
-#ifndef CONFIG_VIDEO
-#define CFG_MONITOR_LEN		(384 * 1024) /* Reserve 384 kiB for Monitor  */
-#define CFG_MALLOC_LEN		(256 * 1024) /* Reserve 256 kiB for malloc() */
-#else
-#define CFG_MONITOR_LEN		(512 * 1024)    /* Reserve 512 kB for Monitor   */
-#define CFG_MALLOC_LEN		(1024 * 1024)   /* Reserve 1024 kB for malloc() */
-#endif
-
 #define CFG_TLB_FOR_BOOT_FLASH	0x0003
 #define CFG_BOOT_BASE_ADDR	0xf0000000
-#define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
 #define CFG_FLASH_BASE		0xfc000000	/* start of FLASH	*/
-#define CFG_MONITOR_BASE	TEXT_BASE
 #define CFG_NAND_ADDR		0xd0000000	/* NAND Flash		*/
 #define CFG_OCM_BASE		0xe0010000	/* ocm			*/
 #define CFG_OCM_DATA_ADDR	CFG_OCM_BASE
@@ -108,14 +106,9 @@
  * Serial Port
  */
 #define CFG_EXT_SERIAL_CLOCK	11059200	/* ext. 11.059MHz clk	*/
-#define CONFIG_BAUDRATE		115200
-#define CONFIG_SERIAL_MULTI	1
 /* define this if you want console on UART1 */
 #undef CONFIG_UART1_CONSOLE
 
-#define CFG_BAUDRATE_TABLE						\
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
 /*
  * Environment
  */
@@ -227,10 +220,7 @@
 /*
  * I2C
  */
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
-#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
 
 #define CFG_I2C_MULTI_EEPROMS
 #define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
@@ -247,80 +237,27 @@
 #define CFG_DTT_LOW_TEMP	-30
 #define CFG_DTT_HYSTERESIS	3
 
-#define CONFIG_PREBOOT	"echo;"						\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-/* Setup some board specific values for the default environment variables */
-#ifndef CONFIG_RAINIER
-#define CONFIG_HOSTNAME		sequoia
-#define CFG_BOOTFILE		"bootfile=sequoia/uImage\0"
-#define CFG_DTBFILE		"fdt_file=sequoia/sequoia.dtb\0"
-#define CFG_ROOTPATH		"rootpath=/opt/eldk/ppc_4xxFP\0"
-#else
-#define CONFIG_HOSTNAME		rainier
-#define CFG_BOOTFILE		"bootfile=rainier/uImage\0"
-#define CFG_DTBFILE		"fdt_file=rainier/rainier.dtb\0"
-#define CFG_ROOTPATH		"rootpath=/opt/eldk/ppc_4xx\0"
-#endif
-
+/*
+ * Default environment variables
+ */
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
-	CFG_BOOTFILE							\
-	CFG_ROOTPATH							\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
-	"addmisc=setenv bootargs ${bootargs}\0"				\
-	"flash_nfs=run nfsargs addip addtty addmisc;"			\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip addtty addmisc;"			\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};"				\
-		"run nfsargs addip addtty addmisc;"			\
-		"bootm\0"						\
-	"fdt_file=sequoia/sequoia.dtb\0"				\
-	"fdt_addr=400000\0"						\
-	"net_nfs_fdt=tftp 200000 ${bootfile};"				\
-		"tftp ${fdt_addr} ${fdt_file};"				\
-		"run nfsargs addip addtty addmisc;"			\
-		"bootm 200000 - ${fdt_addr}\0"				\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	CONFIG_AMCC_DEF_ENV_NAND_UPD					\
 	"kernel_addr=FC000000\0"					\
 	"ramdisk_addr=FC180000\0"					\
-	"load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0"		\
-	"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;"	\
-		"cp.b 200000 FFFA0000 60000\0"			        \
-	"upd=run load update\0"						\
 	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 #define CONFIG_M88E1111_PHY	1
 #define	CONFIG_IBM_EMAC4_V4	1
-#define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address, See schematics	*/
 
 #define CONFIG_PHY_RESET        1	/* reset phy upon startup	*/
 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
 
 #define CONFIG_HAS_ETH0
-#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx	*/
-					/*   buffers & descriptors	*/
-#define CONFIG_NET_MULTI	1
 #define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
 #define CONFIG_PHY1_ADDR	1
 
@@ -347,35 +284,12 @@
 #define CONFIG_ISO_PARTITION
 
 /*
- * BOOTP options
+ * Commands additional to the ones defined in amcc-common.h
  */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_SUBNETMASK
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DTT
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
 #define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_SDRAM
 
 #ifdef CONFIG_440EPX
@@ -407,35 +321,6 @@
 #define CONFIG_SUPPORT_VFAT
 
 /*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
-					/* Print Buffer Size		*/
-#define CFG_MAXARGS	        16	/* max number of command args	*/
-#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000 /* memtest works on		*/
-#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR		0x100000  /* default load address	*/
-#define CFG_EXTBDINFO		1  /* To use extended board_into (bd_t)	*/
-
-#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks	*/
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_LOOPW		1	/* enable loopw command		*/
-#define CONFIG_MX_CYCLIC	1	/* enable mdc/mwc commands	*/
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable	*/
-
-/*
  * PCI stuff
  */
 /* General PCI */
@@ -453,13 +338,6 @@
 #define CFG_PCI_SUBSYS_ID       0xcafe	/* Whatever			*/
 
 /*
- * For booting Linux, the board info and command line data have to be in the
- * first 8 MB of memory, since this is the maximum mapped by the Linux kernel
- * during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
-
-/*
  * External Bus Controller (EBC) Setup
  */
 
@@ -577,23 +455,6 @@
 }											\
 }
 
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02	/* Software reboot			*/
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400 /* speed to run kgdb serial port	*/
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use	*/
-#endif
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-
 #ifdef CONFIG_VIDEO
 #define CONFIG_BIOSEMU			/* x86 bios emulator for vga bios */
 #define CONFIG_ATI_RADEON_FB		/* use radeon framebuffer driver */
diff --git a/include/configs/taihu.h b/include/configs/taihu.h
index c060b1e..86f776d 100644
--- a/include/configs/taihu.h
+++ b/include/configs/taihu.h
@@ -32,6 +32,12 @@
 #define CONFIG_4xx		1	/*  member of PPC4xx family */
 #define CONFIG_TAIHU	        1	/*  on a taihu board */
 
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		taihu
+#include "amcc-common.h"
+
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f */
 
 #define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
@@ -70,87 +76,31 @@
 
 #define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars */
 
-#define CONFIG_ENV_OVERWRITE 1
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"bootfile=/tftpboot/taihu/uImage\0"				\
-	"rootpath=/opt/eldk/ppc_4xx\0"					\
-	"netdev=eth0\0"							\
-	"hostname=taihu\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
-	        "bootm\0"						\
+/*
+ * Default environment variables
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_PPC						\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
 	"kernel_addr=FC000000\0"					\
 	"ramdisk_addr=FC180000\0"					\
-	"load=tftp 200000 /tftpboot/taihu/u-boot.bin\0"			\
-	"update=protect off FFFC0000 FFFFFFFF;era FFFC0000 FFFFFFFF;"	\
-		"cp.b 200000 FFFC0000 40000\0"				\
-	"upd=run load update\0"						\
 	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
 
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0x14	/* PHY address			*/
 #define CONFIG_HAS_ETH0
 #define CONFIG_HAS_ETH1
 #define CONFIG_PHY1_ADDR	0x10	/* EMAC1 PHY address		*/
-#define CONFIG_NET_MULTI	1
-#define CFG_RX_ETH_BUFFER	16	/* Number of ethernet rx buffers & descriptors */
 #define CONFIG_PHY_RESET	1
 
 /*
- * BOOTP options
+ * Commands additional to the ones defined in amcc-common.h
  */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_SPI
 
-#undef CONFIG_WATCHDOG			/* watchdog disabled */
-
 #undef CONFIG_SPD_EEPROM		/* use SPD EEPROM for setup */
 #define CFG_SDRAM_SIZE_PER_BANK 0x04000000 /* 64MB */
 #define CFG_SDRAM_BANKS	        2
@@ -169,23 +119,6 @@
 #define CFG_SDRAM_tRFC		66	/* Auto refresh period */
 
 /*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START  0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END	   0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-/*
  * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
  * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
  * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
@@ -198,35 +131,13 @@
 #undef  CFG_EXT_SERIAL_CLOCK           /* external serial clock */
 #undef  CFG_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
 #define CFG_BASE_BAUD		691200
-
-#define CONFIG_BAUDRATE		115200
-
 #define CONFIG_UART1_CONSOLE	1
 
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE  \
-    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-#define CFG_LOAD_ADDR	    0x100000	/* default load address */
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_LOOPW            1       /* enable loopw command         */
-#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
-
 /*-----------------------------------------------------------------------
  * I2C stuff
  *-----------------------------------------------------------------------
  */
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
-#undef  CONFIG_SOFT_I2C			/* I2C bit-banged		*/
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
 
 #define CFG_I2C_NOPROBES	{ 0x69 } /* avoid iprobe hangup (why?) */
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	6 /* 24C02 requires 5ms delay */
@@ -278,25 +189,12 @@ unsigned char spi_read(void);
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
 #define CFG_FLASH_BASE		0xFFE00000
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
-#define CFG_MONITOR_BASE	(-CFG_MONITOR_LEN)
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-
 #define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
 #define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
 
@@ -421,21 +319,5 @@ unsigned char spi_read(void);
 
 #define CPLD_REG0_ADDR	0x50100000
 #define CPLD_REG1_ADDR	0x50100001
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM	0x02		/* Software reboot */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/taishan.h b/include/configs/taishan.h
index 1879d38..ba42192 100644
--- a/include/configs/taishan.h
+++ b/include/configs/taishan.h
@@ -32,9 +32,15 @@
 #define CONFIG_440GX		1	/* Specifc GX support		*/
 #define CONFIG_440		1	/* ... PPC440 family		*/
 #define CONFIG_4xx		1	/* ... PPC4xx family		*/
-#undef	CFG_DRAM_TEST			/* Disable-takes long time!	*/
 #define CONFIG_SYS_CLK_FREQ	33333333 /* external freq to pll	*/
 
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		taishan
+#define CONFIG_USE_TTY		ttyS1
+#include "amcc-common.h"
+
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_pre_init		*/
 #define CONFIG_MISC_INIT_R	1	/* Call misc_init_r		*/
 
@@ -42,9 +48,7 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
 #define CFG_FLASH_BASE		0xfc000000	/* start of FLASH	*/
-#define CFG_MONITOR_BASE	0xfffc0000	/* start of monitor	*/
 #define CFG_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
 #define CFG_PERIPHERAL_BASE	0xe0000000	/* internal peripherals	*/
 #define CFG_ISRAM_BASE		0xc0000000	/* internal SRAM	*/
@@ -70,19 +74,11 @@
 #define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 0x4)
 #define CFG_INIT_SP_OFFSET	CFG_POST_WORD_ADDR
 
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon*/
-#define CFG_MALLOC_LEN		(1024 * 1024)	/* Reserve 1024 kB for malloc*/
-
 /*-----------------------------------------------------------------------
  * Serial Port
  *----------------------------------------------------------------------*/
 #define CONFIG_UART1_CONSOLE	1	/* use of UART1 as console	*/
-#define CONFIG_SERIAL_MULTI     1	/* enable serial multi support	*/
 #define CFG_EXT_SERIAL_CLOCK	(1843200 * 6)	/* Ext clk @ 11.059 MHz */
-#define CONFIG_BAUDRATE		115200
-
-#define CFG_BAUDRATE_TABLE  \
-    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 
 /*-----------------------------------------------------------------------
  * Environment
@@ -138,10 +134,7 @@
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
-#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
 
 #undef CFG_I2C_MULTI_EEPROMS
 #define CFG_I2C_EEPROM_ADDR	0x50
@@ -159,65 +152,23 @@
 #define CFG_DTT_LOW_TEMP	-30
 #define CFG_DTT_HYSTERESIS	3
 
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
+/*
+ * Default environment variables
+ */
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"hostname=taishan\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
-	        "bootm\0"						\
-	"rootpath=/opt/eldk/ppc_4xx\0"					\
-	"bootfile=/tftpboot/taishan/uImage\0"				\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
 	"kernel_addr=fc000000\0"					\
 	"ramdisk_addr=fc180000\0"					\
-	"initrd_high=30000000\0"					\
-	"load=tftp 100000 /tftpboot/taishan/u-boot.bin\0"		\
-	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
-		"cp.b 100000 fffc0000 40000;"			        \
-		"setenv filesize;saveenv\0"				\
-	"upd=run load update\0"						\
-	"fixedip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
-	"$(gatewayip):$(netmask):$(hostname):$(netdev):off panic=1\0"	\
-	"dhcp=setenv bootargs $(bootargs) ip=dhcp\0"			\
 	"kozio=bootm 0xffe00000\0"					\
 	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define CONFIG_BAUDRATE		115200
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
 /*-----------------------------------------------------------------------
  * Networking
  *----------------------------------------------------------------------*/
 #define CONFIG_EMAC_NR_START	2	/* start with EMAC 2 (skip 0&1)	*/
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_NET_MULTI	1
 #define CONFIG_PHY_ADDR		0xff	     /* no phy on EMAC0		*/
 #define CONFIG_PHY1_ADDR	0xff	     /* no phy on EMAC1		*/
 #define CONFIG_PHY2_ADDR	0x1
@@ -230,70 +181,12 @@
 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
 #define CONFIG_PHY_RESET        1       /* reset phy upon startup         */
 #define CONFIG_PHY_RESET_DELAY	1000
-#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
 
 /*
- * Command line configuration.
+ * Commands additional to the ones defined in amcc-common.h
  */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
 #define CONFIG_CMD_DTT
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- *----------------------------------------------------------------------*/
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	        16	/* max number of command args	*/
-#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000 /* memtest works on		*/
-#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR		0x100000  /* default load address	*/
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-
-#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks	*/
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_LOOPW            1       /* enable loopw command         */
-#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -312,28 +205,4 @@
 #define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
 #define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
 
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/walnut.h b/include/configs/walnut.h
index adc420b..e19c5f3 100644
--- a/include/configs/walnut.h
+++ b/include/configs/walnut.h
@@ -38,122 +38,44 @@
 #define CONFIG_WALNUT		1	/* ...on a WALNUT board		*/
 					/* ...and on a SYCAMORE board	*/
 
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		walnut
+#include "amcc-common.h"
+
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
 
 #define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll	*/
 
-#define CONFIG_PREBOOT	"echo;" \
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"hostname=walnut\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"	\
-		"bootm\0"						\
-	"rootpath=/opt/eldk/ppc_4xx\0"					\
-	"bootfile=/tftpboot/walnut/uImage\0"				\
+/*
+ * Default environment variables
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
 	"kernel_addr=fff80000\0"					\
 	"ramdisk_addr=fff80000\0"					\
-	"initrd_high=30000000\0"					\
-	"load=tftp 100000 /tftpboot/walnut/u-boot.bin\0"		\
-	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
-		"cp.b 100000 fffc0000 40000;"				\
-		"setenv filesize;saveenv\0"				\
-	"upd=run load update\0"						\
 	""
-#define CONFIG_BOOTCOMMAND	"run net_nfs"
-
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define CONFIG_BAUDRATE		115200
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
-#define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		1	/* PHY address			*/
-
-#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
 #define CONFIG_HAS_ETH0		1
 
-#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
-#define CONFIG_NET_MULTI		/* needed for NetConsole	*/
-
 #define CONFIG_RTC_DS174x	1	/* use DS1743 RTC in Walnut	*/
 
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
 /*
- * Command line configuration.
+ * Commands additional to the ones defined in amcc-common.h
  */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_SNTP
 
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
 #define CONFIG_SPD_EEPROM      1       /* use SPD EEPROM for setup    */
 
 /*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-/*
  * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
  * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
  * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
@@ -167,29 +89,11 @@
 #undef	CFG_405_UART_ERRATA_59	       /* 405GP/CR Rev. D silicon */
 #define CFG_BASE_BAUD	    691200
 
-/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE  \
-    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_LOOPW		1	/* enable loopw command		*/
-#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-
 /*-----------------------------------------------------------------------
  * I2C stuff
  *-----------------------------------------------------------------------
  */
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
-#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
 
 #define CFG_I2C_MULTI_EEPROMS
 #define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
@@ -224,13 +128,8 @@
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
  */
-#define CFG_SDRAM_BASE		0x00000000
 #define CFG_FLASH_BASE		0xFFF80000
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
-#define CFG_MONITOR_BASE	(-CFG_MONITOR_LEN)
 
 /*
  * Define here the location of the environment variables (FLASH or NVRAM).
@@ -243,13 +142,6 @@
 #define CFG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
 #endif
 
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
@@ -335,21 +227,4 @@
  */
 #define SPD_EEPROM_ADDRESS	0x50
 
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h
index f22e798..891b515 100644
--- a/include/configs/yosemite.h
+++ b/include/configs/yosemite.h
@@ -42,6 +42,11 @@
 #define CONFIG_4xx		1	/* ... PPC4xx family		*/
 #define CONFIG_SYS_CLK_FREQ	66666666    /* external freq to pll	*/
 
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#include "amcc-common.h"
+
 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f	*/
 #define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
 #define CONFIG_BOARD_RESET	1	/* call board_reset()		*/
@@ -50,10 +55,6 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
-#define CFG_MONITOR_BASE	(-CFG_MONITOR_LEN)
-#define CFG_SDRAM_BASE	        0x00000000	    /* _must_ be 0	*/
 #define CFG_FLASH_BASE	        0xfc000000	    /* start of FLASH	*/
 #define CFG_PCI_MEMBASE	        0xa0000000	    /* mapped pci memory*/
 #define CFG_PCI_MEMBASE1        CFG_PCI_MEMBASE  + 0x10000000
@@ -84,14 +85,9 @@
  * Serial Port
  *----------------------------------------------------------------------*/
 #define CFG_EXT_SERIAL_CLOCK	11059200 /* use external 11.059MHz clk	*/
-#define CONFIG_BAUDRATE		115200
-#define CONFIG_SERIAL_MULTI     1
 /*define this if you want console on UART1*/
 #undef CONFIG_UART1_CONSOLE
 
-#define CFG_BAUDRATE_TABLE  \
-    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
 /*-----------------------------------------------------------------------
  * Environment
  *----------------------------------------------------------------------*/
@@ -142,10 +138,7 @@
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C		1	    /* I2C with hardware support	*/
-#undef	CONFIG_SOFT_I2C			    /* I2C bit-banged		*/
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
 
 #define CFG_I2C_MULTI_EEPROMS
 #define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
@@ -167,72 +160,22 @@
 #define CFG_DTT_LOW_TEMP	-30
 #define CFG_DTT_HYSTERESIS	3
 
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
-/* Setup some board specific values for the default environment variables */
-#ifndef CONFIG_YELLOWSTONE
-#define CONFIG_HOSTNAME		yosemite
-#define CFG_BOOTFILE		"bootfile=/tftpboot/yosemite/uImage\0"
-#define CFG_ROOTPATH		"rootpath=/opt/eldk/ppc_4xxFP\0"
-#else
-#define CONFIG_HOSTNAME		yellowstone
-#define CFG_BOOTFILE		"bootfile=/tftpboot/yellowstone/uImage\0"
-#define CFG_ROOTPATH		"rootpath=/opt/eldk/ppc_4xx\0"
-#endif
-
+/*
+ * Default environment variables
+ */
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
-	CFG_BOOTFILE							\
-	CFG_ROOTPATH							\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
-	        "bootm\0"						\
-	"bootfile=/tftpboot/${hostname}/uImage\0"			\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
 	"kernel_addr=fc000000\0"					\
 	"ramdisk_addr=fc180000\0"					\
-	"load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0"		\
-	"update=protect off fff80000 ffffffff;era fff80000 ffffffff;"	\
-		"cp.b 200000 fff80000 80000;"			        \
-		"setenv filesize;saveenv\0"				\
-	"upd=run load update\0"						\
 	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define CONFIG_BAUDRATE		115200
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_NET_MULTI        1	/* required for netconsole      */
-#define CONFIG_PHY1_ADDR        3
 #define CONFIG_HAS_ETH0		1	/* add support for "ethaddr"	*/
 #define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
 #define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
-
-#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
+#define CONFIG_PHY1_ADDR        3
 
 /* Partitions */
 #define CONFIG_MAC_PARTITION
@@ -263,36 +206,11 @@
 #define CONFIG_HW_WATCHDOG			/* watchdog */
 #endif
 
-
 /*
- * BOOTP options
+ * Commands additional to the ones defined in amcc-common.h
  */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
 #define CONFIG_CMD_DTT
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SDRAM
 
 #ifdef CONFIG_440EP
     #define CONFIG_CMD_USB
@@ -300,36 +218,6 @@
     #define CONFIG_CMD_EXT2
 #endif
 
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	        16	/* max number of command args	*/
-#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000 /* memtest works on	        */
-#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
-
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
-#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-#define CONFIG_LYNXKDI          1       /* support kdi files            */
-
-#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_LOOPW            1       /* enable loopw command         */
-#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-
 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------
@@ -347,13 +235,6 @@
 #define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
 #define CFG_PCI_SUBSYS_ID       0xcafe	/* Whatever */
 
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  *----------------------------------------------------------------------*/
@@ -370,21 +251,4 @@
 
 #define CFG_BCSR5_PCI66EN	0x80
 
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/yucca.h b/include/configs/yucca.h
index 6f9d3e3..026fef6 100644
--- a/include/configs/yucca.h
+++ b/include/configs/yucca.h
@@ -38,13 +38,18 @@
 #define CONFIG_440			1	/* ... PPC440 family	*/
 #define CONFIG_440SPE			1	/* Specifc SPe support	*/
 #define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init	*/
-#undef	CFG_DRAM_TEST				/* Disable-takes long time */
 #define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll	*/
 #define EXTCLK_33_33		33333333
 #define EXTCLK_66_66		66666666
 #define EXTCLK_50		50000000
 #define EXTCLK_83		83333333
 
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		yucca
+#include "amcc-common.h"
+
 #define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/
 #undef  CONFIG_SHOW_BOOT_PROGRESS
 #undef  CONFIG_STRESS
@@ -53,9 +58,7 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
 #define CFG_FLASH_BASE		0xfff00000	/* start of FLASH	*/
-#define CFG_MONITOR_BASE	0xfffb0000	/* start of monitor	*/
 #define CFG_PERIPHERAL_BASE	0xa0000000	/* internal peripherals	*/
 #define CFG_ISRAM_BASE		0x90000000	/* internal SRAM	*/
 
@@ -99,24 +102,15 @@
 #define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 0x4)
 #define CFG_INIT_SP_OFFSET	CFG_POST_WORD_ADDR
 
-#define CFG_MONITOR_LEN		(320 * 1024)	/* Reserve 320 kB for Mon */
-#define CFG_MALLOC_LEN		(512 * 1024)	/* Reserve 512 kB for malloc */
-
 /*-----------------------------------------------------------------------
  * Serial Port
  *----------------------------------------------------------------------*/
-#define CONFIG_SERIAL_MULTI	1
 #undef CONFIG_UART1_CONSOLE
 
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
 #undef CFG_EXT_SERIAL_CLOCK
 /* #define CFG_EXT_SERIAL_CLOCK	(1843200 * 6) */ /* Ext clk @ 11.059 MHz */
 
-#define CONFIG_BAUDRATE		115200
-
-#define CFG_BAUDRATE_TABLE  \
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
 /*-----------------------------------------------------------------------
  * DDR SDRAM
  *----------------------------------------------------------------------*/
@@ -127,10 +121,7 @@
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
-#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
 
 #define IIC0_BOOTPROM_ADDR	0x50
 #define IIC0_ALT_BOOTPROM_ADDR	0x54
@@ -153,123 +144,32 @@
 #undef	CFG_ENV_IS_IN_EEPROM		/* ... not in EEPROM		*/
 #define CONFIG_ENV_OVERWRITE	1
 
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS
-
+/*
+ * Default environment variables
+ */
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"hostname=yucca\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
-		"bootm\0"						\
-	"rootpath=/opt/eldk/ppc_4xx\0"					\
-	"bootfile=yucca/uImage\0"					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_PPC						\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
 	"kernel_addr=E7F10000\0"					\
 	"ramdisk_addr=E7F20000\0"					\
-	"initrd_high=30000000\0"					\
-	"load=tftp 100000 yuca/u-boot.bin\0"				\
-	"update=protect off 2:4-7;era 2:4-7;"				\
-		"cp.b ${fileaddr} FFFB0000 ${filesize};"		\
-		"setenv filesize;saveenv\0"				\
-	"upd=run load update\0"						\
 	"pciconfighost=1\0"						\
 	"pcie_mode=RP:EP:EP\0"						\
 	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
 
 /*
- * BOOTP options
+ * Commands additional to the ones defined in amcc-common.h
  */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_SDRAM
 
-
 #define	CONFIG_IBM_EMAC4_V4	1
-#define CONFIG_MII		1	/* MII PHY management		*/
-#undef CONFIG_NET_MULTI
 #define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
 #define CONFIG_HAS_ETH0
 #define CONFIG_PHY_RESET        1	/* reset phy upon startup	*/
 #define CONFIG_PHY_RESET_DELAY	1000
 #define CONFIG_CIS8201_PHY	1	/* Enable 'special' RGMII mode for Cicada phy */
 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
-#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
-#define CONFIG_NET_MULTI		/* needed for NetConsole	*/
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP				/* undef to save memory		*/
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
-
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
-#else
-#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CFG_MEMTEST_START	0x0400000	/* memtest works on		*/
-#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM		*/
-
-#define CFG_LOAD_ADDR		0x100000	/* default load address		*/
-#define CFG_EXTBDINFO		1		/* To use extended board_into (bd_t) */
-
-#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_LOOPW            1       /* enable loopw command         */
-#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
 /*-----------------------------------------------------------------------
  * FLASH related
@@ -318,26 +218,6 @@
 /* Support for Intel 82557/82559/82559ER chips. */
 #define CONFIG_EEPRO100
 
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20)	/*Initial Memory map for Linux*/
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM	0x02		/* Software reboot */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-
 /* FB Divisor selection */
 #define FPGA_FB_DIV_6		6
 #define FPGA_FB_DIV_10		10
@@ -539,10 +419,4 @@
 #define PERIOD_33_33MHZ		30000	/* 30ns */
 #define PERIOD_25_00MHZ		40000	/* 40ns */
 
-/*---------------------------------------------------------------------------*/
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-
 #endif	/* __CONFIG_H */
diff --git a/include/ppc405.h b/include/ppc405.h
index d953378..2231a5f 100644
--- a/include/ppc405.h
+++ b/include/ppc405.h
@@ -22,6 +22,10 @@
 #ifndef	__PPC405_H__
 #define __PPC405_H__
 
+/* Define bits and masks for real-mode storage attribute control registers */
+#define PPC_128MB_SACR_BIT(addr)	((addr) >> 27)
+#define PPC_128MB_SACR_VALUE(addr)	PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1)
+
 #ifndef CONFIG_IOP480
 #define CFG_DCACHE_SIZE		(16 << 10)	/* For AMCC 405 CPUs	*/
 #else
@@ -363,31 +367,118 @@
 #endif	/* defined(CONFIG_405EZ) */
 
 /******************************************************************************
- * SDRAM Controller
- ******************************************************************************/
-  /* values for memcfga register - indirect addressing of these regs */
-#ifndef CONFIG_405EP
-  #define mem_besra   0x00    /* bus error syndrome reg a	     */
-  #define mem_besrsa  0x04    /* bus error syndrome reg set a	     */
-  #define mem_besrb   0x08    /* bus error syndrome reg b	     */
-  #define mem_besrsb  0x0c    /* bus error syndrome reg set b	     */
-  #define mem_bear    0x10    /* bus error address reg		     */
-#endif
-  #define mem_mcopt1  0x20    /* memory controller options 1	     */
-  #define mem_status  0x24    /* memory status			     */
-  #define mem_rtr     0x30    /* refresh timer reg		     */
-  #define mem_pmit    0x34    /* power management idle timer	     */
-  #define mem_mb0cf   0x40    /* memory bank 0 configuration	     */
-  #define mem_mb1cf   0x44    /* memory bank 1 configuration	     */
-#ifndef CONFIG_405EP
-  #define mem_mb2cf   0x48    /* memory bank 2 configuration	     */
-  #define mem_mb3cf   0x4c    /* memory bank 3 configuration	     */
-#endif
-  #define mem_sdtr1   0x80    /* timing reg 1			     */
-#ifndef CONFIG_405EP
-  #define mem_ecccf   0x94    /* ECC configuration		     */
-  #define mem_eccerr  0x98    /* ECC error status		     */
-#endif
+ * External Bus Controller (EBC)
+ *****************************************************************************/
+
+/* Bank Configuration Register */
+#define	EBC_BXCR_BAS_MASK	PPC_REG_VAL(11, 0xFFF)
+#define EBC_BXCR_BAS_ENCODE(n)	(((static_cast(unsigned long, n)) & \
+				  EBC_BXCR_BAS_MASK) << 0)
+#define EBC_BXCR_BS_MASK	PPC_REG_VAL(14, 0x7)
+#define EBC_BXCR_BS_1MB		PPC_REG_VAL(14, 0x0)
+#define EBC_BXCR_BS_2MB		PPC_REG_VAL(14, 0x1)
+#define EBC_BXCR_BS_4MB		PPC_REG_VAL(14, 0x2)
+#define EBC_BXCR_BS_8MB		PPC_REG_VAL(14, 0x3)
+#define EBC_BXCR_BS_16MB	PPC_REG_VAL(14, 0x4)
+#define EBC_BXCR_BS_32MB	PPC_REG_VAL(14, 0x5)
+#define EBC_BXCR_BS_64MB	PPC_REG_VAL(14, 0x6)
+#define EBC_BXCR_BS_128MB	PPC_REG_VAL(14, 0x7)
+#define EBC_BXCR_BU_MASK	PPC_REG_VAL(16, 0x3)
+#define	EBC_BXCR_BU_NONE	PPC_REG_VAL(16, 0x0)
+#define EBC_BXCR_BU_R		PPC_REG_VAL(16, 0x1)
+#define EBC_BXCR_BU_W		PPC_REG_VAL(16, 0x2)
+#define EBC_BXCR_BU_RW		PPC_REG_VAL(16, 0x3)
+#define EBC_BXCR_BW_MASK	PPC_REG_VAL(18, 0x3)
+#define EBC_BXCR_BW_8BIT	PPC_REG_VAL(18, 0x0)
+#define EBC_BXCR_BW_16BIT	PPC_REG_VAL(18, 0x1)
+#define EBC_BXCR_BW_32BIT	PPC_REG_VAL(18, 0x3)
+
+/* Bank Access Parameter Register */
+#define EBC_BXAP_BME_ENABLED	PPC_REG_VAL(0, 0x1)
+#define EBC_BXAP_BME_DISABLED	PPC_REG_VAL(0, 0x0)
+#define EBC_BXAP_TWT_ENCODE(n)	PPC_REG_VAL(8, \
+					    (static_cast(unsigned long, n)) \
+					    & 0xFF)
+#define	EBC_BXAP_FWT_ENCODE(n)	PPC_REG_VAL(5, \
+					    (static_cast(unsigned long, n)) \
+					    & 0x1F)
+#define	EBC_BXAP_BWT_ENCODE(n)	PPC_REG_VAL(8, \
+					    (static_cast(unsigned long, n)) \
+					    & 0x7)
+#define EBC_BXAP_BCE_DISABLE	PPC_REG_VAL(9, 0x0)
+#define EBC_BXAP_BCE_ENABLE	PPC_REG_VAL(9, 0x1)
+#define EBC_BXAP_BCT_MASK	PPC_REG_VAL(11, 0x3)
+#define EBC_BXAP_BCT_2TRANS	PPC_REG_VAL(11, 0x0)
+#define EBC_BXAP_BCT_4TRANS	PPC_REG_VAL(11, 0x1)
+#define EBC_BXAP_BCT_8TRANS	PPC_REG_VAL(11, 0x2)
+#define EBC_BXAP_BCT_16TRANS	PPC_REG_VAL(11, 0x3)
+#define EBC_BXAP_CSN_ENCODE(n)	PPC_REG_VAL(13, \
+					    (static_cast(unsigned long, n)) \
+					    & 0x3)
+#define EBC_BXAP_OEN_ENCODE(n)	PPC_REG_VAL(15, \
+					    (static_cast(unsigned long, n)) \
+					    & 0x3)
+#define EBC_BXAP_WBN_ENCODE(n)	PPC_REG_VAL(17, \
+					    (static_cast(unsigned long, n)) \
+					    & 0x3)
+#define EBC_BXAP_WBF_ENCODE(n)	PPC_REG_VAL(19, \
+					    (static_cast(unsigned long, n)) \
+					    & 0x3)
+#define EBC_BXAP_TH_ENCODE(n)	PPC_REG_VAL(22, \
+					    (static_cast(unsigned long, n)) \
+					    & 0x7)
+#define EBC_BXAP_RE_ENABLED	PPC_REG_VAL(23, 0x1)
+#define EBC_BXAP_RE_DISABLED	PPC_REG_VAL(23, 0x0)
+#define EBC_BXAP_SOR_DELAYED	PPC_REG_VAL(24, 0x0)
+#define EBC_BXAP_SOR_NONDELAYED	PPC_REG_VAL(24, 0x1)
+#define EBC_BXAP_BEM_WRITEONLY	PPC_REG_VAL(25, 0x0)
+#define EBC_BXAP_BEM_RW		PPC_REG_VAL(25, 0x1)
+#define EBC_BXAP_PEN_DISABLED	PPC_REG_VAL(26, 0x0)
+#define EBC_BXAP_PEN_ENABLED	PPC_REG_VAL(26, 0x1)
+
+/* Configuration Register */
+#define EBC_CFG_LE_MASK		PPC_REG_VAL(0, 0x1)
+#define EBC_CFG_LE_UNLOCK	PPC_REG_VAL(0, 0x0)
+#define EBC_CFG_LE_LOCK		PPC_REG_VAL(0, 0x1)
+#define EBC_CFG_PTD_MASK	PPC_REG_VAL(1, 0x1)
+#define EBC_CFG_PTD_ENABLE	PPC_REG_VAL(1, 0x0)
+#define EBC_CFG_PTD_DISABLE	PPC_REG_VAL(1, 0x1)
+#define EBC_CFG_RTC_MASK	PPC_REG_VAL(4, 0x7)
+#define EBC_CFG_RTC_16PERCLK	PPC_REG_VAL(4, 0x0)
+#define EBC_CFG_RTC_32PERCLK	PPC_REG_VAL(4, 0x1)
+#define EBC_CFG_RTC_64PERCLK	PPC_REG_VAL(4, 0x2)
+#define EBC_CFG_RTC_128PERCLK	PPC_REG_VAL(4, 0x3)
+#define EBC_CFG_RTC_256PERCLK	PPC_REG_VAL(4, 0x4)
+#define EBC_CFG_RTC_512PERCLK	PPC_REG_VAL(4, 0x5)
+#define EBC_CFG_RTC_1024PERCLK	PPC_REG_VAL(4, 0x6)
+#define EBC_CFG_RTC_2048PERCLK	PPC_REG_VAL(4, 0x7)
+#define EBC_CFG_ATC_MASK	PPC_REG_VAL(5, 0x1)
+#define EBC_CFG_ATC_HI		PPC_REG_VAL(5, 0x0)
+#define EBC_CFG_ATC_PREVIOUS	PPC_REG_VAL(5, 0x1)
+#define EBC_CFG_DTC_MASK	PPC_REG_VAL(6, 0x1)
+#define EBC_CFG_DTC_HI		PPC_REG_VAL(6, 0x0)
+#define EBC_CFG_DTC_PREVIOUS	PPC_REG_VAL(6, 0x1)
+#define EBC_CFG_CTC_MASK	PPC_REG_VAL(7, 0x1)
+#define EBC_CFG_CTC_HI		PPC_REG_VAL(7, 0x0)
+#define EBC_CFG_CTC_PREVIOUS	PPC_REG_VAL(7, 0x1)
+#define EBC_CFG_OEO_MASK	PPC_REG_VAL(8, 0x1)
+#define EBC_CFG_OEO_DISABLE	PPC_REG_VAL(8, 0x0)
+#define EBC_CFG_OEO_ENABLE	PPC_REG_VAL(8, 0x1)
+#define EBC_CFG_EMC_MASK	PPC_REG_VAL(9, 0x1)
+#define EBC_CFG_EMC_NONDEFAULT	PPC_REG_VAL(9, 0x0)
+#define EBC_CFG_EMC_DEFAULT	PPC_REG_VAL(9, 0x1)
+#define EBC_CFG_PME_MASK	PPC_REG_VAL(14, 0x1)
+#define EBC_CFG_PME_DISABLE	PPC_REG_VAL(14, 0x0)
+#define EBC_CFG_PME_ENABLE	PPC_REG_VAL(14, 0x1)
+#define EBC_CFG_PMT_MASK	PPC_REG_VAL(19, 0x1F)
+#define EBC_CFG_PMT_ENCODE(n)	PPC_REG_VAL(19, \
+					    (static_cast(unsigned long, n)) \
+					    & 0x1F)
+#define EBC_CFG_PR_MASK		PPC_REG_VAL(21, 0x3)
+#define EBC_CFG_PR_16		PPC_REG_VAL(21, 0x0)
+#define EBC_CFG_PR_32		PPC_REG_VAL(21, 0x1)
+#define EBC_CFG_PR_64		PPC_REG_VAL(21, 0x2)
+#define EBC_CFG_PR_128		PPC_REG_VAL(21, 0x3)
 
 #ifndef CONFIG_405EP
 /******************************************************************************
@@ -1163,369 +1254,6 @@
 #if defined(CONFIG_405EX)
 #define SDR0_SRST		0x0200
 
-#define SDRAM_BESR0	0x00
-#define SDRAM_BEARL	0x02
-#define SDRAM_BEARU	0x03
-#define SDRAM_WMIRQ	0x06	/**/
-#define SDRAM_PLBOPT	0x08	/**/
-#define SDRAM_PUABA	0x09	/**/
-#define SDRAM_MCSTAT	0x1F	/* memory controller status	      */
-#define SDRAM_MCOPT1	0x20	/* memory controller options 1	      */
-#define SDRAM_MCOPT2	0x21	/* memory controller options 2	      */
-#define SDRAM_MODT0	0x22	/* on die termination for bank 0      */
-#define SDRAM_MODT1	0x23	/* on die termination for bank 1      */
-#define SDRAM_MODT2	0x24	/* on die termination for bank 2      */
-#define SDRAM_MODT3	0x25	/* on die termination for bank 3      */
-#define SDRAM_CODT	0x26	/* on die termination for controller  */
-#define SDRAM_VVPR	0x27	/* variable VRef programmming	      */
-#define SDRAM_OPARS	0x28	/* on chip driver control setup       */
-#define SDRAM_OPART	0x29	/* on chip driver control trigger     */
-#define SDRAM_RTR	0x30	/* refresh timer		      */
-#define SDRAM_PMIT	0x34	/* power management idle timer	      */
-#define SDRAM_MB0CF	0x40	/* memory bank 0 configuration	      */
-#define SDRAM_MB1CF	0x44	/* memory bank 1 configuration	      */
-#define SDRAM_MB2CF	0x48	/* memory bank 2 configuration	      */
-#define SDRAM_MB3CF	0x4C	/* memory bank 3 configuration	      */
-#define SDRAM_INITPLR0	0x50	/* manual initialization control      */
-#define SDRAM_INITPLR1	0x51	/* manual initialization control      */
-#define SDRAM_INITPLR2	0x52	/* manual initialization control      */
-#define SDRAM_INITPLR3	0x53	/* manual initialization control      */
-#define SDRAM_INITPLR4	0x54	/* manual initialization control      */
-#define SDRAM_INITPLR5	0x55	/* manual initialization control      */
-#define SDRAM_INITPLR6	0x56	/* manual initialization control      */
-#define SDRAM_INITPLR7	0x57	/* manual initialization control      */
-#define SDRAM_INITPLR8	0x58	/* manual initialization control      */
-#define SDRAM_INITPLR9	0x59	/* manual initialization control      */
-#define SDRAM_INITPLR10 0x5a	/* manual initialization control      */
-#define SDRAM_INITPLR11 0x5b	/* manual initialization control      */
-#define SDRAM_INITPLR12 0x5c	/* manual initialization control      */
-#define SDRAM_INITPLR13 0x5d	/* manual initialization control      */
-#define SDRAM_INITPLR14 0x5e	/* manual initialization control      */
-#define SDRAM_INITPLR15 0x5f	/* manual initialization control      */
-#define SDRAM_RQDC	0x70	/* read DQS delay control	      */
-#define SDRAM_RFDC	0x74	/* read feedback delay control	      */
-#define SDRAM_RDCC	0x78	/* read data capture control	      */
-#define SDRAM_DLCR	0x7A	/* delay line calibration	      */
-#define SDRAM_CLKTR	0x80	/* DDR clock timing		      */
-#define SDRAM_WRDTR	0x81	/* write data, DQS, DM clock, timing  */
-#define SDRAM_SDTR1	0x85	/* DDR SDRAM timing 1		      */
-#define SDRAM_SDTR2	0x86	/* DDR SDRAM timing 2		      */
-#define SDRAM_SDTR3	0x87	/* DDR SDRAM timing 3		      */
-#define SDRAM_MMODE	0x88	/* memory mode			      */
-#define SDRAM_MEMODE	0x89	/* memory extended mode		      */
-#define SDRAM_ECCCR	0x98	/* ECC error status		      */
-#define SDRAM_RID	0xF8	/* revision ID			      */
-
-/*-----------------------------------------------------------------------------+
-|  Memory Bank 0-7 configuration
-+-----------------------------------------------------------------------------*/
-#define SDRAM_RXBAS_SDSZ_4	   0x00000000	   /*	4M		      */
-#define SDRAM_RXBAS_SDSZ_8	   0x00001000	   /*	8M		      */
-#define SDRAM_RXBAS_SDSZ_16	   0x00002000	   /*  16M		      */
-#define SDRAM_RXBAS_SDSZ_32	   0x00003000	   /*  32M		      */
-#define SDRAM_RXBAS_SDSZ_64	   0x00004000	   /*  64M		      */
-#define SDRAM_RXBAS_SDSZ_128	   0x00005000	   /* 128M		      */
-#define SDRAM_RXBAS_SDSZ_256	   0x00006000	   /* 256M		      */
-#define SDRAM_RXBAS_SDSZ_512	   0x00007000	   /* 512M		      */
-#define SDRAM_RXBAS_SDSZ_1024	   0x00008000	   /* 1024M		      */
-#define SDRAM_RXBAS_SDSZ_2048	   0x00009000	   /* 2048M		      */
-#define SDRAM_RXBAS_SDSZ_4096	   0x0000a000	   /* 4096M		      */
-#define SDRAM_RXBAS_SDSZ_8192	   0x0000b000	   /* 8192M		      */
-
-/*-----------------------------------------------------------------------------+
-|  Memory Controller Status
-+-----------------------------------------------------------------------------*/
-#define SDRAM_MCSTAT_MIC_MASK	    0x80000000	/* Memory init status mask    */
-#define   SDRAM_MCSTAT_MIC_NOTCOMP  0x00000000	/* Mem init not complete      */
-#define   SDRAM_MCSTAT_MIC_COMP     0x80000000	/* Mem init complete	      */
-#define SDRAM_MCSTAT_SRMS_MASK	    0x80000000	/* Mem self refresh stat mask */
-#define   SDRAM_MCSTAT_SRMS_NOT_SF  0x00000000	/* Mem not in self refresh    */
-#define   SDRAM_MCSTAT_SRMS_SF	    0x80000000	/* Mem in self refresh	      */
-
-/*-----------------------------------------------------------------------------+
-|  Memory Controller Options 1
-+-----------------------------------------------------------------------------*/
-#define SDRAM_MCOPT1_MCHK_MASK	     0x30000000 /* Memory data err check mask */
-#define   SDRAM_MCOPT1_MCHK_NON      0x00000000 /* No ECC generation	      */
-#define   SDRAM_MCOPT1_MCHK_GEN      0x20000000 /* ECC generation	      */
-#define   SDRAM_MCOPT1_MCHK_CHK      0x10000000 /* ECC generation and check   */
-#define   SDRAM_MCOPT1_MCHK_CHK_REP  0x30000000 /* ECC generation, chk, report*/
-#define   SDRAM_MCOPT1_MCHK_CHK_DECODE(n)  ((((unsigned long)(n))>>28)&0x3)
-#define SDRAM_MCOPT1_RDEN_MASK	     0x08000000 /* Registered DIMM mask       */
-#define   SDRAM_MCOPT1_RDEN	     0x08000000 /* Registered DIMM enable     */
-#define SDRAM_MCOPT1_PMU_MASK	     0x06000000 /* Page management unit mask  */
-#define   SDRAM_MCOPT1_PMU_CLOSE     0x00000000 /* PMU Close		      */
-#define   SDRAM_MCOPT1_PMU_OPEN      0x04000000 /* PMU Open		      */
-#define   SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose	      */
-#define SDRAM_MCOPT1_DMWD_MASK	     0x01000000 /* DRAM width mask	      */
-#define   SDRAM_MCOPT1_DMWD_32	     0x00000000 /* 32 bits		      */
-#define   SDRAM_MCOPT1_DMWD_64	     0x01000000 /* 64 bits		      */
-#define SDRAM_MCOPT1_UIOS_MASK	     0x00C00000 /* Unused IO State	      */
-#define SDRAM_MCOPT1_BCNT_MASK	     0x00200000 /* Bank count		      */
-#define   SDRAM_MCOPT1_4_BANKS	     0x00000000 /* 4 Banks		      */
-#define   SDRAM_MCOPT1_8_BANKS	     0x00200000 /* 8 Banks		      */
-#define SDRAM_MCOPT1_DDR_TYPE_MASK   0x00100000 /* DDR Memory Type mask       */
-#define   SDRAM_MCOPT1_DDR1_TYPE     0x00000000 /* DDR1 Memory Type	      */
-#define   SDRAM_MCOPT1_DDR2_TYPE     0x00100000 /* DDR2 Memory Type	      */
-#define   SDRAM_MCOPT1_QDEP	     0x00020000 /* 4 commands deep	      */
-#define SDRAM_MCOPT1_RWOO_MASK	     0x00008000 /* Out of Order Read mask     */
-#define   SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled		      */
-#define   SDRAM_MCOPT1_RWOO_ENABLED  0x00008000 /* enabled		      */
-#define SDRAM_MCOPT1_WOOO_MASK	     0x00004000 /* Out of Order Write mask    */
-#define   SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled		      */
-#define   SDRAM_MCOPT1_WOOO_ENABLED  0x00004000 /* enabled		      */
-#define SDRAM_MCOPT1_DCOO_MASK	     0x00002000 /* All Out of Order mask      */
-#define   SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled		      */
-#define   SDRAM_MCOPT1_DCOO_ENABLED  0x00000000 /* enabled		      */
-#define SDRAM_MCOPT1_DREF_MASK	     0x00001000 /* Deferred refresh mask      */
-#define   SDRAM_MCOPT1_DREF_NORMAL   0x00000000 /* normal refresh	      */
-#define   SDRAM_MCOPT1_DREF_DEFER_4  0x00001000 /* defer up to 4 refresh cmd  */
-
-/*-----------------------------------------------------------------------------+
-|  Memory Controller Options 2
-+-----------------------------------------------------------------------------*/
-#define SDRAM_MCOPT2_SREN_MASK	      0x80000000 /* Self Test mask	      */
-#define   SDRAM_MCOPT2_SREN_EXIT      0x00000000 /* Self Test exit	      */
-#define   SDRAM_MCOPT2_SREN_ENTER     0x80000000 /* Self Test enter	      */
-#define SDRAM_MCOPT2_PMEN_MASK	      0x40000000 /* Power Management mask     */
-#define   SDRAM_MCOPT2_PMEN_DISABLE   0x00000000 /* disable		      */
-#define   SDRAM_MCOPT2_PMEN_ENABLE    0x40000000 /* enable		      */
-#define SDRAM_MCOPT2_IPTR_MASK	      0x20000000 /* Init Trigger Reg mask     */
-#define   SDRAM_MCOPT2_IPTR_IDLE      0x00000000 /* idle		      */
-#define   SDRAM_MCOPT2_IPTR_EXECUTE   0x20000000 /* execute preloaded init    */
-#define SDRAM_MCOPT2_XSRP_MASK	      0x10000000 /* Exit Self Refresh Prevent */
-#define   SDRAM_MCOPT2_XSRP_ALLOW     0x00000000 /* allow self refresh exit   */
-#define   SDRAM_MCOPT2_XSRP_PREVENT   0x10000000 /* prevent self refresh exit */
-#define SDRAM_MCOPT2_DCEN_MASK	      0x08000000 /* SDRAM Controller Enable   */
-#define   SDRAM_MCOPT2_DCEN_DISABLE   0x00000000 /* SDRAM Controller Enable   */
-#define   SDRAM_MCOPT2_DCEN_ENABLE    0x08000000 /* SDRAM Controller Enable   */
-#define SDRAM_MCOPT2_ISIE_MASK	      0x04000000 /* Init Seq Interruptable mas*/
-#define   SDRAM_MCOPT2_ISIE_DISABLE   0x00000000 /* disable		      */
-#define   SDRAM_MCOPT2_ISIE_ENABLE    0x04000000 /* enable		      */
-
-/*-----------------------------------------------------------------------------+
-|  SDRAM Refresh Timer Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_RTR_RINT_MASK		0xFFF80000
-#define   SDRAM_RTR_RINT_ENCODE(n)	((((unsigned long)(n))&0xFFF8)<<16)
-#define   SDRAM_RTR_RINT_DECODE(n)	((((unsigned long)(n))>>16)&0xFFF8)
-
-/*-----------------------------------------------------------------------------+
-|  SDRAM Read DQS Delay Control Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_RQDC_RQDE_MASK		0x80000000
-#define   SDRAM_RQDC_RQDE_DISABLE	0x00000000
-#define   SDRAM_RQDC_RQDE_ENABLE	0x80000000
-#define SDRAM_RQDC_RQFD_MASK		0x000001FF
-#define   SDRAM_RQDC_RQFD_ENCODE(n)	((((unsigned long)(n))&0x1FF)<<0)
-
-#define SDRAM_RQDC_RQFD_MAX		0xFF
-
-/*-----------------------------------------------------------------------------+
-|  SDRAM Read Data Capture Control Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_RDCC_RDSS_MASK		0xC0000000
-#define   SDRAM_RDCC_RDSS_T1		0x00000000
-#define   SDRAM_RDCC_RDSS_T2		0x40000000
-#define   SDRAM_RDCC_RDSS_T3		0x80000000
-#define   SDRAM_RDCC_RDSS_T4		0xC0000000
-#define SDRAM_RDCC_RSAE_MASK		0x00000001
-#define   SDRAM_RDCC_RSAE_DISABLE	0x00000001
-#define   SDRAM_RDCC_RSAE_ENABLE	0x00000000
-
-/*-----------------------------------------------------------------------------+
-|  SDRAM Read Feedback Delay Control Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_RFDC_ARSE_MASK		0x80000000
-#define   SDRAM_RFDC_ARSE_DISABLE	0x80000000
-#define   SDRAM_RFDC_ARSE_ENABLE	0x00000000
-#define SDRAM_RFDC_RFOS_MASK		0x007F0000
-#define   SDRAM_RFDC_RFOS_ENCODE(n)	((((unsigned long)(n))&0x7F)<<16)
-#define SDRAM_RFDC_RFFD_MASK		0x000003FF
-#define   SDRAM_RFDC_RFFD_ENCODE(n)	((((unsigned long)(n))&0x3FF)<<0)
-
-#define SDRAM_RFDC_RFFD_MAX		0x4FF
-
-/*-----------------------------------------------------------------------------+
-|  SDRAM Delay Line Calibration Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_DLCR_DCLM_MASK		0x80000000
-#define   SDRAM_DLCR_DCLM_MANUEL	0x80000000
-#define   SDRAM_DLCR_DCLM_AUTO		0x00000000
-#define SDRAM_DLCR_DLCR_MASK		0x08000000
-#define   SDRAM_DLCR_DLCR_CALIBRATE	0x08000000
-#define   SDRAM_DLCR_DLCR_IDLE		0x00000000
-#define SDRAM_DLCR_DLCS_MASK		0x07000000
-#define   SDRAM_DLCR_DLCS_NOT_RUN	0x00000000
-#define   SDRAM_DLCR_DLCS_IN_PROGRESS	0x01000000
-#define   SDRAM_DLCR_DLCS_COMPLETE	0x02000000
-#define   SDRAM_DLCR_DLCS_CONT_DONE	0x03000000
-#define   SDRAM_DLCR_DLCS_ERROR	0x04000000
-#define SDRAM_DLCR_DLCV_MASK		0x000001FF
-#define   SDRAM_DLCR_DLCV_ENCODE(n)	((((unsigned long)(n))&0x1FF)<<0)
-#define   SDRAM_DLCR_DLCV_DECODE(n)	((((unsigned long)(n))>>0)&0x1FF)
-
-/*-----------------------------------------------------------------------------+
-|  SDRAM Controller On Die Termination Register
-+-----------------------------------------------------------------------------*/
-#define   SDRAM_CODT_ODT_ON			0x80000000
-#define   SDRAM_CODT_ODT_OFF			0x00000000
-#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK	0x00000020
-#define   SDRAM_CODT_DQS_2_5_V_DDR1		0x00000000
-#define   SDRAM_CODT_DQS_1_8_V_DDR2		0x00000020
-#define SDRAM_CODT_DQS_MASK			0x00000010
-#define   SDRAM_CODT_DQS_DIFFERENTIAL		0x00000000
-#define   SDRAM_CODT_DQS_SINGLE_END		0x00000010
-#define   SDRAM_CODT_CKSE_DIFFERENTIAL		0x00000000
-#define   SDRAM_CODT_CKSE_SINGLE_END		0x00000008
-#define   SDRAM_CODT_FEEBBACK_RCV_SINGLE_END	0x00000004
-#define   SDRAM_CODT_FEEBBACK_DRV_SINGLE_END	0x00000002
-#define   SDRAM_CODT_IO_HIZ			0x00000000
-#define   SDRAM_CODT_IO_NMODE			0x00000001
-
-/*-----------------------------------------------------------------------------+
-|  SDRAM Mode Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_MMODE_WR_MASK			0x00000E00
-#define   SDRAM_MMODE_WR_DDR1			0x00000000
-#define   SDRAM_MMODE_WR_DDR2_3_CYC		0x00000400
-#define   SDRAM_MMODE_WR_DDR2_4_CYC		0x00000600
-#define   SDRAM_MMODE_WR_DDR2_5_CYC		0x00000800
-#define   SDRAM_MMODE_WR_DDR2_6_CYC		0x00000A00
-#define SDRAM_MMODE_DCL_MASK			0x00000070
-#define   SDRAM_MMODE_DCL_DDR1_2_0_CLK		0x00000020
-#define   SDRAM_MMODE_DCL_DDR1_2_5_CLK		0x00000060
-#define   SDRAM_MMODE_DCL_DDR1_3_0_CLK		0x00000030
-#define   SDRAM_MMODE_DCL_DDR2_2_0_CLK		0x00000020
-#define   SDRAM_MMODE_DCL_DDR2_3_0_CLK		0x00000030
-#define   SDRAM_MMODE_DCL_DDR2_4_0_CLK		0x00000040
-#define   SDRAM_MMODE_DCL_DDR2_5_0_CLK		0x00000050
-#define   SDRAM_MMODE_DCL_DDR2_6_0_CLK		0x00000060
-#define   SDRAM_MMODE_DCL_DDR2_7_0_CLK		0x00000070
-
-/*-----------------------------------------------------------------------------+
-|  SDRAM Extended Mode Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_MEMODE_DIC_MASK			0x00000002
-#define   SDRAM_MEMODE_DIC_NORMAL		0x00000000
-#define   SDRAM_MEMODE_DIC_WEAK			0x00000002
-#define SDRAM_MEMODE_DLL_MASK			0x00000001
-#define   SDRAM_MEMODE_DLL_DISABLE		0x00000001
-#define   SDRAM_MEMODE_DLL_ENABLE		0x00000000
-#define SDRAM_MEMODE_RTT_MASK			0x00000044
-#define   SDRAM_MEMODE_RTT_DISABLED		0x00000000
-#define   SDRAM_MEMODE_RTT_75OHM		0x00000004
-#define   SDRAM_MEMODE_RTT_150OHM		0x00000040
-#define SDRAM_MEMODE_DQS_MASK			0x00000400
-#define   SDRAM_MEMODE_DQS_DISABLE		0x00000400
-#define   SDRAM_MEMODE_DQS_ENABLE		0x00000000
-
-/*-----------------------------------------------------------------------------+
-|  SDRAM Clock Timing Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_CLKTR_CLKP_MASK			0xC0000000
-#define   SDRAM_CLKTR_CLKP_0_DEG		0x00000000
-#define   SDRAM_CLKTR_CLKP_180_DEG_ADV		0x80000000
-
-/*-----------------------------------------------------------------------------+
-|  SDRAM Write Timing Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_WRDTR_WDTP_1_CYC			0x80000000
-#define SDRAM_WRDTR_LLWP_MASK			0x10000000
-#define   SDRAM_WRDTR_LLWP_DIS			0x10000000
-#define   SDRAM_WRDTR_LLWP_1_CYC		0x00000000
-#define SDRAM_WRDTR_WTR_MASK			0x0E000000
-#define   SDRAM_WRDTR_WTR_0_DEG			0x06000000
-#define   SDRAM_WRDTR_WTR_180_DEG_ADV		0x02000000
-#define   SDRAM_WRDTR_WTR_270_DEG_ADV		0x00000000
-
-/*-----------------------------------------------------------------------------+
-|  SDRAM SDTR1 Options
-+-----------------------------------------------------------------------------*/
-#define SDRAM_SDTR1_LDOF_MASK			0x80000000
-#define   SDRAM_SDTR1_LDOF_1_CLK		0x00000000
-#define   SDRAM_SDTR1_LDOF_2_CLK		0x80000000
-#define SDRAM_SDTR1_RTW_MASK			0x00F00000
-#define   SDRAM_SDTR1_RTW_2_CLK		0x00200000
-#define   SDRAM_SDTR1_RTW_3_CLK		0x00300000
-#define SDRAM_SDTR1_WTWO_MASK			0x000F0000
-#define   SDRAM_SDTR1_WTWO_0_CLK		0x00000000
-#define   SDRAM_SDTR1_WTWO_1_CLK		0x00010000
-#define SDRAM_SDTR1_RTRO_MASK			0x0000F000
-#define   SDRAM_SDTR1_RTRO_1_CLK		0x00000000
-#define   SDRAM_SDTR1_RTRO_2_CLK		0x00002000
-
-/*-----------------------------------------------------------------------------+
-|  SDRAM SDTR2 Options
-+-----------------------------------------------------------------------------*/
-#define SDRAM_SDTR2_RCD_MASK			0xF0000000
-#define   SDRAM_SDTR2_RCD_1_CLK		0x10000000
-#define   SDRAM_SDTR2_RCD_2_CLK		0x20000000
-#define   SDRAM_SDTR2_RCD_3_CLK		0x30000000
-#define   SDRAM_SDTR2_RCD_4_CLK		0x40000000
-#define   SDRAM_SDTR2_RCD_5_CLK		0x50000000
-#define SDRAM_SDTR2_WTR_MASK		0x0F000000
-#define   SDRAM_SDTR2_WTR_1_CLK      0x01000000
-#define   SDRAM_SDTR2_WTR_2_CLK      0x02000000
-#define   SDRAM_SDTR2_WTR_3_CLK      0x03000000
-#define   SDRAM_SDTR2_WTR_4_CLK      0x04000000
-#define   SDRAM_SDTR3_WTR_ENCODE(n)  ((((unsigned long)(n))&0xF)<<24)
-#define SDRAM_SDTR2_XSNR_MASK	     0x00FF0000
-#define   SDRAM_SDTR2_XSNR_8_CLK     0x00080000
-#define   SDRAM_SDTR2_XSNR_16_CLK    0x00100000
-#define   SDRAM_SDTR2_XSNR_32_CLK    0x00200000
-#define   SDRAM_SDTR2_XSNR_64_CLK    0x00400000
-#define SDRAM_SDTR2_WPC_MASK	     0x0000F000
-#define   SDRAM_SDTR2_WPC_2_CLK      0x00002000
-#define   SDRAM_SDTR2_WPC_3_CLK      0x00003000
-#define   SDRAM_SDTR2_WPC_4_CLK      0x00004000
-#define   SDRAM_SDTR2_WPC_5_CLK      0x00005000
-#define   SDRAM_SDTR2_WPC_6_CLK      0x00006000
-#define   SDRAM_SDTR3_WPC_ENCODE(n)  ((((unsigned long)(n))&0xF)<<12)
-#define SDRAM_SDTR2_RPC_MASK	     0x00000F00
-#define   SDRAM_SDTR2_RPC_2_CLK      0x00000200
-#define   SDRAM_SDTR2_RPC_3_CLK      0x00000300
-#define   SDRAM_SDTR2_RPC_4_CLK      0x00000400
-#define SDRAM_SDTR2_RP_MASK	     0x000000F0
-#define   SDRAM_SDTR2_RP_3_CLK	     0x00000030
-#define   SDRAM_SDTR2_RP_4_CLK	     0x00000040
-#define   SDRAM_SDTR2_RP_5_CLK	     0x00000050
-#define   SDRAM_SDTR2_RP_6_CLK	     0x00000060
-#define   SDRAM_SDTR2_RP_7_CLK	     0x00000070
-#define SDRAM_SDTR2_RRD_MASK	     0x0000000F
-#define   SDRAM_SDTR2_RRD_2_CLK      0x00000002
-#define   SDRAM_SDTR2_RRD_3_CLK      0x00000003
-
-/*-----------------------------------------------------------------------------+
-|  SDRAM SDTR3 Options
-+-----------------------------------------------------------------------------*/
-#define SDRAM_SDTR3_RAS_MASK	     0x1F000000
-#define   SDRAM_SDTR3_RAS_ENCODE(n)  ((((unsigned long)(n))&0x1F)<<24)
-#define SDRAM_SDTR3_RC_MASK	     0x001F0000
-#define   SDRAM_SDTR3_RC_ENCODE(n)   ((((unsigned long)(n))&0x1F)<<16)
-#define SDRAM_SDTR3_XCS_MASK	     0x00001F00
-#define SDRAM_SDTR3_XCS		     0x00000D00
-#define SDRAM_SDTR3_RFC_MASK	     0x0000003F
-#define   SDRAM_SDTR3_RFC_ENCODE(n)  ((((unsigned long)(n))&0x3F)<<0)
-
-/*-----------------------------------------------------------------------------+
-|  Memory Bank 0-1 configuration
-+-----------------------------------------------------------------------------*/
-#define SDRAM_BXCF_M_AM_MASK	  0x00000F00	  /* Addressing mode	      */
-#define   SDRAM_BXCF_M_AM_0	  0x00000000	  /*   Mode 0		      */
-#define   SDRAM_BXCF_M_AM_1	  0x00000100	  /*   Mode 1		      */
-#define   SDRAM_BXCF_M_AM_2	  0x00000200	  /*   Mode 2		      */
-#define   SDRAM_BXCF_M_AM_3	  0x00000300	  /*   Mode 3		      */
-#define   SDRAM_BXCF_M_AM_4	  0x00000400	  /*   Mode 4		      */
-#define   SDRAM_BXCF_M_AM_5	  0x00000500	  /*   Mode 5		      */
-#define   SDRAM_BXCF_M_AM_6	  0x00000600	  /*   Mode 6		      */
-#define   SDRAM_BXCF_M_AM_7	  0x00000700	  /*   Mode 7		      */
-#define   SDRAM_BXCF_M_AM_8	  0x00000800	  /*   Mode 8		      */
-#define   SDRAM_BXCF_M_AM_9	  0x00000900	  /*   Mode 9		      */
-#define SDRAM_BXCF_M_BE_MASK	  0x00000001	  /* Memory Bank Enable       */
-#define   SDRAM_BXCF_M_BE_DISABLE 0x00000000	  /* Memory Bank Enable       */
-#define   SDRAM_BXCF_M_BE_ENABLE  0x00000001	  /* Memory Bank Enable       */
-
 #define sdr_uart0	0x0120	/* UART0 Config */
 #define sdr_uart1	0x0121	/* UART1 Config */
 #define sdr_mfr		0x4300	/* SDR0_MFR reg */
@@ -1612,4 +1340,27 @@
 #define SDR0_PFC1_GPT_FREQ	0x0000000f
 #endif
 
+/* General Purpose Timer (GPT) Register Offsets */
+#define GPT0_TBC		0x00000000
+#define GPT0_IM			0x00000018
+#define GPT0_ISS		0x0000001C
+#define GPT0_ISC		0x00000020
+#define GPT0_IE			0x00000024
+#define GPT0_COMP0		0x00000080
+#define GPT0_COMP1		0x00000084
+#define GPT0_COMP2		0x00000088
+#define GPT0_COMP3		0x0000008C
+#define GPT0_COMP4		0x00000090
+#define GPT0_COMP5		0x00000094
+#define GPT0_COMP6		0x00000098
+#define GPT0_MASK0		0x000000C0
+#define GPT0_MASK1		0x000000C4
+#define GPT0_MASK2		0x000000C8
+#define GPT0_MASK3		0x000000CC
+#define GPT0_MASK4		0x000000D0
+#define GPT0_MASK5		0x000000D4
+#define GPT0_MASK6		0x000000D8
+#define GPT0_DCT0		0x00000110
+#define GPT0_DCIS		0x0000011C
+
 #endif	/* __PPC405_H__ */
diff --git a/include/ppc440.h b/include/ppc440.h
index 54b4553..62f1680 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -210,36 +210,6 @@
 #define sdr_plbtr	0x4200
 #define sdr_mfr		0x4300	/* SDR0_MFR reg */
 
-/*-----------------------------------------------------------------------------
- | SDRAM Controller
- +----------------------------------------------------------------------------*/
-/* values for memcfga register - indirect addressing of these regs	    */
-#define mem_besr0_clr	0x0000	/* bus error status reg 0 (clr)		    */
-#define mem_besr0_set	0x0004	/* bus error status reg 0 (set)		    */
-#define mem_besr1_clr	0x0008	/* bus error status reg 1 (clr)		    */
-#define mem_besr1_set	0x000c	/* bus error status reg 1 (set)		    */
-#define mem_bear	0x0010	/* bus error address reg		    */
-#define mem_mirq_clr	0x0011	/* bus master interrupt (clr)		    */
-#define mem_mirq_set	0x0012	/* bus master interrupt (set)		    */
-#define mem_slio	0x0018	/* ddr sdram slave interface options	    */
-#define mem_cfg0	0x0020	/* ddr sdram options 0			    */
-#define mem_cfg1	0x0021	/* ddr sdram options 1			    */
-#define mem_devopt	0x0022	/* ddr sdram device options		    */
-#define mem_mcsts	0x0024	/* memory controller status		    */
-#define mem_rtr		0x0030	/* refresh timer register		    */
-#define mem_pmit	0x0034	/* power management idle timer		    */
-#define mem_uabba	0x0038	/* plb UABus base address		    */
-#define mem_b0cr	0x0040	/* ddr sdram bank 0 configuration	    */
-#define mem_b1cr	0x0044	/* ddr sdram bank 1 configuration	    */
-#define mem_b2cr	0x0048	/* ddr sdram bank 2 configuration	    */
-#define mem_b3cr	0x004c	/* ddr sdram bank 3 configuration	    */
-#define mem_tr0		0x0080	/* sdram timing register 0		    */
-#define mem_tr1		0x0081	/* sdram timing register 1		    */
-#define mem_clktr	0x0082	/* ddr clock timing register		    */
-#define mem_wddctr	0x0083	/* write data/dm/dqs clock timing reg	    */
-#define mem_dlycal	0x0084	/* delay line calibration register	    */
-#define mem_eccesr	0x0098	/* ECC error status			    */
-
 #ifdef CONFIG_440GX
 #define sdr_amp		0x0240
 #define sdr_xpllc	0x01c1
@@ -380,872 +350,6 @@
 #define SDR0_PEGPLLSTS		0x000003A2	/* PE Pll LC Tank Status */
 #endif /* CONFIG_440SPE */
 
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT)
-/*----------------------------------------------------------------------------+
-| SDRAM Controller
-+----------------------------------------------------------------------------*/
-/*-----------------------------------------------------------------------------+
-| SDRAM DLYCAL Options
-+-----------------------------------------------------------------------------*/
-#define SDRAM_DLYCAL_DLCV_MASK		0x000003FC
-#define SDRAM_DLYCAL_DLCV_ENCODE(x)	(((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
-#define SDRAM_DLYCAL_DLCV_DECODE(x)	(((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
-
-/*----------------------------------------------------------------------------+
-| Memory queue defines
-+----------------------------------------------------------------------------*/
-/* A REVOIR versus RWC  - SG*/
-#define SDRAMQ_DCR_BASE	0x040
-
-#define SDRAM_R0BAS	(SDRAMQ_DCR_BASE+0x0)	/* rank 0 base address & size  */
-#define SDRAM_R1BAS	(SDRAMQ_DCR_BASE+0x1)	/* rank 1 base address & size  */
-#define SDRAM_R2BAS	(SDRAMQ_DCR_BASE+0x2)	/* rank 2 base address & size  */
-#define SDRAM_R3BAS	(SDRAMQ_DCR_BASE+0x3)	/* rank 3 base address & size  */
-#define SDRAM_CONF1HB	(SDRAMQ_DCR_BASE+0x5)	/* configuration 1 HB          */
-#define SDRAM_ERRSTATHB	(SDRAMQ_DCR_BASE+0x7)	/* error status HB             */
-#define SDRAM_ERRADDUHB	(SDRAMQ_DCR_BASE+0x8)	/* error address upper 32 HB   */
-#define SDRAM_ERRADDLHB	(SDRAMQ_DCR_BASE+0x9)	/* error address lower 32 HB   */
-#define SDRAM_PLBADDULL	(SDRAMQ_DCR_BASE+0xA)	/* PLB base address upper 32 LL */
-#define SDRAM_CONF1LL	(SDRAMQ_DCR_BASE+0xB)	/* configuration 1 LL          */
-#define SDRAM_ERRSTATLL	(SDRAMQ_DCR_BASE+0xC)	/* error status LL             */
-#define SDRAM_ERRADDULL	(SDRAMQ_DCR_BASE+0xD)	/* error address upper 32 LL   */
-#define SDRAM_ERRADDLLL	(SDRAMQ_DCR_BASE+0xE)	/* error address lower 32 LL   */
-#define SDRAM_CONFPATHB	(SDRAMQ_DCR_BASE+0xF)	/* configuration between paths */
-#define SDRAM_PLBADDUHB	(SDRAMQ_DCR_BASE+0x10)	/* PLB base address upper 32 LL */
-
-/*-----------------------------------------------------------------------------+
-|  Memory Bank 0-7 configuration
-+-----------------------------------------------------------------------------*/
-#if defined(CONFIG_440SPE) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define SDRAM_RXBAS_SDBA_MASK		0xFFE00000	/* Base address	*/
-#define SDRAM_RXBAS_SDBA_ENCODE(n)	((((unsigned long)(n))&0xFFE00000)>>2)
-#define SDRAM_RXBAS_SDBA_DECODE(n)	((((unsigned long)(n))&0xFFE00000)<<2)
-#endif /* CONFIG_440SPE */
-#if defined(CONFIG_440SP)
-#define SDRAM_RXBAS_SDBA_MASK		0xFF800000	/* Base address	*/
-#define SDRAM_RXBAS_SDBA_ENCODE(n)	((((unsigned long)(n))&0xFF800000))
-#define SDRAM_RXBAS_SDBA_DECODE(n)	((((unsigned long)(n))&0xFF800000))
-#endif /* CONFIG_440SP */
-#define SDRAM_RXBAS_SDSZ_MASK		0x0000FFC0	/* Size		*/
-#define SDRAM_RXBAS_SDSZ_ENCODE(n)	((((unsigned long)(n))&0x3FF)<<6)
-#define SDRAM_RXBAS_SDSZ_DECODE(n)	((((unsigned long)(n))>>6)&0x3FF)
-#define SDRAM_RXBAS_SDSZ_0		0x00000000	/*   0M		*/
-#define SDRAM_RXBAS_SDSZ_8		0x0000FFC0	/*   8M		*/
-#define SDRAM_RXBAS_SDSZ_16		0x0000FF80	/*  16M		*/
-#define SDRAM_RXBAS_SDSZ_32		0x0000FF00	/*  32M		*/
-#define SDRAM_RXBAS_SDSZ_64		0x0000FE00	/*  64M		*/
-#define SDRAM_RXBAS_SDSZ_128		0x0000FC00	/* 128M		*/
-#define SDRAM_RXBAS_SDSZ_256		0x0000F800	/* 256M		*/
-#define SDRAM_RXBAS_SDSZ_512		0x0000F000	/* 512M		*/
-#define SDRAM_RXBAS_SDSZ_1024		0x0000E000	/* 1024M	*/
-#define SDRAM_RXBAS_SDSZ_2048		0x0000C000	/* 2048M	*/
-#define SDRAM_RXBAS_SDSZ_4096		0x00008000	/* 4096M	*/
-
-/*----------------------------------------------------------------------------+
-| Memory controller defines
-+----------------------------------------------------------------------------*/
-/* A REVOIR versus specs 4 bank  - SG*/
-#define SDRAM_MCSTAT	0x14	/* memory controller status                  */
-#define SDRAM_MCOPT1	0x20	/* memory controller options 1               */
-#define SDRAM_MCOPT2	0x21	/* memory controller options 2               */
-#define SDRAM_MODT0	0x22	/* on die termination for bank 0             */
-#define SDRAM_MODT1	0x23	/* on die termination for bank 1             */
-#define SDRAM_MODT2	0x24	/* on die termination for bank 2             */
-#define SDRAM_MODT3	0x25	/* on die termination for bank 3             */
-#define SDRAM_CODT	0x26	/* on die termination for controller         */
-#define SDRAM_VVPR	0x27	/* variable VRef programmming                */
-#define SDRAM_OPARS	0x28	/* on chip driver control setup              */
-#define SDRAM_OPART	0x29	/* on chip driver control trigger            */
-#define SDRAM_RTR	0x30	/* refresh timer                             */
-#define SDRAM_PMIT	0x34	/* power management idle timer               */
-#define SDRAM_MB0CF	0x40	/* memory bank 0 configuration               */
-#define SDRAM_MB1CF	0x44	/* memory bank 1 configuration               */
-#define SDRAM_MB2CF	0x48
-#define SDRAM_MB3CF	0x4C
-#define SDRAM_INITPLR0	0x50	/* manual initialization control             */
-#define SDRAM_INITPLR1	0x51	/* manual initialization control             */
-#define SDRAM_INITPLR2	0x52	/* manual initialization control             */
-#define SDRAM_INITPLR3	0x53	/* manual initialization control             */
-#define SDRAM_INITPLR4	0x54	/* manual initialization control             */
-#define SDRAM_INITPLR5	0x55	/* manual initialization control             */
-#define SDRAM_INITPLR6	0x56	/* manual initialization control             */
-#define SDRAM_INITPLR7	0x57	/* manual initialization control             */
-#define SDRAM_INITPLR8	0x58	/* manual initialization control             */
-#define SDRAM_INITPLR9	0x59	/* manual initialization control             */
-#define SDRAM_INITPLR10	0x5a	/* manual initialization control             */
-#define SDRAM_INITPLR11	0x5b	/* manual initialization control             */
-#define SDRAM_INITPLR12	0x5c	/* manual initialization control             */
-#define SDRAM_INITPLR13	0x5d	/* manual initialization control             */
-#define SDRAM_INITPLR14	0x5e	/* manual initialization control             */
-#define SDRAM_INITPLR15	0x5f	/* manual initialization control             */
-#define SDRAM_RQDC	0x70	/* read DQS delay control                    */
-#define SDRAM_RFDC	0x74	/* read feedback delay control               */
-#define SDRAM_RDCC	0x78	/* read data capture control                 */
-#define SDRAM_DLCR	0x7A	/* delay line calibration                    */
-#define SDRAM_CLKTR	0x80	/* DDR clock timing                          */
-#define SDRAM_WRDTR	0x81	/* write data, DQS, DM clock, timing         */
-#define SDRAM_SDTR1	0x85	/* DDR SDRAM timing 1                        */
-#define SDRAM_SDTR2	0x86	/* DDR SDRAM timing 2                        */
-#define SDRAM_SDTR3	0x87	/* DDR SDRAM timing 3                        */
-#define SDRAM_MMODE	0x88	/* memory mode                               */
-#define SDRAM_MEMODE	0x89	/* memory extended mode                      */
-#define SDRAM_ECCCR	0x98	/* ECC error status                          */
-#define SDRAM_CID	0xA4	/* core ID                                   */
-#define SDRAM_RID	0xA8	/* revision ID                               */
-#define SDRAM_RTSR	0xB1	/* run time status tracking                  */
-
-/*-----------------------------------------------------------------------------+
-|  Memory Controller Status
-+-----------------------------------------------------------------------------*/
-#define SDRAM_MCSTAT_MIC_MASK		0x80000000	/* Memory init status mask	*/
-#define SDRAM_MCSTAT_MIC_NOTCOMP	0x00000000	/* Mem init not complete	*/
-#define SDRAM_MCSTAT_MIC_COMP		0x80000000	/* Mem init complete		*/
-#define SDRAM_MCSTAT_SRMS_MASK		0x40000000	/* Mem self refresh stat mask	*/
-#define SDRAM_MCSTAT_SRMS_NOT_SF	0x00000000	/* Mem not in self refresh	*/
-#define SDRAM_MCSTAT_SRMS_SF		0x40000000	/* Mem in self refresh		*/
-#define SDRAM_MCSTAT_IDLE_MASK		0x20000000	/* Mem self refresh stat mask	*/
-#define SDRAM_MCSTAT_IDLE_NOT		0x00000000	/* Mem contr not idle		*/
-#define SDRAM_MCSTAT_IDLE		0x20000000	/* Mem contr idle		*/
-
-/*-----------------------------------------------------------------------------+
-|  Memory Controller Options 1
-+-----------------------------------------------------------------------------*/
-#define SDRAM_MCOPT1_MCHK_MASK		0x30000000 /* Memory data err check mask*/
-#define SDRAM_MCOPT1_MCHK_NON		0x00000000 /* No ECC generation		*/
-#define SDRAM_MCOPT1_MCHK_GEN		0x20000000 /* ECC generation		*/
-#define SDRAM_MCOPT1_MCHK_CHK		0x10000000 /* ECC generation and check	*/
-#define SDRAM_MCOPT1_MCHK_CHK_REP	0x30000000 /* ECC generation, chk, report*/
-#define SDRAM_MCOPT1_MCHK_CHK_DECODE(n)	((((unsigned long)(n))>>28)&0x3)
-#define SDRAM_MCOPT1_RDEN_MASK		0x08000000 /* Registered DIMM mask	*/
-#define SDRAM_MCOPT1_RDEN		0x08000000 /* Registered DIMM enable	*/
-#define SDRAM_MCOPT1_PMU_MASK		0x06000000 /* Page management unit mask	*/
-#define SDRAM_MCOPT1_PMU_CLOSE		0x00000000 /* PMU Close			*/
-#define SDRAM_MCOPT1_PMU_OPEN		0x04000000 /* PMU Open			*/
-#define SDRAM_MCOPT1_PMU_AUTOCLOSE	0x02000000 /* PMU AutoClose		*/
-#define SDRAM_MCOPT1_DMWD_MASK		0x01000000 /* DRAM width mask		*/
-#define SDRAM_MCOPT1_DMWD_32		0x00000000 /* 32 bits			*/
-#define SDRAM_MCOPT1_DMWD_64		0x01000000 /* 64 bits			*/
-#define SDRAM_MCOPT1_UIOS_MASK		0x00C00000 /* Unused IO State		*/
-#define SDRAM_MCOPT1_BCNT_MASK		0x00200000 /* Bank count		*/
-#define SDRAM_MCOPT1_4_BANKS		0x00000000 /* 4 Banks			*/
-#define SDRAM_MCOPT1_8_BANKS		0x00200000 /* 8 Banks			*/
-#define SDRAM_MCOPT1_DDR_TYPE_MASK	0x00100000 /* DDR Memory Type mask	*/
-#define SDRAM_MCOPT1_DDR1_TYPE		0x00000000 /* DDR1 Memory Type		*/
-#define SDRAM_MCOPT1_DDR2_TYPE		0x00100000 /* DDR2 Memory Type		*/
-#define SDRAM_MCOPT1_QDEP		0x00020000 /* 4 commands deep		*/
-#define SDRAM_MCOPT1_RWOO_MASK		0x00008000 /* Out of Order Read mask	*/
-#define SDRAM_MCOPT1_RWOO_DISABLED	0x00000000 /* disabled			*/
-#define SDRAM_MCOPT1_RWOO_ENABLED	0x00008000 /* enabled			*/
-#define SDRAM_MCOPT1_WOOO_MASK		0x00004000 /* Out of Order Write mask	*/
-#define SDRAM_MCOPT1_WOOO_DISABLED	0x00000000 /* disabled			*/
-#define SDRAM_MCOPT1_WOOO_ENABLED	0x00004000 /* enabled			*/
-#define SDRAM_MCOPT1_DCOO_MASK		0x00002000 /* All Out of Order mask	*/
-#define SDRAM_MCOPT1_DCOO_DISABLED	0x00002000 /* disabled			*/
-#define SDRAM_MCOPT1_DCOO_ENABLED	0x00000000 /* enabled			*/
-#define SDRAM_MCOPT1_DREF_MASK		0x00001000 /* Deferred refresh mask	*/
-#define SDRAM_MCOPT1_DREF_NORMAL	0x00000000 /* normal refresh		*/
-#define SDRAM_MCOPT1_DREF_DEFER_4	0x00001000 /* defer up to 4 refresh cmd	*/
-
-/*-----------------------------------------------------------------------------+
-|  Memory Controller Options 2
-+-----------------------------------------------------------------------------*/
-#define SDRAM_MCOPT2_SREN_MASK		0x80000000 /* Self Test mask		*/
-#define SDRAM_MCOPT2_SREN_EXIT		0x00000000 /* Self Test exit		*/
-#define SDRAM_MCOPT2_SREN_ENTER		0x80000000 /* Self Test enter		*/
-#define SDRAM_MCOPT2_PMEN_MASK		0x40000000 /* Power Management mask	*/
-#define SDRAM_MCOPT2_PMEN_DISABLE	0x00000000 /* disable			*/
-#define SDRAM_MCOPT2_PMEN_ENABLE	0x40000000 /* enable			*/
-#define SDRAM_MCOPT2_IPTR_MASK		0x20000000 /* Init Trigger Reg mask	*/
-#define SDRAM_MCOPT2_IPTR_IDLE		0x00000000 /* idle			*/
-#define SDRAM_MCOPT2_IPTR_EXECUTE	0x20000000 /* execute preloaded init	*/
-#define SDRAM_MCOPT2_XSRP_MASK		0x10000000 /* Exit Self Refresh Prevent	*/
-#define SDRAM_MCOPT2_XSRP_ALLOW		0x00000000 /* allow self refresh exit	*/
-#define SDRAM_MCOPT2_XSRP_PREVENT	0x10000000 /* prevent self refresh exit	*/
-#define SDRAM_MCOPT2_DCEN_MASK		0x08000000 /* SDRAM Controller Enable	*/
-#define SDRAM_MCOPT2_DCEN_DISABLE	0x00000000 /* SDRAM Controller Enable	*/
-#define SDRAM_MCOPT2_DCEN_ENABLE	0x08000000 /* SDRAM Controller Enable	*/
-#define SDRAM_MCOPT2_ISIE_MASK		0x04000000 /* Init Seq Interruptable mas*/
-#define SDRAM_MCOPT2_ISIE_DISABLE	0x00000000 /* disable			*/
-#define SDRAM_MCOPT2_ISIE_ENABLE	0x04000000 /* enable			*/
-
-/*-----------------------------------------------------------------------------+
-|  SDRAM Refresh Timer Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_RTR_RINT_MASK		0xFFF80000
-#define SDRAM_RTR_RINT_ENCODE(n)	((((unsigned long)(n))&0xFFF8)<<16)
-#define SDRAM_RTR_RINT_DECODE(n)	((((unsigned long)(n))>>16)&0xFFF8)
-
-/*-----------------------------------------------------------------------------+
-|  SDRAM Read DQS Delay Control Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_RQDC_RQDE_MASK		0x80000000
-#define SDRAM_RQDC_RQDE_DISABLE		0x00000000
-#define SDRAM_RQDC_RQDE_ENABLE		0x80000000
-#define SDRAM_RQDC_RQFD_MASK		0x000001FF
-#define SDRAM_RQDC_RQFD_ENCODE(n)	((((unsigned long)(n))&0x1FF)<<0)
-
-#define SDRAM_RQDC_RQFD_MAX		0x1FF
-
-/*-----------------------------------------------------------------------------+
-|  SDRAM Read Data Capture Control Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_RDCC_RDSS_MASK		0xC0000000
-#define SDRAM_RDCC_RDSS_T1		0x00000000
-#define SDRAM_RDCC_RDSS_T2		0x40000000
-#define SDRAM_RDCC_RDSS_T3		0x80000000
-#define SDRAM_RDCC_RDSS_T4		0xC0000000
-#define SDRAM_RDCC_RSAE_MASK		0x00000001
-#define SDRAM_RDCC_RSAE_DISABLE		0x00000001
-#define SDRAM_RDCC_RSAE_ENABLE		0x00000000
-
-/*-----------------------------------------------------------------------------+
-|  SDRAM Read Feedback Delay Control Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_RFDC_ARSE_MASK		0x80000000
-#define SDRAM_RFDC_ARSE_DISABLE		0x80000000
-#define SDRAM_RFDC_ARSE_ENABLE		0x00000000
-#define SDRAM_RFDC_RFOS_MASK		0x007F0000
-#define SDRAM_RFDC_RFOS_ENCODE(n)	((((unsigned long)(n))&0x7F)<<16)
-#define SDRAM_RFDC_RFFD_MASK		0x000007FF
-#define SDRAM_RFDC_RFFD_ENCODE(n)	((((unsigned long)(n))&0x7FF)<<0)
-
-#define SDRAM_RFDC_RFFD_MAX		0x7FF
-
-/*-----------------------------------------------------------------------------+
-|  SDRAM Delay Line Calibration Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_DLCR_DCLM_MASK		0x80000000
-#define SDRAM_DLCR_DCLM_MANUEL		0x80000000
-#define SDRAM_DLCR_DCLM_AUTO		0x00000000
-#define SDRAM_DLCR_DLCR_MASK		0x08000000
-#define SDRAM_DLCR_DLCR_CALIBRATE	0x08000000
-#define SDRAM_DLCR_DLCR_IDLE		0x00000000
-#define SDRAM_DLCR_DLCS_MASK		0x07000000
-#define SDRAM_DLCR_DLCS_NOT_RUN		0x00000000
-#define SDRAM_DLCR_DLCS_IN_PROGRESS	0x01000000
-#define SDRAM_DLCR_DLCS_COMPLETE	0x02000000
-#define SDRAM_DLCR_DLCS_CONT_DONE	0x03000000
-#define SDRAM_DLCR_DLCS_ERROR		0x04000000
-#define SDRAM_DLCR_DLCV_MASK		0x000001FF
-#define SDRAM_DLCR_DLCV_ENCODE(n)	((((unsigned long)(n))&0x1FF)<<0)
-#define SDRAM_DLCR_DLCV_DECODE(n)	((((unsigned long)(n))>>0)&0x1FF)
-
-/*-----------------------------------------------------------------------------+
-|  SDRAM Controller On Die Termination Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_CODT_ODT_ON			0x80000000
-#define SDRAM_CODT_ODT_OFF			0x00000000
-#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK		0x00000020
-#define SDRAM_CODT_DQS_2_5_V_DDR1		0x00000000
-#define SDRAM_CODT_DQS_1_8_V_DDR2		0x00000020
-#define SDRAM_CODT_DQS_MASK			0x00000010
-#define SDRAM_CODT_DQS_DIFFERENTIAL		0x00000000
-#define SDRAM_CODT_DQS_SINGLE_END		0x00000010
-#define SDRAM_CODT_CKSE_DIFFERENTIAL		0x00000000
-#define SDRAM_CODT_CKSE_SINGLE_END		0x00000008
-#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END	0x00000004
-#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END	0x00000002
-#define SDRAM_CODT_IO_HIZ			0x00000000
-#define SDRAM_CODT_IO_NMODE			0x00000001
-
-/*-----------------------------------------------------------------------------+
-|  SDRAM Mode Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_MMODE_WR_MASK		0x00000E00
-#define SDRAM_MMODE_WR_DDR1		0x00000000
-#define SDRAM_MMODE_WR_DDR2_3_CYC	0x00000400
-#define SDRAM_MMODE_WR_DDR2_4_CYC	0x00000600
-#define SDRAM_MMODE_WR_DDR2_5_CYC	0x00000800
-#define SDRAM_MMODE_WR_DDR2_6_CYC	0x00000A00
-#define SDRAM_MMODE_DCL_MASK		0x00000070
-#define SDRAM_MMODE_DCL_DDR1_2_0_CLK	0x00000020
-#define SDRAM_MMODE_DCL_DDR1_2_5_CLK	0x00000060
-#define SDRAM_MMODE_DCL_DDR1_3_0_CLK	0x00000030
-#define SDRAM_MMODE_DCL_DDR2_2_0_CLK	0x00000020
-#define SDRAM_MMODE_DCL_DDR2_3_0_CLK	0x00000030
-#define SDRAM_MMODE_DCL_DDR2_4_0_CLK	0x00000040
-#define SDRAM_MMODE_DCL_DDR2_5_0_CLK	0x00000050
-#define SDRAM_MMODE_DCL_DDR2_6_0_CLK	0x00000060
-#define SDRAM_MMODE_DCL_DDR2_7_0_CLK	0x00000070
-
-/*-----------------------------------------------------------------------------+
-|  SDRAM Extended Mode Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_MEMODE_DIC_MASK		0x00000002
-#define SDRAM_MEMODE_DIC_NORMAL		0x00000000
-#define SDRAM_MEMODE_DIC_WEAK		0x00000002
-#define SDRAM_MEMODE_DLL_MASK		0x00000001
-#define SDRAM_MEMODE_DLL_DISABLE	0x00000001
-#define SDRAM_MEMODE_DLL_ENABLE		0x00000000
-#define SDRAM_MEMODE_RTT_MASK		0x00000044
-#define SDRAM_MEMODE_RTT_DISABLED	0x00000000
-#define SDRAM_MEMODE_RTT_75OHM		0x00000004
-#define SDRAM_MEMODE_RTT_150OHM		0x00000040
-#define SDRAM_MEMODE_DQS_MASK		0x00000400
-#define SDRAM_MEMODE_DQS_DISABLE	0x00000400
-#define SDRAM_MEMODE_DQS_ENABLE		0x00000000
-
-/*-----------------------------------------------------------------------------+
-|  SDRAM Clock Timing Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_CLKTR_CLKP_MASK		0xC0000000
-#define SDRAM_CLKTR_CLKP_0_DEG		0x00000000
-#define SDRAM_CLKTR_CLKP_180_DEG_ADV	0x80000000
-#define SDRAM_CLKTR_CLKP_90_DEG_ADV	0x40000000
-#define SDRAM_CLKTR_CLKP_270_DEG_ADV	0xC0000000
-
-/*-----------------------------------------------------------------------------+
-|  SDRAM Write Timing Register
-+-----------------------------------------------------------------------------*/
-#define SDRAM_WRDTR_LLWP_MASK		0x10000000
-#define SDRAM_WRDTR_LLWP_DIS		0x10000000
-#define SDRAM_WRDTR_LLWP_1_CYC		0x00000000
-#define SDRAM_WRDTR_WTR_MASK		0x0E000000
-#define SDRAM_WRDTR_WTR_0_DEG		0x06000000
-#define SDRAM_WRDTR_WTR_90_DEG_ADV	0x04000000
-#define SDRAM_WRDTR_WTR_180_DEG_ADV	0x02000000
-#define SDRAM_WRDTR_WTR_270_DEG_ADV	0x00000000
-
-/*-----------------------------------------------------------------------------+
-|  SDRAM SDTR1 Options
-+-----------------------------------------------------------------------------*/
-#define SDRAM_SDTR1_LDOF_MASK		0x80000000
-#define SDRAM_SDTR1_LDOF_1_CLK		0x00000000
-#define SDRAM_SDTR1_LDOF_2_CLK		0x80000000
-#define SDRAM_SDTR1_RTW_MASK		0x00F00000
-#define SDRAM_SDTR1_RTW_2_CLK		0x00200000
-#define SDRAM_SDTR1_RTW_3_CLK		0x00300000
-#define SDRAM_SDTR1_WTWO_MASK		0x000F0000
-#define SDRAM_SDTR1_WTWO_0_CLK		0x00000000
-#define SDRAM_SDTR1_WTWO_1_CLK		0x00010000
-#define SDRAM_SDTR1_RTRO_MASK		0x0000F000
-#define SDRAM_SDTR1_RTRO_1_CLK		0x00001000
-#define SDRAM_SDTR1_RTRO_2_CLK		0x00002000
-
-/*-----------------------------------------------------------------------------+
-|  SDRAM SDTR2 Options
-+-----------------------------------------------------------------------------*/
-#define SDRAM_SDTR2_RCD_MASK		0xF0000000
-#define SDRAM_SDTR2_RCD_1_CLK		0x10000000
-#define SDRAM_SDTR2_RCD_2_CLK		0x20000000
-#define SDRAM_SDTR2_RCD_3_CLK		0x30000000
-#define SDRAM_SDTR2_RCD_4_CLK		0x40000000
-#define SDRAM_SDTR2_RCD_5_CLK		0x50000000
-#define SDRAM_SDTR2_WTR_MASK		0x0F000000
-#define SDRAM_SDTR2_WTR_1_CLK		0x01000000
-#define SDRAM_SDTR2_WTR_2_CLK		0x02000000
-#define SDRAM_SDTR2_WTR_3_CLK		0x03000000
-#define SDRAM_SDTR2_WTR_4_CLK		0x04000000
-#define SDRAM_SDTR3_WTR_ENCODE(n)	((((unsigned long)(n))&0xF)<<24)
-#define SDRAM_SDTR2_XSNR_MASK		0x00FF0000
-#define SDRAM_SDTR2_XSNR_8_CLK		0x00080000
-#define SDRAM_SDTR2_XSNR_16_CLK		0x00100000
-#define SDRAM_SDTR2_XSNR_32_CLK		0x00200000
-#define SDRAM_SDTR2_XSNR_64_CLK		0x00400000
-#define SDRAM_SDTR2_WPC_MASK		0x0000F000
-#define SDRAM_SDTR2_WPC_2_CLK		0x00002000
-#define SDRAM_SDTR2_WPC_3_CLK		0x00003000
-#define SDRAM_SDTR2_WPC_4_CLK		0x00004000
-#define SDRAM_SDTR2_WPC_5_CLK		0x00005000
-#define SDRAM_SDTR2_WPC_6_CLK		0x00006000
-#define SDRAM_SDTR3_WPC_ENCODE(n)	((((unsigned long)(n))&0xF)<<12)
-#define SDRAM_SDTR2_RPC_MASK		0x00000F00
-#define SDRAM_SDTR2_RPC_2_CLK		0x00000200
-#define SDRAM_SDTR2_RPC_3_CLK		0x00000300
-#define SDRAM_SDTR2_RPC_4_CLK		0x00000400
-#define SDRAM_SDTR2_RP_MASK		0x000000F0
-#define SDRAM_SDTR2_RP_3_CLK		0x00000030
-#define SDRAM_SDTR2_RP_4_CLK		0x00000040
-#define SDRAM_SDTR2_RP_5_CLK		0x00000050
-#define SDRAM_SDTR2_RP_6_CLK		0x00000060
-#define SDRAM_SDTR2_RP_7_CLK		0x00000070
-#define SDRAM_SDTR2_RRD_MASK		0x0000000F
-#define SDRAM_SDTR2_RRD_2_CLK		0x00000002
-#define SDRAM_SDTR2_RRD_3_CLK		0x00000003
-
-/*-----------------------------------------------------------------------------+
-|  SDRAM SDTR3 Options
-+-----------------------------------------------------------------------------*/
-#define SDRAM_SDTR3_RAS_MASK		0x1F000000
-#define SDRAM_SDTR3_RAS_ENCODE(n)	((((unsigned long)(n))&0x1F)<<24)
-#define SDRAM_SDTR3_RC_MASK		0x001F0000
-#define SDRAM_SDTR3_RC_ENCODE(n)	((((unsigned long)(n))&0x1F)<<16)
-#define SDRAM_SDTR3_XCS_MASK		0x00001F00
-#define SDRAM_SDTR3_XCS			0x00000D00
-#define SDRAM_SDTR3_RFC_MASK		0x0000003F
-#define SDRAM_SDTR3_RFC_ENCODE(n)	((((unsigned long)(n))&0x3F)<<0)
-
-/*-----------------------------------------------------------------------------+
-|  Memory Bank 0-1 configuration
-+-----------------------------------------------------------------------------*/
-#define SDRAM_BXCF_M_AM_MASK		0x00000F00	/* Addressing mode	*/
-#define SDRAM_BXCF_M_AM_0		0x00000000	/*   Mode 0		*/
-#define SDRAM_BXCF_M_AM_1		0x00000100	/*   Mode 1		*/
-#define SDRAM_BXCF_M_AM_2		0x00000200	/*   Mode 2		*/
-#define SDRAM_BXCF_M_AM_3		0x00000300	/*   Mode 3		*/
-#define SDRAM_BXCF_M_AM_4		0x00000400	/*   Mode 4		*/
-#define SDRAM_BXCF_M_AM_5		0x00000500	/*   Mode 5		*/
-#define SDRAM_BXCF_M_AM_6		0x00000600	/*   Mode 6		*/
-#define SDRAM_BXCF_M_AM_7		0x00000700	/*   Mode 7		*/
-#define SDRAM_BXCF_M_AM_8		0x00000800	/*   Mode 8		*/
-#define SDRAM_BXCF_M_AM_9		0x00000900	/*   Mode 9		*/
-#define SDRAM_BXCF_M_BE_MASK		0x00000001	/* Memory Bank Enable	*/
-#define SDRAM_BXCF_M_BE_DISABLE		0x00000000	/* Memory Bank Enable	*/
-#define SDRAM_BXCF_M_BE_ENABLE		0x00000001	/* Memory Bank Enable	*/
-
-#define SDRAM_RTSR_TRK1SM_MASK		0xC0000000	/* Tracking State Mach 1*/
-#define SDRAM_RTSR_TRK1SM_ATBASE	0x00000000	/* atbase state		*/
-#define SDRAM_RTSR_TRK1SM_MISSED	0x40000000	/* missed state		*/
-#define SDRAM_RTSR_TRK1SM_ATPLS1	0x80000000	/* atpls1 state		*/
-#define SDRAM_RTSR_TRK1SM_RESET		0xC0000000	/* reset  state		*/
-
-#define SDR0_MFR_FIXD			0x10000000	/* Workaround for PCI/DMA */
-#endif /* CONFIG_440SPE */
-
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-/*-----------------------------------------------------------------------------
- | SDRAM Controller
- +----------------------------------------------------------------------------*/
-#define DDR0_00				0x00
-#define DDR0_00_INT_ACK_MASK              0x7F000000	/* Write only */
-#define DDR0_00_INT_ACK_ALL               0x7F000000
-#define DDR0_00_INT_ACK_ENCODE(n)           ((((unsigned long)(n))&0x7F)<<24)
-#define DDR0_00_INT_ACK_DECODE(n)           ((((unsigned long)(n))>>24)&0x7F)
-/* Status */
-#define DDR0_00_INT_STATUS_MASK           0x00FF0000	/* Read only */
-/* Bit0. A single access outside the defined PHYSICAL memory space detected. */
-#define DDR0_00_INT_STATUS_BIT0           0x00010000
-/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */
-#define DDR0_00_INT_STATUS_BIT1           0x00020000
-/* Bit2. Single correctable ECC event detected */
-#define DDR0_00_INT_STATUS_BIT2           0x00040000
-/* Bit3. Multiple correctable ECC events detected. */
-#define DDR0_00_INT_STATUS_BIT3           0x00080000
-/* Bit4. Single uncorrectable ECC event detected. */
-#define DDR0_00_INT_STATUS_BIT4           0x00100000
-/* Bit5. Multiple uncorrectable ECC events detected. */
-#define DDR0_00_INT_STATUS_BIT5           0x00200000
-/* Bit6. DRAM initialization complete. */
-#define DDR0_00_INT_STATUS_BIT6           0x00400000
-/* Bit7. Logical OR of all lower bits. */
-#define DDR0_00_INT_STATUS_BIT7           0x00800000
-
-#define DDR0_00_INT_STATUS_ENCODE(n)        ((((unsigned long)(n))&0xFF)<<16)
-#define DDR0_00_INT_STATUS_DECODE(n)        ((((unsigned long)(n))>>16)&0xFF)
-#define DDR0_00_DLL_INCREMENT_MASK        0x00007F00
-#define DDR0_00_DLL_INCREMENT_ENCODE(n)     ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_00_DLL_INCREMENT_DECODE(n)     ((((unsigned long)(n))>>8)&0x7F)
-#define DDR0_00_DLL_START_POINT_MASK      0x0000007F
-#define DDR0_00_DLL_START_POINT_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_00_DLL_START_POINT_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
-
-#define DDR0_01				0x01
-#define DDR0_01_PLB0_DB_CS_LOWER_MASK     0x1F000000
-#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n)  ((((unsigned long)(n))&0x1F)<<24)
-#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n)  ((((unsigned long)(n))>>24)&0x1F)
-#define DDR0_01_PLB0_DB_CS_UPPER_MASK     0x001F0000
-#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n)  ((((unsigned long)(n))&0x1F)<<16)
-#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n)  ((((unsigned long)(n))>>16)&0x1F)
-#define DDR0_01_OUT_OF_RANGE_TYPE_MASK    0x00000700	/* Read only */
-#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n)               ((((unsigned long)(n))&0x7)<<8)
-#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n)               ((((unsigned long)(n))>>8)&0x7)
-#define DDR0_01_INT_MASK_MASK             0x000000FF
-#define DDR0_01_INT_MASK_ENCODE(n)          ((((unsigned long)(n))&0xFF)<<0)
-#define DDR0_01_INT_MASK_DECODE(n)          ((((unsigned long)(n))>>0)&0xFF)
-#define DDR0_01_INT_MASK_ALL_ON           0x000000FF
-#define DDR0_01_INT_MASK_ALL_OFF          0x00000000
-
-#define DDR0_02				0x02
-#define DDR0_02_MAX_CS_REG_MASK           0x02000000	/* Read only */
-#define DDR0_02_MAX_CS_REG_ENCODE(n)        ((((unsigned long)(n))&0x2)<<24)
-#define DDR0_02_MAX_CS_REG_DECODE(n)        ((((unsigned long)(n))>>24)&0x2)
-#define DDR0_02_MAX_COL_REG_MASK          0x000F0000	/* Read only */
-#define DDR0_02_MAX_COL_REG_ENCODE(n)       ((((unsigned long)(n))&0xF)<<16)
-#define DDR0_02_MAX_COL_REG_DECODE(n)       ((((unsigned long)(n))>>16)&0xF)
-#define DDR0_02_MAX_ROW_REG_MASK          0x00000F00	/* Read only */
-#define DDR0_02_MAX_ROW_REG_ENCODE(n)       ((((unsigned long)(n))&0xF)<<8)
-#define DDR0_02_MAX_ROW_REG_DECODE(n)       ((((unsigned long)(n))>>8)&0xF)
-#define DDR0_02_START_MASK                0x00000001
-#define DDR0_02_START_ENCODE(n)             ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_02_START_DECODE(n)             ((((unsigned long)(n))>>0)&0x1)
-#define DDR0_02_START_OFF                 0x00000000
-#define DDR0_02_START_ON                  0x00000001
-
-#define DDR0_03				0x03
-#define DDR0_03_BSTLEN_MASK               0x07000000
-#define DDR0_03_BSTLEN_ENCODE(n)            ((((unsigned long)(n))&0x7)<<24)
-#define DDR0_03_BSTLEN_DECODE(n)            ((((unsigned long)(n))>>24)&0x7)
-#define DDR0_03_CASLAT_MASK               0x00070000
-#define DDR0_03_CASLAT_ENCODE(n)            ((((unsigned long)(n))&0x7)<<16)
-#define DDR0_03_CASLAT_DECODE(n)            ((((unsigned long)(n))>>16)&0x7)
-#define DDR0_03_CASLAT_LIN_MASK           0x00000F00
-#define DDR0_03_CASLAT_LIN_ENCODE(n)        ((((unsigned long)(n))&0xF)<<8)
-#define DDR0_03_CASLAT_LIN_DECODE(n)        ((((unsigned long)(n))>>8)&0xF)
-#define DDR0_03_INITAREF_MASK             0x0000000F
-#define DDR0_03_INITAREF_ENCODE(n)          ((((unsigned long)(n))&0xF)<<0)
-#define DDR0_03_INITAREF_DECODE(n)          ((((unsigned long)(n))>>0)&0xF)
-
-#define DDR0_04				0x04
-#define DDR0_04_TRC_MASK                  0x1F000000
-#define DDR0_04_TRC_ENCODE(n)               ((((unsigned long)(n))&0x1F)<<24)
-#define DDR0_04_TRC_DECODE(n)               ((((unsigned long)(n))>>24)&0x1F)
-#define DDR0_04_TRRD_MASK                 0x00070000
-#define DDR0_04_TRRD_ENCODE(n)              ((((unsigned long)(n))&0x7)<<16)
-#define DDR0_04_TRRD_DECODE(n)              ((((unsigned long)(n))>>16)&0x7)
-#define DDR0_04_TRTP_MASK                 0x00000700
-#define DDR0_04_TRTP_ENCODE(n)              ((((unsigned long)(n))&0x7)<<8)
-#define DDR0_04_TRTP_DECODE(n)              ((((unsigned long)(n))>>8)&0x7)
-
-#define DDR0_05				0x05
-#define DDR0_05_TMRD_MASK                 0x1F000000
-#define DDR0_05_TMRD_ENCODE(n)              ((((unsigned long)(n))&0x1F)<<24)
-#define DDR0_05_TMRD_DECODE(n)              ((((unsigned long)(n))>>24)&0x1F)
-#define DDR0_05_TEMRS_MASK                0x00070000
-#define DDR0_05_TEMRS_ENCODE(n)             ((((unsigned long)(n))&0x7)<<16)
-#define DDR0_05_TEMRS_DECODE(n)             ((((unsigned long)(n))>>16)&0x7)
-#define DDR0_05_TRP_MASK                  0x00000F00
-#define DDR0_05_TRP_ENCODE(n)               ((((unsigned long)(n))&0xF)<<8)
-#define DDR0_05_TRP_DECODE(n)               ((((unsigned long)(n))>>8)&0xF)
-#define DDR0_05_TRAS_MIN_MASK             0x000000FF
-#define DDR0_05_TRAS_MIN_ENCODE(n)          ((((unsigned long)(n))&0xFF)<<0)
-#define DDR0_05_TRAS_MIN_DECODE(n)          ((((unsigned long)(n))>>0)&0xFF)
-
-#define DDR0_06				0x06
-#define DDR0_06_WRITEINTERP_MASK          0x01000000
-#define DDR0_06_WRITEINTERP_ENCODE(n)       ((((unsigned long)(n))&0x1)<<24)
-#define DDR0_06_WRITEINTERP_DECODE(n)       ((((unsigned long)(n))>>24)&0x1)
-#define DDR0_06_TWTR_MASK                 0x00070000
-#define DDR0_06_TWTR_ENCODE(n)              ((((unsigned long)(n))&0x7)<<16)
-#define DDR0_06_TWTR_DECODE(n)              ((((unsigned long)(n))>>16)&0x7)
-#define DDR0_06_TDLL_MASK                 0x0000FF00
-#define DDR0_06_TDLL_ENCODE(n)              ((((unsigned long)(n))&0xFF)<<8)
-#define DDR0_06_TDLL_DECODE(n)              ((((unsigned long)(n))>>8)&0xFF)
-#define DDR0_06_TRFC_MASK                 0x0000007F
-#define DDR0_06_TRFC_ENCODE(n)              ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_06_TRFC_DECODE(n)              ((((unsigned long)(n))>>0)&0x7F)
-
-#define DDR0_07				0x07
-#define DDR0_07_NO_CMD_INIT_MASK          0x01000000
-#define DDR0_07_NO_CMD_INIT_ENCODE(n)       ((((unsigned long)(n))&0x1)<<24)
-#define DDR0_07_NO_CMD_INIT_DECODE(n)       ((((unsigned long)(n))>>24)&0x1)
-#define DDR0_07_TFAW_MASK                 0x001F0000
-#define DDR0_07_TFAW_ENCODE(n)              ((((unsigned long)(n))&0x1F)<<16)
-#define DDR0_07_TFAW_DECODE(n)              ((((unsigned long)(n))>>16)&0x1F)
-#define DDR0_07_AUTO_REFRESH_MODE_MASK    0x00000100
-#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
-#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
-#define DDR0_07_AREFRESH_MASK             0x00000001
-#define DDR0_07_AREFRESH_ENCODE(n)          ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_07_AREFRESH_DECODE(n)          ((((unsigned long)(n))>>0)&0x1)
-
-#define DDR0_08				0x08
-#define DDR0_08_WRLAT_MASK                0x07000000
-#define DDR0_08_WRLAT_ENCODE(n)             ((((unsigned long)(n))&0x7)<<24)
-#define DDR0_08_WRLAT_DECODE(n)             ((((unsigned long)(n))>>24)&0x7)
-#define DDR0_08_TCPD_MASK                 0x00FF0000
-#define DDR0_08_TCPD_ENCODE(n)              ((((unsigned long)(n))&0xFF)<<16)
-#define DDR0_08_TCPD_DECODE(n)              ((((unsigned long)(n))>>16)&0xFF)
-#define DDR0_08_DQS_N_EN_MASK             0x00000100
-#define DDR0_08_DQS_N_EN_ENCODE(n)          ((((unsigned long)(n))&0x1)<<8)
-#define DDR0_08_DQS_N_EN_DECODE(n)          ((((unsigned long)(n))>>8)&0x1)
-#define DDR0_08_DDRII_SDRAM_MODE_MASK     0x00000001
-#define DDR0_08_DDRII_ENCODE(n)             ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_08_DDRII_DECODE(n)             ((((unsigned long)(n))>>0)&0x1)
-
-#define DDR0_09				0x09
-#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK  0x1F000000
-#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
-#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
-#define DDR0_09_RTT_0_MASK                0x00030000
-#define DDR0_09_RTT_0_ENCODE(n)             ((((unsigned long)(n))&0x3)<<16)
-#define DDR0_09_RTT_0_DECODE(n)             ((((unsigned long)(n))>>16)&0x3)
-#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK  0x00007F00
-#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
-#define DDR0_09_WR_DQS_SHIFT_MASK         0x0000007F
-#define DDR0_09_WR_DQS_SHIFT_ENCODE(n)      ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_09_WR_DQS_SHIFT_DECODE(n)      ((((unsigned long)(n))>>0)&0x7F)
-
-#define DDR0_10				0x0A
-#define DDR0_10_WRITE_MODEREG_MASK        0x00010000	/* Write only */
-#define DDR0_10_WRITE_MODEREG_ENCODE(n)     ((((unsigned long)(n))&0x1)<<16)
-#define DDR0_10_WRITE_MODEREG_DECODE(n)     ((((unsigned long)(n))>>16)&0x1)
-#define DDR0_10_CS_MAP_MASK               0x00000300
-#define DDR0_10_CS_MAP_NO_MEM             0x00000000
-#define DDR0_10_CS_MAP_RANK0_INSTALLED    0x00000100
-#define DDR0_10_CS_MAP_RANK1_INSTALLED    0x00000200
-#define DDR0_10_CS_MAP_ENCODE(n)            ((((unsigned long)(n))&0x3)<<8)
-#define DDR0_10_CS_MAP_DECODE(n)            ((((unsigned long)(n))>>8)&0x3)
-#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK  0x0000001F
-#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0)
-#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F)
-
-#define DDR0_11				0x0B
-#define DDR0_11_SREFRESH_MASK             0x01000000
-#define DDR0_11_SREFRESH_ENCODE(n)          ((((unsigned long)(n))&0x1)<<24)
-#define DDR0_11_SREFRESH_DECODE(n)          ((((unsigned long)(n))>>24)&0x1F)
-#define DDR0_11_TXSNR_MASK                0x00FF0000
-#define DDR0_11_TXSNR_ENCODE(n)             ((((unsigned long)(n))&0xFF)<<16)
-#define DDR0_11_TXSNR_DECODE(n)             ((((unsigned long)(n))>>16)&0xFF)
-#define DDR0_11_TXSR_MASK                 0x0000FF00
-#define DDR0_11_TXSR_ENCODE(n)              ((((unsigned long)(n))&0xFF)<<8)
-#define DDR0_11_TXSR_DECODE(n)              ((((unsigned long)(n))>>8)&0xFF)
-
-#define DDR0_12				0x0C
-#define DDR0_12_TCKE_MASK                 0x0000007
-#define DDR0_12_TCKE_ENCODE(n)              ((((unsigned long)(n))&0x7)<<0)
-#define DDR0_12_TCKE_DECODE(n)              ((((unsigned long)(n))>>0)&0x7)
-
-#define DDR0_14				0x0E
-#define DDR0_14_DLL_BYPASS_MODE_MASK      0x01000000
-#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n)   ((((unsigned long)(n))&0x1)<<24)
-#define DDR0_14_DLL_BYPASS_MODE_DECODE(n)   ((((unsigned long)(n))>>24)&0x1)
-#define DDR0_14_REDUC_MASK                0x00010000
-#define DDR0_14_REDUC_64BITS              0x00000000
-#define DDR0_14_REDUC_32BITS              0x00010000
-#define DDR0_14_REDUC_ENCODE(n)             ((((unsigned long)(n))&0x1)<<16)
-#define DDR0_14_REDUC_DECODE(n)             ((((unsigned long)(n))>>16)&0x1)
-#define DDR0_14_REG_DIMM_ENABLE_MASK      0x00000100
-#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n)   ((((unsigned long)(n))&0x1)<<8)
-#define DDR0_14_REG_DIMM_ENABLE_DECODE(n)   ((((unsigned long)(n))>>8)&0x1)
-
-#define DDR0_17				0x11
-#define DDR0_17_DLL_DQS_DELAY_0_MASK      0x7F000000
-#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
-#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
-#define DDR0_17_DLLLOCKREG_MASK           0x00010000	/* Read only */
-#define DDR0_17_DLLLOCKREG_LOCKED         0x00010000
-#define DDR0_17_DLLLOCKREG_UNLOCKED       0x00000000
-#define DDR0_17_DLLLOCKREG_ENCODE(n)        ((((unsigned long)(n))&0x1)<<16)
-#define DDR0_17_DLLLOCKREG_DECODE(n)        ((((unsigned long)(n))>>16)&0x1)
-#define DDR0_17_DLL_LOCK_MASK             0x00007F00	/* Read only */
-#define DDR0_17_DLL_LOCK_ENCODE(n)          ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_17_DLL_LOCK_DECODE(n)          ((((unsigned long)(n))>>8)&0x7F)
-
-#define DDR0_18				0x12
-#define DDR0_18_DLL_DQS_DELAY_X_MASK      0x7F7F7F7F
-#define DDR0_18_DLL_DQS_DELAY_4_MASK      0x7F000000
-#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
-#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
-#define DDR0_18_DLL_DQS_DELAY_3_MASK      0x007F0000
-#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<16)
-#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n)   ((((unsigned long)(n))>>16)&0x7F)
-#define DDR0_18_DLL_DQS_DELAY_2_MASK      0x00007F00
-#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n)   ((((unsigned long)(n))>>8)&0x7F)
-#define DDR0_18_DLL_DQS_DELAY_1_MASK      0x0000007F
-#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
-
-#define DDR0_19				0x13
-#define DDR0_19_DLL_DQS_DELAY_X_MASK      0x7F7F7F7F
-#define DDR0_19_DLL_DQS_DELAY_8_MASK      0x7F000000
-#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
-#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
-#define DDR0_19_DLL_DQS_DELAY_7_MASK      0x007F0000
-#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<16)
-#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n)   ((((unsigned long)(n))>>16)&0x7F)
-#define DDR0_19_DLL_DQS_DELAY_6_MASK      0x00007F00
-#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n)   ((((unsigned long)(n))>>8)&0x7F)
-#define DDR0_19_DLL_DQS_DELAY_5_MASK      0x0000007F
-#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
-
-#define DDR0_20				0x14
-#define DDR0_20_DLL_DQS_BYPASS_3_MASK      0x7F000000
-#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
-#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
-#define DDR0_20_DLL_DQS_BYPASS_2_MASK      0x007F0000
-#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<16)
-#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n)   ((((unsigned long)(n))>>16)&0x7F)
-#define DDR0_20_DLL_DQS_BYPASS_1_MASK      0x00007F00
-#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n)   ((((unsigned long)(n))>>8)&0x7F)
-#define DDR0_20_DLL_DQS_BYPASS_0_MASK      0x0000007F
-#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
-
-#define DDR0_21				0x15
-#define DDR0_21_DLL_DQS_BYPASS_7_MASK      0x7F000000
-#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
-#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
-#define DDR0_21_DLL_DQS_BYPASS_6_MASK      0x007F0000
-#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<16)
-#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n)   ((((unsigned long)(n))>>16)&0x7F)
-#define DDR0_21_DLL_DQS_BYPASS_5_MASK      0x00007F00
-#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n)   ((((unsigned long)(n))>>8)&0x7F)
-#define DDR0_21_DLL_DQS_BYPASS_4_MASK      0x0000007F
-#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
-
-#define DDR0_22				0x16
-#define DDR0_22_CTRL_RAW_MASK             0x03000000
-#define DDR0_22_CTRL_RAW_ECC_DISABLE      0x00000000	/* ECC not being used */
-#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY   0x01000000	/* ECC checking is on, but no attempts to correct */
-#define DDR0_22_CTRL_RAW_NO_ECC_RAM       0x02000000	/* No ECC RAM storage available */
-#define DDR0_22_CTRL_RAW_ECC_ENABLE       0x03000000	/* ECC checking and correcting on */
-#define DDR0_22_CTRL_RAW_ENCODE(n)          ((((unsigned long)(n))&0x3)<<24)
-#define DDR0_22_CTRL_RAW_DECODE(n)          ((((unsigned long)(n))>>24)&0x3)
-#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000
-#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
-#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
-#define DDR0_22_DQS_OUT_SHIFT_MASK        0x00007F00
-#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n)     ((((unsigned long)(n))&0x7F)<<8)
-#define DDR0_22_DQS_OUT_SHIFT_DECODE(n)     ((((unsigned long)(n))>>8)&0x7F)
-#define DDR0_22_DLL_DQS_BYPASS_8_MASK     0x0000007F
-#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n)  ((((unsigned long)(n))&0x7F)<<0)
-#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n)  ((((unsigned long)(n))>>0)&0x7F)
-
-#define DDR0_23				0x17
-#define DDR0_23_ODT_RD_MAP_CS0_MASK       0x03000000
-#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n)   ((((unsigned long)(n))&0x3)<<24)
-#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n)   ((((unsigned long)(n))>>24)&0x3)
-#define DDR0_23_ECC_C_SYND_MASK           0x00FF0000	/* Read only */
-#define DDR0_23_ECC_C_SYND_ENCODE(n)        ((((unsigned long)(n))&0xFF)<<16)
-#define DDR0_23_ECC_C_SYND_DECODE(n)        ((((unsigned long)(n))>>16)&0xFF)
-#define DDR0_23_ECC_U_SYND_MASK           0x0000FF00	/* Read only */
-#define DDR0_23_ECC_U_SYND_ENCODE(n)        ((((unsigned long)(n))&0xFF)<<8)
-#define DDR0_23_ECC_U_SYND_DECODE(n)        ((((unsigned long)(n))>>8)&0xFF)
-#define DDR0_23_FWC_MASK                  0x00000001	/* Write only */
-#define DDR0_23_FWC_ENCODE(n)               ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_23_FWC_DECODE(n)               ((((unsigned long)(n))>>0)&0x1)
-
-#define DDR0_24				0x18
-#define DDR0_24_RTT_PAD_TERMINATION_MASK  0x03000000
-#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
-#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
-#define DDR0_24_ODT_WR_MAP_CS1_MASK       0x00030000
-#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n)    ((((unsigned long)(n))&0x3)<<16)
-#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n)    ((((unsigned long)(n))>>16)&0x3)
-#define DDR0_24_ODT_RD_MAP_CS1_MASK       0x00000300
-#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n)    ((((unsigned long)(n))&0x3)<<8)
-#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n)    ((((unsigned long)(n))>>8)&0x3)
-#define DDR0_24_ODT_WR_MAP_CS0_MASK       0x00000003
-#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n)    ((((unsigned long)(n))&0x3)<<0)
-#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n)    ((((unsigned long)(n))>>0)&0x3)
-
-#define DDR0_25				0x19
-#define DDR0_25_VERSION_MASK              0xFFFF0000	/* Read only */
-#define DDR0_25_VERSION_ENCODE(n)           ((((unsigned long)(n))&0xFFFF)<<16)
-#define DDR0_25_VERSION_DECODE(n)           ((((unsigned long)(n))>>16)&0xFFFF)
-#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK  0x000003FF	/* Read only */
-#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
-#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
-
-#define DDR0_26				0x1A
-#define DDR0_26_TRAS_MAX_MASK             0xFFFF0000
-#define DDR0_26_TRAS_MAX_ENCODE(n)          ((((unsigned long)(n))&0xFFFF)<<16)
-#define DDR0_26_TRAS_MAX_DECODE(n)          ((((unsigned long)(n))>>16)&0xFFFF)
-#define DDR0_26_TREF_MASK                 0x00003FFF
-#define DDR0_26_TREF_ENCODE(n)              ((((unsigned long)(n))&0x3FFF)<<0)
-#define DDR0_26_TREF_DECODE(n)              ((((unsigned long)(n))>>0)&0x3FFF)
-
-#define DDR0_27				0x1B
-#define DDR0_27_EMRS_DATA_MASK            0x3FFF0000
-#define DDR0_27_EMRS_DATA_ENCODE(n)         ((((unsigned long)(n))&0x3FFF)<<16)
-#define DDR0_27_EMRS_DATA_DECODE(n)         ((((unsigned long)(n))>>16)&0x3FFF)
-#define DDR0_27_TINIT_MASK                0x0000FFFF
-#define DDR0_27_TINIT_ENCODE(n)             ((((unsigned long)(n))&0xFFFF)<<0)
-#define DDR0_27_TINIT_DECODE(n)             ((((unsigned long)(n))>>0)&0xFFFF)
-
-#define DDR0_28				0x1C
-#define DDR0_28_EMRS3_DATA_MASK           0x3FFF0000
-#define DDR0_28_EMRS3_DATA_ENCODE(n)        ((((unsigned long)(n))&0x3FFF)<<16)
-#define DDR0_28_EMRS3_DATA_DECODE(n)        ((((unsigned long)(n))>>16)&0x3FFF)
-#define DDR0_28_EMRS2_DATA_MASK           0x00003FFF
-#define DDR0_28_EMRS2_DATA_ENCODE(n)        ((((unsigned long)(n))&0x3FFF)<<0)
-#define DDR0_28_EMRS2_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0x3FFF)
-
-#define DDR0_31				0x1F
-#define DDR0_31_XOR_CHECK_BITS_MASK       0x0000FFFF
-#define DDR0_31_XOR_CHECK_BITS_ENCODE(n)    ((((unsigned long)(n))&0xFFFF)<<0)
-#define DDR0_31_XOR_CHECK_BITS_DECODE(n)    ((((unsigned long)(n))>>0)&0xFFFF)
-
-#define DDR0_32				0x20
-#define DDR0_32_OUT_OF_RANGE_ADDR_MASK    0xFFFFFFFF	/* Read only */
-#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
-#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_33				0x21
-#define DDR0_33_OUT_OF_RANGE_ADDR_MASK    0x00000001	/* Read only */
-#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n)               ((((unsigned long)(n))>>0)&0x1)
-
-#define DDR0_34				0x22
-#define DDR0_34_ECC_U_ADDR_MASK           0xFFFFFFFF	/* Read only */
-#define DDR0_34_ECC_U_ADDR_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
-#define DDR0_34_ECC_U_ADDR_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_35				0x23
-#define DDR0_35_ECC_U_ADDR_MASK           0x00000001	/* Read only */
-#define DDR0_35_ECC_U_ADDR_ENCODE(n)        ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_35_ECC_U_ADDR_DECODE(n)        ((((unsigned long)(n))>>0)&0x1)
-
-#define DDR0_36				0x24
-#define DDR0_36_ECC_U_DATA_MASK           0xFFFFFFFF	/* Read only */
-#define DDR0_36_ECC_U_DATA_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
-#define DDR0_36_ECC_U_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_37				0x25
-#define DDR0_37_ECC_U_DATA_MASK           0xFFFFFFFF	/* Read only */
-#define DDR0_37_ECC_U_DATA_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
-#define DDR0_37_ECC_U_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_38				0x26
-#define DDR0_38_ECC_C_ADDR_MASK           0xFFFFFFFF	/* Read only */
-#define DDR0_38_ECC_C_ADDR_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
-#define DDR0_38_ECC_C_ADDR_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_39				0x27
-#define DDR0_39_ECC_C_ADDR_MASK           0x00000001	/* Read only */
-#define DDR0_39_ECC_C_ADDR_ENCODE(n)        ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_39_ECC_C_ADDR_DECODE(n)        ((((unsigned long)(n))>>0)&0x1)
-
-#define DDR0_40				0x28
-#define DDR0_40_ECC_C_DATA_MASK           0xFFFFFFFF	/* Read only */
-#define DDR0_40_ECC_C_DATA_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
-#define DDR0_40_ECC_C_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_41				0x29
-#define DDR0_41_ECC_C_DATA_MASK           0xFFFFFFFF	/* Read only */
-#define DDR0_41_ECC_C_DATA_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
-#define DDR0_41_ECC_C_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
-
-#define DDR0_42				0x2A
-#define DDR0_42_ADDR_PINS_MASK            0x07000000
-#define DDR0_42_ADDR_PINS_ENCODE(n)         ((((unsigned long)(n))&0x7)<<24)
-#define DDR0_42_ADDR_PINS_DECODE(n)         ((((unsigned long)(n))>>24)&0x7)
-#define DDR0_42_CASLAT_LIN_GATE_MASK      0x0000000F
-#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n)   ((((unsigned long)(n))&0xF)<<0)
-#define DDR0_42_CASLAT_LIN_GATE_DECODE(n)   ((((unsigned long)(n))>>0)&0xF)
-
-#define DDR0_43				0x2B
-#define DDR0_43_TWR_MASK                  0x07000000
-#define DDR0_43_TWR_ENCODE(n)               ((((unsigned long)(n))&0x7)<<24)
-#define DDR0_43_TWR_DECODE(n)               ((((unsigned long)(n))>>24)&0x7)
-#define DDR0_43_APREBIT_MASK              0x000F0000
-#define DDR0_43_APREBIT_ENCODE(n)           ((((unsigned long)(n))&0xF)<<16)
-#define DDR0_43_APREBIT_DECODE(n)           ((((unsigned long)(n))>>16)&0xF)
-#define DDR0_43_COLUMN_SIZE_MASK          0x00000700
-#define DDR0_43_COLUMN_SIZE_ENCODE(n)       ((((unsigned long)(n))&0x7)<<8)
-#define DDR0_43_COLUMN_SIZE_DECODE(n)       ((((unsigned long)(n))>>8)&0x7)
-#define DDR0_43_EIGHT_BANK_MODE_MASK      0x00000001
-#define DDR0_43_EIGHT_BANK_MODE_8_BANKS     0x00000001
-#define DDR0_43_EIGHT_BANK_MODE_4_BANKS     0x00000000
-#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n)   ((((unsigned long)(n))&0x1)<<0)
-#define DDR0_43_EIGHT_BANK_MODE_DECODE(n)   ((((unsigned long)(n))>>0)&0x1)
-
-#define DDR0_44				0x2C
-#define DDR0_44_TRCD_MASK                 0x000000FF
-#define DDR0_44_TRCD_ENCODE(n)              ((((unsigned long)(n))&0xFF)<<0)
-#define DDR0_44_TRCD_DECODE(n)              ((((unsigned long)(n))>>0)&0xFF)
-
-#endif /* CONFIG_440EPX */
-
 /*-----------------------------------------------------------------------------
  | External Bus Controller
  +----------------------------------------------------------------------------*/
diff --git a/include/ppc4xx.h b/include/ppc4xx.h
index 76fe872..0a8479f 100644
--- a/include/ppc4xx.h
+++ b/include/ppc4xx.h
@@ -22,12 +22,52 @@
 #ifndef	__PPC4XX_H__
 #define __PPC4XX_H__
 
+/*
+ * Configure which SDRAM/DDR/DDR2 controller is equipped
+ */
+#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) || \
+	defined(CONFIG_AP1000) || defined(CONFIG_ML2)
+#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM	/* IBM SDRAM controller */
+#endif
+
+#if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
+    defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#define CONFIG_SDRAM_PPC4xx_IBM_DDR	/* IBM DDR controller */
+#endif
+
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define CONFIG_SDRAM_PPC4xx_DENALI_DDR2	/* Denali DDR(2) controller */
+#endif
+
+#if defined(CONFIG_405EX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define CONFIG_SDRAM_PPC4xx_IBM_DDR2	/* IBM DDR(2) controller */
+#endif
+
 #if defined(CONFIG_440)
 #include <ppc440.h>
 #else
 #include <ppc405.h>
 #endif
 
+#include <asm/ppc4xx-sdram.h>
+
+/*
+ * Macro for generating register field mnemonics
+ */
+#define	PPC_REG_BITS		32
+#define	PPC_REG_VAL(bit, value)	((value) << ((PPC_REG_BITS - 1) - (bit)))
+
+/*
+ * Elide casts when assembling register mnemonics
+ */
+#ifndef __ASSEMBLY__
+#define	static_cast(type, val)	(type)(val)
+#else
+#define	static_cast(type, val)	(val)
+#endif
+
 /*
  * Common stuff for 4xx (405 and 440)
  */