ppc4xx: Big cleanup of PPC4xx defines

This patch cleans up multiple issues of the 4xx register (mostly
DCR, SDR, CPR, etc) definitions:

- Change lower case defines to upper case (plb4_acr -> PLB4_ACR)
- Change the defines to better match the names from the
  user's manuals (e.g. cprpllc -> CPR0_PLLC)
- Removal of some unused defines

Please test this patch intensive on your PPC4xx platform. Even though
I tried not to break anything and tested successfully on multiple
4xx AMCC platforms, testing on custom platforms is recommended.

Signed-off-by: Stefan Roese <sr@denx.de>

5 files changed, 317 insertions, 626 deletions

diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h
index 553845d..40e4735 100644
--- a/include/configs/W7OLMC.h
+++ b/include/configs/W7OLMC.h
@@ -207,9 +207,9 @@
 #define CONFIG_SYS_EBC_PB5CR   0xFD21A000
 
 /* bank 6 is unused */
-/* pb6ap = 0 */
+/* PB6AP = 0 */
 #define CONFIG_SYS_EBC_PB6AP   0x00000000
-/* pb6cr = 0 */
+/* PB6CR = 0 */
 #define CONFIG_SYS_EBC_PB6CR   0x00000000
 
 /* bank 7 is LED register */
diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h
index 73d6d24..a62f1b4 100644
--- a/include/configs/W7OLMG.h
+++ b/include/configs/W7OLMG.h
@@ -214,9 +214,9 @@
 #define CONFIG_SYS_EBC_PB5CR   0xFD87A000
 
 /* bank 6 is unused */
-/* pb6ap = 0 */
+/* PB6AP = 0 */
 #define CONFIG_SYS_EBC_PB6AP   0x00000000
-/* pb6cr = 0 */
+/* PB6CR = 0 */
 #define CONFIG_SYS_EBC_PB6CR   0x00000000
 
 /* bank 7 is LED register */
diff --git a/include/ppc405.h b/include/ppc405.h
index 55649e4..5e56897 100644
--- a/include/ppc405.h
+++ b/include/ppc405.h
@@ -42,54 +42,39 @@
  * DMA
  ******************************************************************************/
 #define DMA_DCR_BASE 0x100
-#define dmacr0	(DMA_DCR_BASE+0x00)  /* DMA channel control register 0	     */
-#define dmact0	(DMA_DCR_BASE+0x01)  /* DMA count register 0		     */
-#define dmada0	(DMA_DCR_BASE+0x02)  /* DMA destination address register 0   */
-#define dmasa0	(DMA_DCR_BASE+0x03)  /* DMA source address register 0	     */
-#define dmasb0	(DMA_DCR_BASE+0x04)  /* DMA scatter/gather descriptor addr 0 */
-#define dmacr1	(DMA_DCR_BASE+0x08)  /* DMA channel control register 1	     */
-#define dmact1	(DMA_DCR_BASE+0x09)  /* DMA count register 1		     */
-#define dmada1	(DMA_DCR_BASE+0x0a)  /* DMA destination address register 1   */
-#define dmasa1	(DMA_DCR_BASE+0x0b)  /* DMA source address register 1	     */
-#define dmasb1	(DMA_DCR_BASE+0x0c)  /* DMA scatter/gather descriptor addr 1 */
-#define dmacr2	(DMA_DCR_BASE+0x10)  /* DMA channel control register 2	     */
-#define dmact2	(DMA_DCR_BASE+0x11)  /* DMA count register 2		     */
-#define dmada2	(DMA_DCR_BASE+0x12)  /* DMA destination address register 2   */
-#define dmasa2	(DMA_DCR_BASE+0x13)  /* DMA source address register 2	     */
-#define dmasb2	(DMA_DCR_BASE+0x14)  /* DMA scatter/gather descriptor addr 2 */
-#define dmacr3	(DMA_DCR_BASE+0x18)  /* DMA channel control register 3	     */
-#define dmact3	(DMA_DCR_BASE+0x19)  /* DMA count register 3		     */
-#define dmada3	(DMA_DCR_BASE+0x1a)  /* DMA destination address register 3   */
-#define dmasa3	(DMA_DCR_BASE+0x1b)  /* DMA source address register 3	     */
-#define dmasb3	(DMA_DCR_BASE+0x1c)  /* DMA scatter/gather descriptor addr 3 */
-#define dmasr	(DMA_DCR_BASE+0x20)  /* DMA status register		     */
-#define dmasgc	(DMA_DCR_BASE+0x23)  /* DMA scatter/gather command register  */
-#define dmaadr	(DMA_DCR_BASE+0x24)  /* DMA address decode register	     */
+#define DMACR0	(DMA_DCR_BASE+0x00)  /* DMA channel control register 0	     */
+#define DMACT0	(DMA_DCR_BASE+0x01)  /* DMA count register 0		     */
+#define DMADA0	(DMA_DCR_BASE+0x02)  /* DMA destination address register 0   */
+#define DMASA0	(DMA_DCR_BASE+0x03)  /* DMA source address register 0	     */
+#define DMASB0	(DMA_DCR_BASE+0x04)  /* DMA scatter/gather descriptor addr 0 */
+#define DMACR1	(DMA_DCR_BASE+0x08)  /* DMA channel control register 1	     */
+#define DMACT1	(DMA_DCR_BASE+0x09)  /* DMA count register 1		     */
+#define DMADA1	(DMA_DCR_BASE+0x0a)  /* DMA destination address register 1   */
+#define DMASA1	(DMA_DCR_BASE+0x0b)  /* DMA source address register 1	     */
+#define DMASB1	(DMA_DCR_BASE+0x0c)  /* DMA scatter/gather descriptor addr 1 */
+#define DMACR2	(DMA_DCR_BASE+0x10)  /* DMA channel control register 2	     */
+#define DMACT2	(DMA_DCR_BASE+0x11)  /* DMA count register 2		     */
+#define DMADA2	(DMA_DCR_BASE+0x12)  /* DMA destination address register 2   */
+#define DMASA2	(DMA_DCR_BASE+0x13)  /* DMA source address register 2	     */
+#define DMASB2	(DMA_DCR_BASE+0x14)  /* DMA scatter/gather descriptor addr 2 */
+#define DMACR3	(DMA_DCR_BASE+0x18)  /* DMA channel control register 3	     */
+#define DMACT3	(DMA_DCR_BASE+0x19)  /* DMA count register 3		     */
+#define DMADA3	(DMA_DCR_BASE+0x1a)  /* DMA destination address register 3   */
+#define DMASA3	(DMA_DCR_BASE+0x1b)  /* DMA source address register 3	     */
+#define DMASB3	(DMA_DCR_BASE+0x1c)  /* DMA scatter/gather descriptor addr 3 */
+#define DMASR	(DMA_DCR_BASE+0x20)  /* DMA status register		     */
+#define DMASGC	(DMA_DCR_BASE+0x23)  /* DMA scatter/gather command register  */
+#define DMAADR	(DMA_DCR_BASE+0x24)  /* DMA address decode register	     */
 
 #ifndef CONFIG_405EP
 /******************************************************************************
  * Decompression Controller
  ******************************************************************************/
 #define DECOMP_DCR_BASE 0x14
-#define kiar  (DECOMP_DCR_BASE+0x0)  /* Decompression controller addr reg    */
-#define kidr  (DECOMP_DCR_BASE+0x1)  /* Decompression controller data reg    */
-  /* values for kiar register - indirect addressing of these regs */
-  #define kitor0      0x00    /* index table origin register 0	      */
-  #define kitor1      0x01    /* index table origin register 1	      */
-  #define kitor2      0x02    /* index table origin register 2	      */
-  #define kitor3      0x03    /* index table origin register 3	      */
-  #define kaddr0      0x04    /* address decode definition regsiter 0 */
-  #define kaddr1      0x05    /* address decode definition regsiter 1 */
-  #define kconf       0x40    /* decompression core config register   */
-  #define kid	      0x41    /* decompression core ID	   register   */
-  #define kver	      0x42    /* decompression core version # reg     */
-  #define kpear       0x50    /* bus error addr reg (PLB addr)	      */
-  #define kbear       0x51    /* bus error addr reg (DCP to EBIU addr)*/
-  #define kesr0       0x52    /* bus error status reg 0  (R/clear)    */
-  #define kesr0s      0x53    /* bus error status reg 0  (set)	      */
-  /* There are 0x400 of the following registers, from krom0 to krom3ff*/
-  /* Only the first one is given here.				      */
-  #define krom0      0x400    /* SRAM/ROM read/write		      */
+#define KIAR  (DECOMP_DCR_BASE+0x0)  /* Decompression controller addr reg    */
+#define KIDR  (DECOMP_DCR_BASE+0x1)  /* Decompression controller data reg    */
+/* values for kiar register - indirect addressing of these regs */
+#define KCONF       0x40    /* decompression core config register   */
 #endif
 
 /******************************************************************************
@@ -100,38 +85,37 @@
 #else
 #define POWERMAN_DCR_BASE 0xb8
 #endif
-#define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status	     */
-#define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable	     */
-#define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force		     */
+#define CPMSR (POWERMAN_DCR_BASE+0x0) /* Power management status	     */
+#define CPMER (POWERMAN_DCR_BASE+0x1) /* Power management enable	     */
+#define CPMFR (POWERMAN_DCR_BASE+0x2) /* Power management force		     */
 
 /******************************************************************************
  * Extrnal Bus Controller
  ******************************************************************************/
-  /* values for ebccfga register - indirect addressing of these regs */
-  #define pb0cr       0x00    /* periph bank 0 config reg	     */
-  #define pb1cr       0x01    /* periph bank 1 config reg	     */
-  #define pb2cr       0x02    /* periph bank 2 config reg	     */
-  #define pb3cr       0x03    /* periph bank 3 config reg	     */
-  #define pb4cr       0x04    /* periph bank 4 config reg	     */
+  /* values for EBC0_CFGADDR register - indirect addressing of these regs */
+  #define PB0CR       0x00    /* periph bank 0 config reg	     */
+  #define PB1CR       0x01    /* periph bank 1 config reg	     */
+  #define PB2CR       0x02    /* periph bank 2 config reg	     */
+  #define PB3CR       0x03    /* periph bank 3 config reg	     */
+  #define PB4CR       0x04    /* periph bank 4 config reg	     */
 #ifndef CONFIG_405EP
-  #define pb5cr       0x05    /* periph bank 5 config reg	     */
-  #define pb6cr       0x06    /* periph bank 6 config reg	     */
-  #define pb7cr       0x07    /* periph bank 7 config reg	     */
+  #define PB5CR       0x05    /* periph bank 5 config reg	     */
+  #define PB6CR       0x06    /* periph bank 6 config reg	     */
+  #define PB7CR       0x07    /* periph bank 7 config reg	     */
 #endif
-  #define pb0ap       0x10    /* periph bank 0 access parameters     */
-  #define pb1ap       0x11    /* periph bank 1 access parameters     */
-  #define pb2ap       0x12    /* periph bank 2 access parameters     */
-  #define pb3ap       0x13    /* periph bank 3 access parameters     */
-  #define pb4ap       0x14    /* periph bank 4 access parameters     */
+  #define PB0AP       0x10    /* periph bank 0 access parameters     */
+  #define PB1AP       0x11    /* periph bank 1 access parameters     */
+  #define PB2AP       0x12    /* periph bank 2 access parameters     */
+  #define PB3AP       0x13    /* periph bank 3 access parameters     */
+  #define PB4AP       0x14    /* periph bank 4 access parameters     */
 #ifndef CONFIG_405EP
-  #define pb5ap       0x15    /* periph bank 5 access parameters     */
-  #define pb6ap       0x16    /* periph bank 6 access parameters     */
-  #define pb7ap       0x17    /* periph bank 7 access parameters     */
+  #define PB5AP       0x15    /* periph bank 5 access parameters     */
+  #define PB6AP       0x16    /* periph bank 6 access parameters     */
+  #define PB7AP       0x17    /* periph bank 7 access parameters     */
 #endif
-  #define pbear       0x20    /* periph bus error addr reg	     */
-  #define pbesr0      0x21    /* periph bus error status reg 0	     */
-  #define pbesr1      0x22    /* periph bus error status reg 1	     */
-  #define epcr	      0x23    /* external periph control reg	     */
+  #define PBEAR       0x20    /* periph bus error addr reg	     */
+  #define PBESR0      0x21    /* periph bus error status reg 0	     */
+  #define PBESR1      0x22    /* periph bus error status reg 1	     */
 #define EBC0_CFG	0x23	/* external bus configuration reg	*/
 
 #ifdef CONFIG_405EP
@@ -139,12 +123,12 @@
  * Control
  ******************************************************************************/
 #define CNTRL_DCR_BASE 0x0f0
-#define cpc0_pllmr0   (CNTRL_DCR_BASE+0x0)  /* PLL mode  register 0		   */
-#define cpc0_boot     (CNTRL_DCR_BASE+0x1)  /* Clock status register		   */
-#define cpc0_epctl    (CNTRL_DCR_BASE+0x3)  /* EMAC to PHY control register	   */
-#define cpc0_pllmr1   (CNTRL_DCR_BASE+0x4)  /* PLL mode  register 1		   */
-#define cpc0_ucr      (CNTRL_DCR_BASE+0x5)  /* UART control register		   */
-#define cpc0_pci      (CNTRL_DCR_BASE+0x9)  /* PCI control register		   */
+#define CPC0_PLLMR0   (CNTRL_DCR_BASE+0x0)  /* PLL mode  register 0		   */
+#define CPC0_BOOT     (CNTRL_DCR_BASE+0x1)  /* Clock status register		   */
+#define CPC0_EPCTL    (CNTRL_DCR_BASE+0x3)  /* EMAC to PHY control register	   */
+#define CPC0_PLLMR1   (CNTRL_DCR_BASE+0x4)  /* PLL mode  register 1		   */
+#define CPC0_UCR      (CNTRL_DCR_BASE+0x5)  /* UART control register		   */
+#define CPC0_PCI      (CNTRL_DCR_BASE+0x9)  /* PCI control register		   */
 
 #define CPC0_PLLMR0  (CNTRL_DCR_BASE+0x0)  /* PLL mode 0 register	   */
 #define CPC0_BOOT    (CNTRL_DCR_BASE+0x1)  /* Chip Clock Status register   */
@@ -401,10 +385,10 @@
 #define VCO_MIN     500
 #define VCO_MAX     1000
 #elif defined(CONFIG_405EZ)
-#define sdrnand0	0x4000
-#define sdrultra0	0x4040
-#define sdrultra1	0x4050
-#define sdricintstat	0x4510
+#define SDR0_NAND0	0x4000
+#define SDR0_ULTRA0	0x4040
+#define SDR0_ULTRA1	0x4050
+#define SDR0_ICINTSTAT	0x4510
 
 #define SDR_NAND0_NDEN		0x80000000
 #define SDR_NAND0_NDBTEN	0x40000000
@@ -429,21 +413,19 @@
 #define SDR_ICTX0_STAT	0x40000000
 #define SDR_ICTX1_STAT	0x20000000
 
-#define SDR_PINSTP	0x40
+#define SDR0_PINSTP	0x40
 
 /******************************************************************************
  * Control
  ******************************************************************************/
 /* CPR Registers */
-#define cprclkupd	0x020		/* CPR_CLKUPD */
-#define cprpllc		0x040		/* CPR_PLLC */
-#define cprplld		0x060		/* CPR_PLLD */
-#define cprprimad	0x080		/* CPR_PRIMAD */
-#define cprperd0	0x0e0		/* CPR_PERD0 */
-#define cprperd1	0x0e1		/* CPR_PERD1 */
-#define cprperc0	0x180		/* CPR_PERC0 */
-#define cprmisc0	0x181		/* CPR_MISC0 */
-#define cprmisc1	0x182		/* CPR_MISC1 */
+#define CPR0_CLKUP	0x020		/* CPR_CLKUPD */
+#define CPR0_PLLC		0x040		/* CPR_PLLC */
+#define CPR0_PLLD		0x060		/* CPR_PLLD */
+#define CPC0_PRIMAD	0x080		/* CPR_PRIMAD */
+#define CPC0_PERD0	0x0e0		/* CPR_PERD0 */
+#define CPC0_PERD1	0x0e1		/* CPR_PERD1 */
+#define CPC0_PERC0	0x180		/* CPR_PERC0 */
 
 #define CPR_CLKUPD_ENPLLCH_EN  0x40000000     /* Enable CPR PLL Changes */
 #define CPR_CLKUPD_ENDVCH_EN   0x20000000     /* Enable CPR Sys. Div. Changes */
@@ -470,21 +452,14 @@
  * Control
  ******************************************************************************/
 #define CNTRL_DCR_BASE 0x0b0
-#define pllmd	(CNTRL_DCR_BASE+0x0)  /* PLL mode  register		     */
-#define cntrl0	(CNTRL_DCR_BASE+0x1)  /* Control 0 register		     */
-#define cntrl1	(CNTRL_DCR_BASE+0x2)  /* Control 1 register		     */
-#define reset	(CNTRL_DCR_BASE+0x3)  /* reset register			     */
-#define strap	(CNTRL_DCR_BASE+0x4)  /* strap register			     */
-
-#define CPC0_CR0  (CNTRL_DCR_BASE+0x1)	/* chip control register 0	     */
-#define CPC0_CR1  (CNTRL_DCR_BASE+0x2)	/* chip control register 1	     */
-#define CPC0_PSR  (CNTRL_DCR_BASE+0x4)	/* chip pin strapping register	     */
+#define CPC0_PLLMR	(CNTRL_DCR_BASE + 0x0)	/* PLL mode  register */
+#define CPC0_CR0	(CNTRL_DCR_BASE + 0x1)	/* chip control register 0 */
+#define CPC0_CR1	(CNTRL_DCR_BASE + 0x2)	/* chip control register 1 */
+#define CPC0_PSR	(CNTRL_DCR_BASE + 0x4)	/* chip pin strapping reg */
 
 /* CPC0_ECR/CPC0_EIRR: PPC405GPr only */
-#define CPC0_EIRR (CNTRL_DCR_BASE+0x6)	/* external interrupt routing register */
-#define CPC0_ECR  (0xaa)		/* edge conditioner register */
-
-#define ecr	(0xaa)		      /* edge conditioner register (405gpr)  */
+#define CPC0_EIRR	(CNTRL_DCR_BASE + 0x6)	/* ext interrupt routing reg */
+#define CPC0_ECR	0xaa			/* edge conditioner register */
 
 /* Bit definitions */
 #define PLLMR_FWD_DIV_MASK	0xE0000000     /* Forward Divisor */
@@ -557,140 +532,38 @@
  ******************************************************************************/
 #if defined(CONFIG_405EZ)
 #define	MAL_DCR_BASE	0x380
-#define	malmcr		(MAL_DCR_BASE+0x00)	/* MAL Config reg	      */
-#define	malesr		(MAL_DCR_BASE+0x01)	/* Err Status reg (Read/Clear)*/
-#define	malier		(MAL_DCR_BASE+0x02)	/* Interrupt enable reg	      */
-#define	maldbr		(MAL_DCR_BASE+0x03)	/* Mal Debug reg (Read only)  */
-#define	maltxcasr	(MAL_DCR_BASE+0x04)	/* TX Channel active reg (set)*/
-#define	maltxcarr	(MAL_DCR_BASE+0x05)	/* TX Channel active reg (Reset)     */
-#define	maltxeobisr	(MAL_DCR_BASE+0x06)	/* TX End of buffer int status reg   */
-#define	maltxdeir	(MAL_DCR_BASE+0x07)	/* TX Descr. Error Int reg    */
-/*				      0x08-0x0F	   Reserved		      */
-#define	malrxcasr	(MAL_DCR_BASE+0x10)	/* RX Channel active reg (set)*/
-#define	malrxcarr	(MAL_DCR_BASE+0x11)	/* RX Channel active reg (Reset)     */
-#define	malrxeobisr	(MAL_DCR_BASE+0x12)	/* RX End of buffer int status reg   */
-#define	malrxdeir	(MAL_DCR_BASE+0x13)	/* RX Descr. Error Int reg  */
-/*				      0x14-0x1F	   Reserved		    */
-#define	maltxctp0r	(MAL_DCR_BASE+0x20)  /* TX 0 Channel table ptr reg  */
-#define	maltxctp1r	(MAL_DCR_BASE+0x21)  /* TX 1 Channel table ptr reg  */
-#define	maltxctp2r	(MAL_DCR_BASE+0x22)  /* TX 2 Channel table ptr reg  */
-#define	maltxctp3r	(MAL_DCR_BASE+0x23)  /* TX 3 Channel table ptr reg  */
-#define	maltxctp4r	(MAL_DCR_BASE+0x24)  /* TX 4 Channel table ptr reg  */
-#define	maltxctp5r	(MAL_DCR_BASE+0x25)  /* TX 5 Channel table ptr reg  */
-#define	maltxctp6r	(MAL_DCR_BASE+0x26)  /* TX 6 Channel table ptr reg  */
-#define	maltxctp7r	(MAL_DCR_BASE+0x27)  /* TX 7 Channel table ptr reg  */
-#define	maltxctp8r	(MAL_DCR_BASE+0x28)  /* TX 8 Channel table ptr reg  */
-#define	maltxctp9r	(MAL_DCR_BASE+0x29)  /* TX 9 Channel table ptr reg  */
-#define	maltxctp10r	(MAL_DCR_BASE+0x2A)  /* TX 10 Channel table ptr reg */
-#define	maltxctp11r	(MAL_DCR_BASE+0x2B)  /* TX 11 Channel table ptr reg */
-#define	maltxctp12r	(MAL_DCR_BASE+0x2C)  /* TX 12 Channel table ptr reg */
-#define	maltxctp13r	(MAL_DCR_BASE+0x2D)  /* TX 13 Channel table ptr reg */
-#define	maltxctp14r	(MAL_DCR_BASE+0x2E)  /* TX 14 Channel table ptr reg */
-#define	maltxctp15r	(MAL_DCR_BASE+0x2F)  /* TX 15 Channel table ptr reg */
-#define	maltxctp16r	(MAL_DCR_BASE+0x30)  /* TX 16 Channel table ptr reg */
-#define	maltxctp17r	(MAL_DCR_BASE+0x31)  /* TX 17 Channel table ptr reg */
-#define	maltxctp18r	(MAL_DCR_BASE+0x32)  /* TX 18 Channel table ptr reg */
-#define	maltxctp19r	(MAL_DCR_BASE+0x33)  /* TX 19 Channel table ptr reg */
-#define	maltxctp20r	(MAL_DCR_BASE+0x34)  /* TX 20 Channel table ptr reg */
-#define	maltxctp21r	(MAL_DCR_BASE+0x35)  /* TX 21 Channel table ptr reg */
-#define	maltxctp22r	(MAL_DCR_BASE+0x36)  /* TX 22 Channel table ptr reg */
-#define	maltxctp23r	(MAL_DCR_BASE+0x37)  /* TX 23 Channel table ptr reg */
-#define	maltxctp24r	(MAL_DCR_BASE+0x38)  /* TX 24 Channel table ptr reg */
-#define	maltxctp25r	(MAL_DCR_BASE+0x39)  /* TX 25 Channel table ptr reg */
-#define	maltxctp26r	(MAL_DCR_BASE+0x3A)  /* TX 26 Channel table ptr reg */
-#define	maltxctp27r	(MAL_DCR_BASE+0x3B)  /* TX 27 Channel table ptr reg */
-#define	maltxctp28r	(MAL_DCR_BASE+0x3C)  /* TX 28 Channel table ptr reg */
-#define	maltxctp29r	(MAL_DCR_BASE+0x3D)  /* TX 29 Channel table ptr reg */
-#define	maltxctp30r	(MAL_DCR_BASE+0x3E)  /* TX 30 Channel table ptr reg */
-#define	maltxctp31r	(MAL_DCR_BASE+0x3F)  /* TX 31 Channel table ptr reg */
-#define	malrxctp0r	(MAL_DCR_BASE+0x40)  /* RX 0 Channel table ptr reg  */
-#define	malrxctp1r	(MAL_DCR_BASE+0x41)  /* RX 1 Channel table ptr reg  */
-#define	malrxctp2r	(MAL_DCR_BASE+0x42)  /* RX 2 Channel table ptr reg  */
-#define	malrxctp3r	(MAL_DCR_BASE+0x43)  /* RX 3 Channel table ptr reg  */
-#define	malrxctp4r	(MAL_DCR_BASE+0x44)  /* RX 4 Channel table ptr reg  */
-#define	malrxctp5r	(MAL_DCR_BASE+0x45)  /* RX 5 Channel table ptr reg  */
-#define	malrxctp6r	(MAL_DCR_BASE+0x46)  /* RX 6 Channel table ptr reg  */
-#define	malrxctp7r	(MAL_DCR_BASE+0x47)  /* RX 7 Channel table ptr reg  */
-#define	malrxctp8r	(MAL_DCR_BASE+0x48)  /* RX 8 Channel table ptr reg  */
-#define	malrxctp9r	(MAL_DCR_BASE+0x49)  /* RX 9 Channel table ptr reg  */
-#define	malrxctp10r	(MAL_DCR_BASE+0x4A)  /* RX 10 Channel table ptr reg */
-#define	malrxctp11r	(MAL_DCR_BASE+0x4B)  /* RX 11 Channel table ptr reg */
-#define	malrxctp12r	(MAL_DCR_BASE+0x4C)  /* RX 12 Channel table ptr reg */
-#define	malrxctp13r	(MAL_DCR_BASE+0x4D)  /* RX 13 Channel table ptr reg */
-#define	malrxctp14r	(MAL_DCR_BASE+0x4E)  /* RX 14 Channel table ptr reg */
-#define	malrxctp15r	(MAL_DCR_BASE+0x4F)  /* RX 15 Channel table ptr reg */
-#define	malrxctp16r	(MAL_DCR_BASE+0x50)  /* RX 16 Channel table ptr reg */
-#define	malrxctp17r	(MAL_DCR_BASE+0x51)  /* RX 17 Channel table ptr reg */
-#define	malrxctp18r	(MAL_DCR_BASE+0x52)  /* RX 18 Channel table ptr reg */
-#define	malrxctp19r	(MAL_DCR_BASE+0x53)  /* RX 19 Channel table ptr reg */
-#define	malrxctp20r	(MAL_DCR_BASE+0x54)  /* RX 20 Channel table ptr reg */
-#define	malrxctp21r	(MAL_DCR_BASE+0x55)  /* RX 21 Channel table ptr reg */
-#define	malrxctp22r	(MAL_DCR_BASE+0x56)  /* RX 22 Channel table ptr reg */
-#define	malrxctp23r	(MAL_DCR_BASE+0x57)  /* RX 23 Channel table ptr reg */
-#define	malrxctp24r	(MAL_DCR_BASE+0x58)  /* RX 24 Channel table ptr reg */
-#define	malrxctp25r	(MAL_DCR_BASE+0x59)  /* RX 25 Channel table ptr reg */
-#define	malrxctp26r	(MAL_DCR_BASE+0x5A)  /* RX 26 Channel table ptr reg */
-#define	malrxctp27r	(MAL_DCR_BASE+0x5B)  /* RX 27 Channel table ptr reg */
-#define	malrxctp28r	(MAL_DCR_BASE+0x5C)  /* RX 28 Channel table ptr reg */
-#define	malrxctp29r	(MAL_DCR_BASE+0x5D)  /* RX 29 Channel table ptr reg */
-#define	malrxctp30r	(MAL_DCR_BASE+0x5E)  /* RX 30 Channel table ptr reg */
-#define	malrxctp31r	(MAL_DCR_BASE+0x5F)  /* RX 31 Channel table ptr reg */
-#define	malrcbs0	(MAL_DCR_BASE+0x60)  /* RX 0 Channel buffer size reg */
-#define	malrcbs1	(MAL_DCR_BASE+0x61)  /* RX 1 Channel buffer size reg */
-#define	malrcbs2	(MAL_DCR_BASE+0x62)  /* RX 2 Channel buffer size reg */
-#define	malrcbs3	(MAL_DCR_BASE+0x63)  /* RX 3 Channel buffer size reg */
-#define	malrcbs4	(MAL_DCR_BASE+0x64)  /* RX 4 Channel buffer size reg */
-#define	malrcbs5	(MAL_DCR_BASE+0x65)  /* RX 5 Channel buffer size reg */
-#define	malrcbs6	(MAL_DCR_BASE+0x66)  /* RX 6 Channel buffer size reg */
-#define	malrcbs7	(MAL_DCR_BASE+0x67)  /* RX 7 Channel buffer size reg */
-#define	malrcbs8	(MAL_DCR_BASE+0x68)  /* RX 8 Channel buffer size reg */
-#define	malrcbs9	(MAL_DCR_BASE+0x69)  /* RX 9 Channel buffer size reg */
-#define	malrcbs10	(MAL_DCR_BASE+0x6A)  /* RX 10 Channel buffer size reg */
-#define	malrcbs11	(MAL_DCR_BASE+0x6B)  /* RX 11 Channel buffer size reg */
-#define	malrcbs12	(MAL_DCR_BASE+0x6C)  /* RX 12 Channel buffer size reg */
-#define	malrcbs13	(MAL_DCR_BASE+0x6D)  /* RX 13 Channel buffer size reg */
-#define	malrcbs14	(MAL_DCR_BASE+0x6E)  /* RX 14 Channel buffer size reg */
-#define	malrcbs15	(MAL_DCR_BASE+0x6F)  /* RX 15 Channel buffer size reg */
-#define	malrcbs16	(MAL_DCR_BASE+0x70)  /* RX 16 Channel buffer size reg */
-#define	malrcbs17	(MAL_DCR_BASE+0x71)  /* RX 17 Channel buffer size reg */
-#define	malrcbs18	(MAL_DCR_BASE+0x72)  /* RX 18 Channel buffer size reg */
-#define	malrcbs19	(MAL_DCR_BASE+0x73)  /* RX 19 Channel buffer size reg */
-#define	malrcbs20	(MAL_DCR_BASE+0x74)  /* RX 20 Channel buffer size reg */
-#define	malrcbs21	(MAL_DCR_BASE+0x75)  /* RX 21 Channel buffer size reg */
-#define	malrcbs22	(MAL_DCR_BASE+0x76)  /* RX 22 Channel buffer size reg */
-#define	malrcbs23	(MAL_DCR_BASE+0x77)  /* RX 23 Channel buffer size reg */
-#define	malrcbs24	(MAL_DCR_BASE+0x78)  /* RX 24 Channel buffer size reg */
-#define	malrcbs25	(MAL_DCR_BASE+0x79)  /* RX 25 Channel buffer size reg */
-#define	malrcbs26	(MAL_DCR_BASE+0x7A)  /* RX 26 Channel buffer size reg */
-#define	malrcbs27	(MAL_DCR_BASE+0x7B)  /* RX 27 Channel buffer size reg */
-#define	malrcbs28	(MAL_DCR_BASE+0x7C)  /* RX 28 Channel buffer size reg */
-#define	malrcbs29	(MAL_DCR_BASE+0x7D)  /* RX 29 Channel buffer size reg */
-#define	malrcbs30	(MAL_DCR_BASE+0x7E)  /* RX 30 Channel buffer size reg */
-#define	malrcbs31	(MAL_DCR_BASE+0x7F)  /* RX 31 Channel buffer size reg */
-
-#else /* !defined(CONFIG_405EZ) */
-
-#define MAL_DCR_BASE 0x180
-#define malmcr	(MAL_DCR_BASE+0x00)  /* MAL Config reg			     */
-#define malesr	(MAL_DCR_BASE+0x01)  /* Error Status reg (Read/Clear)	     */
-#define malier	(MAL_DCR_BASE+0x02)  /* Interrupt enable reg		     */
-#define maldbr	(MAL_DCR_BASE+0x03)  /* Mal Debug reg (Read only)	     */
-#define maltxcasr  (MAL_DCR_BASE+0x04)	/* TX Channel active reg (set)	     */
-#define maltxcarr  (MAL_DCR_BASE+0x05)	/* TX Channel active reg (Reset)     */
-#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg   */
-#define maltxdeir  (MAL_DCR_BASE+0x07)	/* TX Descr. Error Int reg	     */
-#define malrxcasr  (MAL_DCR_BASE+0x10)	/* RX Channel active reg (set)	     */
-#define malrxcarr  (MAL_DCR_BASE+0x11)	/* RX Channel active reg (Reset)     */
-#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg   */
-#define malrxdeir  (MAL_DCR_BASE+0x13)	/* RX Descr. Error Int reg	     */
-#define maltxctp0r (MAL_DCR_BASE+0x20)	/* TX 0 Channel table pointer reg    */
-#define maltxctp1r (MAL_DCR_BASE+0x21)	/* TX 1 Channel table pointer reg    */
-#define maltxctp2r (MAL_DCR_BASE+0x22)	/* TX 2 Channel table pointer reg    */
-#define malrxctp0r (MAL_DCR_BASE+0x40)	/* RX 0 Channel table pointer reg    */
-#define malrxctp1r (MAL_DCR_BASE+0x41)	/* RX 1 Channel table pointer reg    */
-#define malrcbs0   (MAL_DCR_BASE+0x60)	/* RX 0 Channel buffer size reg      */
-#define malrcbs1   (MAL_DCR_BASE+0x61)	/* RX 1 Channel buffer size reg      */
-#endif /* defined(CONFIG_405EZ) */
+#else
+#define MAL_DCR_BASE	0x180
+#endif
+#define	MAL0_CFG	(MAL_DCR_BASE + 0x00)	/* MAL Config reg */
+#define	MAL0_ESR	(MAL_DCR_BASE + 0x01)	/* Err Status (Read/Clear)*/
+#define	MAL0_IER	(MAL_DCR_BASE + 0x02)	/* Interrupt enable */
+#define	MAL0_TXCASR	(MAL_DCR_BASE + 0x04)	/* TX Channel active (set)*/
+#define	MAL0_TXCARR	(MAL_DCR_BASE + 0x05)	/* TX Channel active (reset)*/
+#define	MAL0_TXEOBISR	(MAL_DCR_BASE + 0x06)	/* TX End of buffer int status*/
+#define	MAL0_TXDEIR	(MAL_DCR_BASE + 0x07)	/* TX Descr. Error Int reg */
+#define	MAL0_RXCASR	(MAL_DCR_BASE + 0x10)	/* RX Channel active (set) */
+#define	MAL0_RXCARR	(MAL_DCR_BASE + 0x11)	/* RX Channel active (reset) */
+#define	MAL0_RXEOBISR	(MAL_DCR_BASE + 0x12)	/* RX End of buffer int status*/
+#define	MAL0_RXDEIR	(MAL_DCR_BASE + 0x13)	/* RX Descr. Error Int reg */
+#define	MAL0_TXCTP0R	(MAL_DCR_BASE + 0x20)	/* TX 0 Channel table ptr */
+#define	MAL0_TXCTP1R	(MAL_DCR_BASE + 0x21)	/* TX 1 Channel table ptr */
+#define	MAL0_TXCTP2R	(MAL_DCR_BASE + 0x22)	/* TX 2 Channel table ptr */
+#define	MAL0_TXCTP3R	(MAL_DCR_BASE + 0x23)	/* TX 3 Channel table ptr */
+#define	MAL0_RXCTP0R	(MAL_DCR_BASE + 0x40)	/* RX 0 Channel table ptr */
+#define	MAL0_RXCTP1R	(MAL_DCR_BASE + 0x41)	/* RX 1 Channel table ptr */
+#define	MAL0_RXCTP2R	(MAL_DCR_BASE + 0x42)	/* RX 2 Channel table ptr */
+#define	MAL0_RXCTP3R	(MAL_DCR_BASE + 0x43)	/* RX 3 Channel table ptr */
+#define	MAL0_RXCTP8R	(MAL_DCR_BASE + 0x48)	/* RX 8 Channel table ptr */
+#define	MAL0_RXCTP16R	(MAL_DCR_BASE + 0x50)	/* RX 16 Channel table ptr */
+#define	MAL0_RXCTP24R	(MAL_DCR_BASE + 0x58)	/* RX 24 Channel table ptr */
+#define	MAL0_RCBS0	(MAL_DCR_BASE + 0x60)	/* RX 0 Channel buffer size */
+#define	MAL0_RCBS1	(MAL_DCR_BASE + 0x61)	/* RX 1 Channel buffer size */
+#define	MAL0_RCBS2	(MAL_DCR_BASE + 0x62)	/* RX 2 Channel buffer size */
+#define	MAL0_RCBS3	(MAL_DCR_BASE + 0x63)	/* RX 3 Channel buffer size */
+#define	MAL0_RCBS8	(MAL_DCR_BASE + 0x68)	/* RX 8 Channel buffer size */
+#define	MAL0_RCBS16	(MAL_DCR_BASE + 0x70)	/* RX 16 Channel buffer size */
+#define	MAL0_RCBS24	(MAL_DCR_BASE + 0x78)	/* RX 24 Channel buffer size */
 
 /*-----------------------------------------------------------------------------
 | IIC Register Offsets
@@ -730,27 +603,19 @@
  ******************************************************************************/
 #if defined(CONFIG_405EZ)
 #define OCM_DCR_BASE 0x020
-#define ocmplb3cr1	(OCM_DCR_BASE+0x00)  /* OCM PLB3 Bank 1 Config Reg    */
-#define ocmplb3cr2	(OCM_DCR_BASE+0x01)  /* OCM PLB3 Bank 2 Config Reg    */
-#define ocmplb3bear	(OCM_DCR_BASE+0x02)  /* OCM PLB3 Bus Error Add Reg    */
-#define ocmplb3besr0	(OCM_DCR_BASE+0x03)  /* OCM PLB3 Bus Error Stat Reg 0 */
-#define ocmplb3besr1	(OCM_DCR_BASE+0x04)  /* OCM PLB3 Bus Error Stat Reg 1 */
-#define ocmcid		(OCM_DCR_BASE+0x05)  /* OCM Core ID		      */
-#define ocmrevid	(OCM_DCR_BASE+0x06)  /* OCM Revision ID		      */
-#define ocmplb3dpc	(OCM_DCR_BASE+0x07)  /* OCM PLB3 Data Parity Check    */
-#define ocmdscr1	(OCM_DCR_BASE+0x08)  /* OCM D-side Bank 1 Config Reg  */
-#define ocmdscr2	(OCM_DCR_BASE+0x09)  /* OCM D-side Bank 2 Config Reg  */
-#define ocmiscr1	(OCM_DCR_BASE+0x0A)  /* OCM I-side Bank 1 Config Reg  */
-#define ocmiscr2	(OCM_DCR_BASE+0x0B)  /* OCM I-side Bank 2 Config Reg  */
-#define ocmdsisdpc	(OCM_DCR_BASE+0x0C)  /* OCM D-side/I-side Data Par Chk*/
-#define ocmdsisbear	(OCM_DCR_BASE+0x0D)  /* OCM D-side/I-side Bus Err Addr*/
-#define ocmdsisbesr	(OCM_DCR_BASE+0x0E)  /* OCM D-side/I-side Bus Err Stat*/
+#define OCM0_PLBCR1	(OCM_DCR_BASE + 0x00)	/* OCM PLB3 Bank 1 Config */
+#define OCM0_PLBCR2	(OCM_DCR_BASE + 0x01)	/* OCM PLB3 Bank 2 Config */
+#define OCM0_PLBBEAR	(OCM_DCR_BASE + 0x02)	/* OCM PLB3 Bus Error Add */
+#define OCM0_DSRC1	(OCM_DCR_BASE + 0x08)	/* OCM D-side Bank 1 Config */
+#define OCM0_DSRC2	(OCM_DCR_BASE + 0x09)	/* OCM D-side Bank 2 Config */
+#define OCM0_ISRC1	(OCM_DCR_BASE + 0x0A)	/* OCM I-side Bank 1Config */
+#define OCM0_ISRC2	(OCM_DCR_BASE + 0x0B)	/* OCM I-side Bank 2 Config */
+#define OCM0_DISDPC	(OCM_DCR_BASE + 0x0C)	/* OCM D-/I-side Data Par Chk*/
 #else
 #define OCM_DCR_BASE 0x018
-#define ocmisarc   (OCM_DCR_BASE+0x00)	/* OCM I-side address compare reg    */
-#define ocmiscntl  (OCM_DCR_BASE+0x01)	/* OCM I-side control reg	     */
-#define ocmdsarc   (OCM_DCR_BASE+0x02)	/* OCM D-side address compare reg    */
-#define ocmdscntl  (OCM_DCR_BASE+0x03)	/* OCM D-side control reg	     */
+#define OCM0_ISCNTL	(OCM_DCR_BASE+0x01)	/* OCM I-side control reg */
+#define OCM0_DSARC	(OCM_DCR_BASE+0x02)	/* OCM D-side address compare */
+#define OCM0_DSCNTL	(OCM_DCR_BASE+0x03)	/* OCM D-side control */
 #endif /* CONFIG_405EZ */
 
 /******************************************************************************
@@ -876,9 +741,9 @@
 #define SDR0_SRST_AHB		PPC_REG_VAL(30, 1)
 #define SDR0_SRST_NDFC		PPC_REG_VAL(31, 1)
 
-#define sdr_uart0	0x0120	/* UART0 Config */
-#define sdr_uart1	0x0121	/* UART1 Config */
-#define sdr_mfr		0x4300	/* SDR0_MFR reg */
+#define SDR0_UART0		0x0120	/* UART0 Config */
+#define SDR0_UART1		0x0121	/* UART1 Config */
+#define SDR0_MFR		0x4300	/* SDR0_MFR reg */
 
 /* Defines for CPC0_EPRCSR register */
 #define CPC0_EPRCSR_E0NFE	   0x80000000
@@ -890,18 +755,16 @@
 #define CPC0_EPRCSR_E1PCI	   0x00000002
 #define CPC0_EPRCSR_E0PCI	   0x00000001
 
-#define cpr0_clkupd	0x020
-#define cpr0_pllc	0x040
-#define cpr0_plld	0x060
-#define cpr0_cpud	0x080
-#define cpr0_plbd	0x0a0
-#define cpr0_opbd	0x0c0
-#define cpr0_perd	0x0e0
-#define cpr0_ahbd	0x100
-#define cpr0_icfg	0x140
-
-#define SDR_PINSTP	0x0040
-#define sdr_sdcs	0x0060
+#define CPR0_CLKUPD	0x020
+#define CPR0_PLLC	0x040
+#define CPR0_PLLD	0x060
+#define CPR0_CPUD	0x080
+#define CPR0_PLBD	0x0a0
+#define CPR0_OPBD	0x0c0
+#define CPR0_PERD	0x0e0
+
+#define SDR0_PINSTP	0x0040
+#define SDR0_SDCS0	0x0060
 
 #define SDR0_SDCS_SDD			(0x80000000 >> 31)
 
diff --git a/include/ppc440.h b/include/ppc440.h
index 7f34fda..378a9de 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -58,64 +58,55 @@
  | Clocking Controller
  +----------------------------------------------------------------------------*/
 /* values for clkcfga register - indirect addressing of these regs */
-#define clk_clkukpd	0x0020
-#define clk_pllc	0x0040
-#define clk_plld	0x0060
-#define clk_primad	0x0080
-#define clk_primbd	0x00a0
-#define clk_opbd	0x00c0
-#define clk_perd	0x00e0
-#define clk_mald	0x0100
-#define clk_spcid	0x0120
-#define clk_icfg	0x0140
+#define CPR0_PLLC	0x0040
+#define CPR0_PLLD	0x0060
+#define CPR0_PRIMAD	0x0080
+#define CPR0_PRIMBD	0x00a0
+#define CPR0_OPBD	0x00c0
+#define CPR0_PERD	0x00e0
+#define CPR0_MALD	0x0100
+#define CPR0_SPCID	0x0120
+#define CPR0_ICFG	0x0140
 
 /* 440gx sdr register definations */
-#define sdr_sdstp0	0x0020	    /* */
-#define sdr_sdstp1	0x0021	    /* */
-#define SDR_PINSTP	0x0040
-#define sdr_sdcs	0x0060
-#define sdr_ecid0	0x0080
-#define sdr_ecid1	0x0081
-#define sdr_ecid2	0x0082
-#define sdr_jtag	0x00c0
+#define SDR0_SDSTP0	0x0020	    /* */
+#define SDR0_SDSTP1	0x0021	    /* */
+#define SDR0_PINSTP	0x0040
+#define SDR0_SDCS0	0x0060
 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define SDR0_DDRCFG	0x00e0
 #endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */
-#define sdr_ebc		0x0100
-#define sdr_uart0	0x0120	/* UART0 Config */
-#define sdr_uart1	0x0121	/* UART1 Config */
-#define sdr_uart2	0x0122	/* UART2 Config */
-#define sdr_uart3	0x0123	/* UART3 Config */
-#define sdr_cp440	0x0180
-#define sdr_xcr		0x01c0
-#define sdr_xpllc	0x01c1
-#define sdr_xplld	0x01c2
-#define sdr_srst	0x0200
-#define sdr_slpipe	0x0220
-#define sdr_amp0        0x0240  /* Override PLB4 prioritiy for up to 8 masters */
-#define sdr_amp1        0x0241  /* Override PLB3 prioritiy for up to 8 masters */
-#define sdr_mirq0	0x0260
-#define sdr_mirq1	0x0261
-#define sdr_maltbl	0x0280
-#define sdr_malrbl	0x02a0
-#define sdr_maltbs	0x02c0
-#define sdr_malrbs	0x02e0
-#define sdr_pci0	0x0300
-#define sdr_usb0	0x0320
-#define sdr_cust0	0x4000
-#define sdr_cust1	0x4002
-#define sdr_pfc0	0x4100	/* Pin Function 0 */
-#define sdr_pfc1	0x4101	/* Pin Function 1 */
-#define sdr_plbtr	0x4200
-#define sdr_mfr		0x4300	/* SDR0_MFR reg */
+#define SDR0_EBC	0x0100
+#define SDR0_UART0	0x0120	/* UART0 Config */
+#define SDR0_UART1	0x0121	/* UART1 Config */
+#define SDR0_UART2	0x0122	/* UART2 Config */
+#define SDR0_UART3	0x0123	/* UART3 Config */
+#define SDR0_CP440	0x0180
+#define SDR0_XCR	0x01c0
+#define SDR0_XPLLC	0x01c1
+#define SDR0_XPLLD	0x01c2
+#define SDR0_SRST	0x0200
+#define SD0_AMP0        0x0240  /* Override PLB4 prioritiy for up to 8 masters */
+#define SD0_AMP1        0x0241  /* Override PLB3 prioritiy for up to 8 masters */
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define SDR0_PCI0	0x01c0
+#else
+#define SDR0_PCI0	0x0300
+#endif
+#define SDR0_USB0	0x0320
+#define SDR0_CUST0	0x4000
+#define SDR0_CUST1	0x4002
+#define SDR0_PFC0	0x4100	/* Pin Function 0 */
+#define SDR0_PFC1	0x4101	/* Pin Function 1 */
+#define SDR0_MFR	0x4300	/* SDR0_MFR reg */
 
 #ifdef CONFIG_440GX
-#define sdr_amp		0x0240
-#define sdr_xpllc	0x01c1
-#define sdr_xplld	0x01c2
-#define sdr_xcr		0x01c0
-#define sdr_sdstp2	0x4001
-#define sdr_sdstp3	0x4003
+#define SD0_AMP		0x0240
+#define SDR0_XPLLC	0x01c1
+#define SDR0_XPLLD	0x01c2
+#define SDR0_XCR	0x01c0
+#define SDR0_SDSTP2	0x4001
+#define SDR0_SDSTP3	0x4003
 #endif	/* CONFIG_440GX */
 
 /*----------------------------------------------------------------------------+
@@ -143,101 +134,66 @@
 #define MMUCR_STID_MASK		0x000000FF
 
 #ifdef CONFIG_440SPE
-#undef sdr_sdstp2
-#define sdr_sdstp2	0x0022
-#undef sdr_sdstp3
-#define sdr_sdstp3	0x0023
-#define sdr_ddr0	0x00E1
-#define sdr_uart2	0x0122
-#define sdr_xcr0	0x01c0
-/* #define sdr_xcr1	0x01c3	only one PCIX - SG */
-/* #define sdr_xcr2	0x01c6	only one PCIX - SG */
-#define sdr_xpllc0	0x01c1
-#define sdr_xplld0	0x01c2
-#define sdr_xpllc1	0x01c4	/*notRCW  - SG */
-#define sdr_xplld1	0x01c5	/*notRCW  - SG */
-#define sdr_xpllc2	0x01c7	/*notRCW  - SG */
-#define sdr_xplld2	0x01c8	/*notRCW  - SG */
-#define sdr_amp0	0x0240
-#define sdr_amp1	0x0241
-#define sdr_cust2	0x4004
-#define sdr_cust3	0x4006
-#define sdr_sdstp4	0x4001
-#define sdr_sdstp5	0x4003
-#define sdr_sdstp6	0x4005
-#define sdr_sdstp7	0x4007
+#undef SDR0_SDSTP2
+#define SDR0_SDSTP2	0x0022
+#undef SDR0_SDSTP3
+#define SDR0_SDSTP3	0x0023
+#define SDR0_DDR0	0x00E1
+#define SDR0_UART2	0x0122
+#define SDR0_XCR0	0x01c0
+#define SDR0_XCR1	0x01c3
+#define SDR0_XCR2	0x01c6
+#define SDR0_XPLLC0	0x01c1
+#define SDR0_XPLLD0	0x01c2
+#define SDR0_XPLLC1	0x01c4	/*notRCW  - SG */
+#define SDR0_XPLLD1	0x01c5	/*notRCW  - SG */
+#define SDR0_XPLLC2	0x01c7	/*notRCW  - SG */
+#define SDR0_XPLLD2	0x01c8	/*notRCW  - SG */
+#define SD0_AMP0	0x0240
+#define SD0_AMP1	0x0241
+#define SDR0_CUST2	0x4004
+#define SDR0_CUST3	0x4006
+#define SDR0_SDSTP4	0x4001
+#define SDR0_SDSTP5	0x4003
+#define SDR0_SDSTP6	0x4005
+#define SDR0_SDSTP7	0x4007
 
 #endif /* CONFIG_440SPE */
 
 /*-----------------------------------------------------------------------------
  | External Bus Controller
  +----------------------------------------------------------------------------*/
-/* values for ebccfga register - indirect addressing of these regs */
-#define pb0cr		0x00	/* periph bank 0 config reg		*/
-#define pb1cr		0x01	/* periph bank 1 config reg		*/
-#define pb2cr		0x02	/* periph bank 2 config reg		*/
-#define pb3cr		0x03	/* periph bank 3 config reg		*/
-#define pb4cr		0x04	/* periph bank 4 config reg		*/
-#define pb5cr		0x05	/* periph bank 5 config reg		*/
-#define pb6cr		0x06	/* periph bank 6 config reg		*/
-#define pb7cr		0x07	/* periph bank 7 config reg		*/
-#define pb0ap		0x10	/* periph bank 0 access parameters	*/
-#define pb1ap		0x11	/* periph bank 1 access parameters	*/
-#define pb2ap		0x12	/* periph bank 2 access parameters	*/
-#define pb3ap		0x13	/* periph bank 3 access parameters	*/
-#define pb4ap		0x14	/* periph bank 4 access parameters	*/
-#define pb5ap		0x15	/* periph bank 5 access parameters	*/
-#define pb6ap		0x16	/* periph bank 6 access parameters	*/
-#define pb7ap		0x17	/* periph bank 7 access parameters	*/
-#define pbear		0x20	/* periph bus error addr reg		*/
-#define pbesr		0x21	/* periph bus error status reg		*/
-#define xbcfg		0x23	/* external bus configuration reg	*/
+/* values for EBC0_CFGADDR register - indirect addressing of these regs */
+#define PB0CR		0x00	/* periph bank 0 config reg		*/
+#define PB1CR		0x01	/* periph bank 1 config reg		*/
+#define PB2CR		0x02	/* periph bank 2 config reg		*/
+#define PB3CR		0x03	/* periph bank 3 config reg		*/
+#define PB4CR		0x04	/* periph bank 4 config reg		*/
+#define PB5CR		0x05	/* periph bank 5 config reg		*/
+#define PB6CR		0x06	/* periph bank 6 config reg		*/
+#define PB7CR		0x07	/* periph bank 7 config reg		*/
+#define PB0AP		0x10	/* periph bank 0 access parameters	*/
+#define PB1AP		0x11	/* periph bank 1 access parameters	*/
+#define PB2AP		0x12	/* periph bank 2 access parameters	*/
+#define PB3AP		0x13	/* periph bank 3 access parameters	*/
+#define PB4AP		0x14	/* periph bank 4 access parameters	*/
+#define PB5AP		0x15	/* periph bank 5 access parameters	*/
+#define PB6AP		0x16	/* periph bank 6 access parameters	*/
+#define PB7AP		0x17	/* periph bank 7 access parameters	*/
+#define PBEAR		0x20	/* periph bus error addr reg		*/
+#define PBESR		0x21	/* periph bus error status reg		*/
 #define EBC0_CFG	0x23	/* external bus configuration reg	*/
-#define xbcid		0x24	/* external bus core id reg		*/
 
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 
-/* PLB4 to PLB3 Bridge OUT */
-#define P4P3_DCR_BASE           0x020
-#define p4p3_esr0_read          (P4P3_DCR_BASE+0x0)
-#define p4p3_esr0_write         (P4P3_DCR_BASE+0x1)
-#define p4p3_eadr               (P4P3_DCR_BASE+0x2)
-#define p4p3_euadr              (P4P3_DCR_BASE+0x3)
-#define p4p3_esr1_read          (P4P3_DCR_BASE+0x4)
-#define p4p3_esr1_write         (P4P3_DCR_BASE+0x5)
-#define p4p3_confg              (P4P3_DCR_BASE+0x6)
-#define p4p3_pic                (P4P3_DCR_BASE+0x7)
-#define p4p3_peir               (P4P3_DCR_BASE+0x8)
-#define p4p3_rev                (P4P3_DCR_BASE+0xA)
-
-/* PLB3 to PLB4 Bridge IN */
-#define P3P4_DCR_BASE           0x030
-#define p3p4_esr0_read          (P3P4_DCR_BASE+0x0)
-#define p3p4_esr0_write         (P3P4_DCR_BASE+0x1)
-#define p3p4_eadr               (P3P4_DCR_BASE+0x2)
-#define p3p4_euadr              (P3P4_DCR_BASE+0x3)
-#define p3p4_esr1_read          (P3P4_DCR_BASE+0x4)
-#define p3p4_esr1_write         (P3P4_DCR_BASE+0x5)
-#define p3p4_confg              (P3P4_DCR_BASE+0x6)
-#define p3p4_pic                (P3P4_DCR_BASE+0x7)
-#define p3p4_peir               (P3P4_DCR_BASE+0x8)
-#define p3p4_rev                (P3P4_DCR_BASE+0xA)
-
 /* PLB3 Arbiter */
-#define PLB3_DCR_BASE           0x070
-#define plb3_revid              (PLB3_DCR_BASE+0x2)
-#define plb3_besr               (PLB3_DCR_BASE+0x3)
-#define plb3_bear               (PLB3_DCR_BASE+0x6)
-#define plb3_acr                (PLB3_DCR_BASE+0x7)
+#define PLB3_DCR_BASE		0x070
+#define PLB3_ACR		(PLB3_DCR_BASE + 0x7)
 
 /* PLB4 Arbiter - PowerPC440EP Pass1 */
-#define PLB4_DCR_BASE           0x080
-#define plb4_acr                (PLB4_DCR_BASE+0x1)
-#define plb4_revid              (PLB4_DCR_BASE+0x2)
-#define plb4_besr               (PLB4_DCR_BASE+0x4)
-#define plb4_bearl              (PLB4_DCR_BASE+0x6)
-#define plb4_bearh              (PLB4_DCR_BASE+0x7)
+#define PLB4_DCR_BASE		0x080
+#define PLB4_ACR		(PLB4_DCR_BASE + 0x1)
 
 #define PLB4_ACR_WRP		(0x80000000 >> 7)
 
@@ -578,24 +534,16 @@
 #define CNTRL_DCR_BASE 0x0b0
 #endif
 
-#define cpc0_er		(CNTRL_DCR_BASE+0x00)	/* CPM enable register		*/
-#define cpc0_fr		(CNTRL_DCR_BASE+0x01)	/* CPM force register		*/
-#define cpc0_sr		(CNTRL_DCR_BASE+0x02)	/* CPM status register		*/
-
-#define cpc0_sys0	(CNTRL_DCR_BASE+0x30)	/* System configuration reg 0	*/
-#define cpc0_sys1	(CNTRL_DCR_BASE+0x31)	/* System configuration reg 1	*/
-#define cpc0_cust0	(CNTRL_DCR_BASE+0x32)	/* Customer configuration reg 0 */
-#define cpc0_cust1	(CNTRL_DCR_BASE+0x33)	/* Customer configuration reg 1 */
+#define CPC0_SYS0	(CNTRL_DCR_BASE+0x30)	/* System configuration reg 0	*/
+#define CPC0_SYS1	(CNTRL_DCR_BASE+0x31)	/* System configuration reg 1	*/
 
-#define cpc0_strp0	(CNTRL_DCR_BASE+0x34)	/* Power-on config reg 0 (RO)	*/
-#define cpc0_strp1	(CNTRL_DCR_BASE+0x35)	/* Power-on config reg 1 (RO)	*/
-#define cpc0_strp2	(CNTRL_DCR_BASE+0x36)	/* Power-on config reg 2 (RO)	*/
-#define cpc0_strp3	(CNTRL_DCR_BASE+0x37)	/* Power-on config reg 3 (RO)	*/
+#define CPC0_STRP0	(CNTRL_DCR_BASE+0x34)	/* Power-on config reg 0 (RO)	*/
+#define CPC0_STRP1	(CNTRL_DCR_BASE+0x35)	/* Power-on config reg 1 (RO)	*/
 
-#define cpc0_gpio	(CNTRL_DCR_BASE+0x38)	/* GPIO config reg (440GP)	*/
+#define CPC0_GPIO	(CNTRL_DCR_BASE+0x38)	/* GPIO config reg (440GP)	*/
 
-#define cntrl0		(CNTRL_DCR_BASE+0x3b)	/* Control 0 register		*/
-#define cntrl1		(CNTRL_DCR_BASE+0x3a)	/* Control 1 register		*/
+#define CPC0_CR0		(CNTRL_DCR_BASE+0x3b)	/* Control 0 register		*/
+#define CPC0_CR1		(CNTRL_DCR_BASE+0x3a)	/* Control 1 register		*/
 
 /*-----------------------------------------------------------------------------
  | DMA
@@ -605,91 +553,59 @@
 #else
 #define DMA_DCR_BASE 0x100
 #endif
-#define dmacr0	(DMA_DCR_BASE+0x00)  /* DMA channel control register 0	     */
-#define dmact0	(DMA_DCR_BASE+0x01)  /* DMA count register 0		     */
-#define dmasah0 (DMA_DCR_BASE+0x02)  /* DMA source address high 0	     */
-#define dmasal0 (DMA_DCR_BASE+0x03)  /* DMA source address low 0	     */
-#define dmadah0 (DMA_DCR_BASE+0x04)  /* DMA destination address high 0	     */
-#define dmadal0 (DMA_DCR_BASE+0x05)  /* DMA destination address low 0	     */
-#define dmasgh0 (DMA_DCR_BASE+0x06)  /* DMA scatter/gather desc addr high 0  */
-#define dmasgl0 (DMA_DCR_BASE+0x07)  /* DMA scatter/gather desc addr low 0   */
-#define dmacr1	(DMA_DCR_BASE+0x08)  /* DMA channel control register 1	     */
-#define dmact1	(DMA_DCR_BASE+0x09)  /* DMA count register 1		     */
-#define dmasah1 (DMA_DCR_BASE+0x0a)  /* DMA source address high 1	     */
-#define dmasal1 (DMA_DCR_BASE+0x0b)  /* DMA source address low 1	     */
-#define dmadah1 (DMA_DCR_BASE+0x0c)  /* DMA destination address high 1	     */
-#define dmadal1 (DMA_DCR_BASE+0x0d)  /* DMA destination address low 1	     */
-#define dmasgh1 (DMA_DCR_BASE+0x0e)  /* DMA scatter/gather desc addr high 1  */
-#define dmasgl1 (DMA_DCR_BASE+0x0f)  /* DMA scatter/gather desc addr low 1   */
-#define dmacr2	(DMA_DCR_BASE+0x10)  /* DMA channel control register 2	     */
-#define dmact2	(DMA_DCR_BASE+0x11)  /* DMA count register 2		     */
-#define dmasah2 (DMA_DCR_BASE+0x12)  /* DMA source address high 2	     */
-#define dmasal2 (DMA_DCR_BASE+0x13)  /* DMA source address low 2	     */
-#define dmadah2 (DMA_DCR_BASE+0x14)  /* DMA destination address high 2	     */
-#define dmadal2 (DMA_DCR_BASE+0x15)  /* DMA destination address low 2	     */
-#define dmasgh2 (DMA_DCR_BASE+0x16)  /* DMA scatter/gather desc addr high 2  */
-#define dmasgl2 (DMA_DCR_BASE+0x17)  /* DMA scatter/gather desc addr low 2   */
-#define dmacr3	(DMA_DCR_BASE+0x18)  /* DMA channel control register 2	     */
-#define dmact3	(DMA_DCR_BASE+0x19)  /* DMA count register 2		     */
-#define dmasah3 (DMA_DCR_BASE+0x1a)  /* DMA source address high 2	     */
-#define dmasal3 (DMA_DCR_BASE+0x1b)  /* DMA source address low 2	     */
-#define dmadah3 (DMA_DCR_BASE+0x1c)  /* DMA destination address high 2	     */
-#define dmadal3 (DMA_DCR_BASE+0x1d)  /* DMA destination address low 2	     */
-#define dmasgh3 (DMA_DCR_BASE+0x1e)  /* DMA scatter/gather desc addr high 2  */
-#define dmasgl3 (DMA_DCR_BASE+0x1f)  /* DMA scatter/gather desc addr low 2   */
-#define dmasr	(DMA_DCR_BASE+0x20)  /* DMA status register		     */
-#define dmasgc	(DMA_DCR_BASE+0x23)  /* DMA scatter/gather command register  */
-#define dmaslp	(DMA_DCR_BASE+0x25)  /* DMA sleep mode register		     */
-#define dmapol	(DMA_DCR_BASE+0x26)  /* DMA polarity configuration register  */
+#define DMACR0	(DMA_DCR_BASE+0x00)  /* DMA channel control register 0	     */
+#define DMACT0	(DMA_DCR_BASE+0x01)  /* DMA count register 0		     */
+#define DMACR1	(DMA_DCR_BASE+0x08)  /* DMA channel control register 1	     */
+#define DMACT1	(DMA_DCR_BASE+0x09)  /* DMA count register 1		     */
+#define DMACR2	(DMA_DCR_BASE+0x10)  /* DMA channel control register 2	     */
+#define DMACT2	(DMA_DCR_BASE+0x11)  /* DMA count register 2		     */
+#define DMACR3	(DMA_DCR_BASE+0x18)  /* DMA channel control register 2	     */
+#define DMASR	(DMA_DCR_BASE+0x20)  /* DMA status register		     */
+#define DMASGC	(DMA_DCR_BASE+0x23)  /* DMA scatter/gather command register  */
 
 /*-----------------------------------------------------------------------------
  | Memory Access Layer
  +----------------------------------------------------------------------------*/
 #define MAL_DCR_BASE 0x180
-#define malmcr	    (MAL_DCR_BASE+0x00) /* MAL Config reg		    */
-#define malesr	    (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear)    */
-#define malier	    (MAL_DCR_BASE+0x02) /* Interrupt enable reg		    */
-#define maldbr	    (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only)	    */
-#define maltxcasr   (MAL_DCR_BASE+0x04) /* TX Channel active reg (set)	    */
-#define maltxcarr   (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset)    */
-#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg  */
-#define maltxdeir   (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg	    */
-#define maltxtattrr (MAL_DCR_BASE+0x08) /* TX PLB attribute reg		    */
-#define maltxbattr  (MAL_DCR_BASE+0x09) /* TX descriptor base addr reg	    */
-#define malrxcasr   (MAL_DCR_BASE+0x10) /* RX Channel active reg (set)	    */
-#define malrxcarr   (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset)    */
-#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg  */
-#define malrxdeir   (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg	    */
-#define malrxtattrr (MAL_DCR_BASE+0x14) /* RX PLB attribute reg		    */
-#define malrxbattr  (MAL_DCR_BASE+0x15) /* RX descriptor base addr reg	    */
-#define maltxctp0r  (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg   */
-#define maltxctp1r  (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg   */
-#define maltxctp2r  (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg   */
-#define maltxctp3r  (MAL_DCR_BASE+0x23) /* TX 3 Channel table pointer reg   */
-#define malrxctp0r  (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg   */
-#define malrxctp1r  (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg   */
-#define malrcbs0    (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg	    */
-#define malrcbs1    (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg	    */
+#define MAL0_CFG	(MAL_DCR_BASE + 0x00)	/* MAL Config reg	*/
+#define MAL0_ESR	(MAL_DCR_BASE + 0x01)	/* Error Status (Read/Clear) */
+#define MAL0_IER	(MAL_DCR_BASE + 0x02)	/* Interrupt enable */
+#define MAL0_TXCASR	(MAL_DCR_BASE + 0x04)	/* TX Channel active (set) */
+#define MAL0_TXCARR	(MAL_DCR_BASE + 0x05)	/* TX Channel active (reset) */
+#define MAL0_TXEOBISR	(MAL_DCR_BASE + 0x06)	/* TX End of buffer int status */
+#define MAL0_TXDEIR	(MAL_DCR_BASE + 0x07)	/* TX Descr. Error Int */
+#define MAL0_TXBADDR	(MAL_DCR_BASE + 0x09)	/* TX descriptor base addr*/
+#define MAL0_RXCASR	(MAL_DCR_BASE + 0x10)	/* RX Channel active (set) */
+#define MAL0_RXCARR	(MAL_DCR_BASE + 0x11)	/* RX Channel active (reset) */
+#define MAL0_RXEOBISR	(MAL_DCR_BASE + 0x12)	/* RX End of buffer int status */
+#define MAL0_RXDEIR	(MAL_DCR_BASE + 0x13)	/* RX Descr. Error Int */
+#define MAL0_RXBADDR	(MAL_DCR_BASE + 0x15)	/* RX descriptor base addr */
+#define MAL0_TXCTP0R	(MAL_DCR_BASE + 0x20)	/* TX 0 Channel table pointer */
+#define MAL0_TXCTP1R	(MAL_DCR_BASE + 0x21)	/* TX 1 Channel table pointer */
+#define MAL0_TXCTP2R	(MAL_DCR_BASE + 0x22)	/* TX 2 Channel table pointer */
+#define MAL0_TXCTP3R	(MAL_DCR_BASE + 0x23)	/* TX 3 Channel table pointer */
+#define MAL0_RXCTP0R	(MAL_DCR_BASE + 0x40)	/* RX 0 Channel table pointer */
+#define MAL0_RXCTP1R	(MAL_DCR_BASE + 0x41)	/* RX 1 Channel table pointer */
+#define MAL0_RCBS0	(MAL_DCR_BASE + 0x60)	/* RX 0 Channel buffer size */
+#define MAL0_RCBS1	(MAL_DCR_BASE + 0x61)	/* RX 1 Channel buffer size */
 #if defined(CONFIG_440GX) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define malrxctp2r  (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg   */
-#define malrxctp3r  (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg   */
-#define malrxctp8r  (MAL_DCR_BASE+0x48) /* RX 8 Channel table pointer reg   */
-#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table pointer reg  */
-#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table pointer reg  */
-#define malrcbs2    (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg	    */
-#define malrcbs3    (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg	    */
-#define malrcbs8    (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg	    */
-#define malrcbs16   (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg    */
-#define malrcbs24   (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg    */
+#define MAL0_RXCTP2R	(MAL_DCR_BASE + 0x42)	/* RX 2 Channel table pointer */
+#define MAL0_RXCTP3R	(MAL_DCR_BASE + 0x43)	/* RX 3 Channel table pointer */
+#define MAL0_RXCTP8R	(MAL_DCR_BASE + 0x48)	/* RX 8 Channel table pointer */
+#define MAL0_RXCTP16R	(MAL_DCR_BASE + 0x50)	/* RX 16 Channel table pointer*/
+#define MAL0_RXCTP24R	(MAL_DCR_BASE + 0x58)	/* RX 24 Channel table pointer*/
+#define MAL0_RCBS2	(MAL_DCR_BASE + 0x62)	/* RX 2 Channel buffer size */
+#define MAL0_RCBS3	(MAL_DCR_BASE + 0x63)	/* RX 3 Channel buffer size */
+#define MAL0_RCBS8	(MAL_DCR_BASE + 0x68)	/* RX 8 Channel buffer size */
+#define MAL0_RCBS16	(MAL_DCR_BASE + 0x70)	/* RX 16 Channel buffer size */
+#define MAL0_RCBS24	(MAL_DCR_BASE + 0x78)	/* RX 24 Channel buffer size */
 #endif /* CONFIG_440GX */
 
 /*-----------------------------------------------------------------------------+
 |  SDR0 Bit Settings
 +-----------------------------------------------------------------------------*/
 #if defined(CONFIG_440SP)
-#define SDR0_SRST			0x0200
-
 #define SDR0_DDR0			0x00E1
 #define SDR0_DDR0_DPLLRST		0x80000000
 #define SDR0_DDR0_DDRM_MASK		0x60000000
@@ -923,79 +839,6 @@
 #define SDR0_UART0			0x0120
 #define SDR0_UART1			0x0121
 #define SDR0_UART2			0x0122
-#define SDR0_UARTX_UXICS_MASK		0xF0000000
-#define SDR0_UARTX_UXICS_PLB		0x20000000
-#define SDR0_UARTX_UXEC_MASK		0x00800000
-#define SDR0_UARTX_UXEC_INT		0x00000000
-#define SDR0_UARTX_UXEC_EXT		0x00800000
-#define SDR0_UARTX_UXDIV_MASK		0x000000FF
-#define SDR0_UARTX_UXDIV_ENCODE(n)	((((unsigned long)(n))&0xFF)<<0)
-#define SDR0_UARTX_UXDIV_DECODE(n)	((((((unsigned long)(n))>>0)-1)&0xFF)+1)
-
-#define SDR0_CP440			0x0180
-#define SDR0_CP440_ERPN_MASK		0x30000000
-#define SDR0_CP440_ERPN_MASK_HI		0x3000
-#define SDR0_CP440_ERPN_MASK_LO		0x0000
-#define SDR0_CP440_ERPN_EBC		0x10000000
-#define SDR0_CP440_ERPN_EBC_HI		0x1000
-#define SDR0_CP440_ERPN_EBC_LO		0x0000
-#define SDR0_CP440_ERPN_PCI		0x20000000
-#define SDR0_CP440_ERPN_PCI_HI		0x2000
-#define SDR0_CP440_ERPN_PCI_LO		0x0000
-#define SDR0_CP440_ERPN_ENCODE(n)	((((unsigned long)(n))&0x03)<<28)
-#define SDR0_CP440_ERPN_DECODE(n)	((((unsigned long)(n))>>28)&0x03)
-#define SDR0_CP440_NTO1_MASK		0x00000002
-#define SDR0_CP440_NTO1_NTOP		0x00000000
-#define SDR0_CP440_NTO1_NTO1		0x00000002
-#define SDR0_CP440_NTO1_ENCODE(n)	((((unsigned long)(n))&0x01)<<1)
-#define SDR0_CP440_NTO1_DECODE(n)	((((unsigned long)(n))>>1)&0x01)
-
-#define SDR0_XCR0			0x01C0
-#define SDR0_XCR1			0x01C3
-#define SDR0_XCR2			0x01C6
-#define SDR0_XCRn_PAE_MASK		0x80000000
-#define SDR0_XCRn_PAE_DISABLE		0x00000000
-#define SDR0_XCRn_PAE_ENABLE		0x80000000
-#define SDR0_XCRn_PAE_ENCODE(n)		((((unsigned long)(n))&0x01)<<31)
-#define SDR0_XCRn_PAE_DECODE(n)		((((unsigned long)(n))>>31)&0x01)
-#define SDR0_XCRn_PHCE_MASK		0x40000000
-#define SDR0_XCRn_PHCE_DISABLE		0x00000000
-#define SDR0_XCRn_PHCE_ENABLE		0x40000000
-#define SDR0_XCRn_PHCE_ENCODE(n)	((((unsigned long)(n))&0x01)<<30)
-#define SDR0_XCRn_PHCE_DECODE(n)	((((unsigned long)(n))>>30)&0x01)
-#define SDR0_XCRn_PISE_MASK		0x20000000
-#define SDR0_XCRn_PISE_DISABLE		0x00000000
-#define SDR0_XCRn_PISE_ENABLE		0x20000000
-#define SDR0_XCRn_PISE_ENCODE(n)	((((unsigned long)(n))&0x01)<<29)
-#define SDR0_XCRn_PISE_DECODE(n)	((((unsigned long)(n))>>29)&0x01)
-#define SDR0_XCRn_PCWE_MASK		0x10000000
-#define SDR0_XCRn_PCWE_DISABLE		0x00000000
-#define SDR0_XCRn_PCWE_ENABLE		0x10000000
-#define SDR0_XCRn_PCWE_ENCODE(n)	((((unsigned long)(n))&0x01)<<28)
-#define SDR0_XCRn_PCWE_DECODE(n)	((((unsigned long)(n))>>28)&0x01)
-#define SDR0_XCRn_PPIM_MASK		0x0F000000
-#define SDR0_XCRn_PPIM_ENCODE(n)	((((unsigned long)(n))&0x0F)<<24)
-#define SDR0_XCRn_PPIM_DECODE(n)	((((unsigned long)(n))>>24)&0x0F)
-#define SDR0_XCRn_PR64E_MASK		0x00800000
-#define SDR0_XCRn_PR64E_DISABLE		0x00000000
-#define SDR0_XCRn_PR64E_ENABLE		0x00800000
-#define SDR0_XCRn_PR64E_ENCODE(n)	((((unsigned long)(n))&0x01)<<23)
-#define SDR0_XCRn_PR64E_DECODE(n)	((((unsigned long)(n))>>23)&0x01)
-#define SDR0_XCRn_PXFS_MASK		0x00600000
-#define SDR0_XCRn_PXFS_100_133		0x00000000
-#define SDR0_XCRn_PXFS_66_100		0x00200000
-#define SDR0_XCRn_PXFS_50_66		0x00400000
-#define SDR0_XCRn_PXFS_0_33		0x00600000
-#define SDR0_XCRn_PXFS_ENCODE(n)	((((unsigned long)(n))&0x03)<<21)
-#define SDR0_XCRn_PXFS_DECODE(n)	((((unsigned long)(n))>>21)&0x03)
-
-#define SDR0_XPLLC0			0x01C1
-#define SDR0_XPLLD0			0x01C2
-#define SDR0_XPLLC1			0x01C4
-#define SDR0_XPLLD1			0x01C5
-#define SDR0_XPLLC2			0x01C7
-#define SDR0_XPLLD2			0x01C8
-#define SDR0_SRST			0x0200
 #define SDR0_SLPIPE			0x0220
 
 #define SDR0_AMP0			0x0240
@@ -1544,8 +1387,7 @@
 
 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
 
-#define SDR0_SRST0		0x0200
-#define SDR0_SRST		SDR0_SRST0 /* for compatability reasons */
+#define SDR0_SRST0		SDR0_SRST  /* for compatability reasons */
 #define SDR0_SRST0_BGO		0x80000000 /* PLB to OPB bridge */
 #define SDR0_SRST0_PLB4		0x40000000 /* PLB4 arbiter */
 #define SDR0_SRST0_EBC		0x20000000 /* External bus controller */
@@ -1607,8 +1449,6 @@
 #define SDR0_SRST1_AHBICM	0x00000002 /* AHB inter-connect matrix */
 #define SDR0_SRST1_SATA		0x00000001 /* Serial ATA controller */
 
-#define SDR0_PCI0		0x1c0		/* PCI Configuration Register */
-
 #else
 
 #define SDR0_SRST_BGO			0x80000000
diff --git a/include/ppc4xx.h b/include/ppc4xx.h
index a9954aa..086f8fb 100644
--- a/include/ppc4xx.h
+++ b/include/ppc4xx.h
@@ -65,49 +65,37 @@
 
 #define PLB_ARBITER_BASE		0x80
 
-#define plb0_revid			(PLB_ARBITER_BASE + 0x00)
-#define plb0_acr			(PLB_ARBITER_BASE + 0x01)
-#define plb0_acr_ppm_mask		0xF0000000
-#define plb0_acr_ppm_fixed		0x00000000
-#define plb0_acr_ppm_fair		0xD0000000
-#define plb0_acr_hbu_mask		0x08000000
-#define plb0_acr_hbu_disabled		0x00000000
-#define plb0_acr_hbu_enabled		0x08000000
-#define plb0_acr_rdp_mask		0x06000000
-#define plb0_acr_rdp_disabled		0x00000000
-#define plb0_acr_rdp_2deep		0x02000000
-#define plb0_acr_rdp_3deep		0x04000000
-#define plb0_acr_rdp_4deep		0x06000000
-#define plb0_acr_wrp_mask		0x01000000
-#define plb0_acr_wrp_disabled		0x00000000
-#define plb0_acr_wrp_2deep		0x01000000
-
-#define plb0_besrl			(PLB_ARBITER_BASE + 0x02)
-#define plb0_besrh			(PLB_ARBITER_BASE + 0x03)
-#define plb0_bearl			(PLB_ARBITER_BASE + 0x04)
-#define plb0_bearh			(PLB_ARBITER_BASE + 0x05)
-#define plb0_ccr			(PLB_ARBITER_BASE + 0x08)
-
-#define plb1_acr			(PLB_ARBITER_BASE + 0x09)
-#define plb1_acr_ppm_mask		0xF0000000
-#define plb1_acr_ppm_fixed		0x00000000
-#define plb1_acr_ppm_fair		0xD0000000
-#define plb1_acr_hbu_mask		0x08000000
-#define plb1_acr_hbu_disabled		0x00000000
-#define plb1_acr_hbu_enabled		0x08000000
-#define plb1_acr_rdp_mask		0x06000000
-#define plb1_acr_rdp_disabled		0x00000000
-#define plb1_acr_rdp_2deep		0x02000000
-#define plb1_acr_rdp_3deep		0x04000000
-#define plb1_acr_rdp_4deep		0x06000000
-#define plb1_acr_wrp_mask		0x01000000
-#define plb1_acr_wrp_disabled		0x00000000
-#define plb1_acr_wrp_2deep		0x01000000
-
-#define plb1_besrl			(PLB_ARBITER_BASE + 0x0A)
-#define plb1_besrh			(PLB_ARBITER_BASE + 0x0B)
-#define plb1_bearl			(PLB_ARBITER_BASE + 0x0C)
-#define plb1_bearh			(PLB_ARBITER_BASE + 0x0D)
+#define PLB0_ACR			(PLB_ARBITER_BASE + 0x01)
+#define PLB0_ACR_PPM_MASK		0xF0000000
+#define PLB0_ACR_PPM_FIXED		0x00000000
+#define PLB0_ACR_PPM_FAIR		0xD0000000
+#define PLB0_ACR_HBU_MASK		0x08000000
+#define PLB0_ACR_HBU_DISABLED		0x00000000
+#define PLB0_ACR_HBU_ENABLED		0x08000000
+#define PLB0_ACR_RDP_MASK		0x06000000
+#define PLB0_ACR_RDP_DISABLED		0x00000000
+#define PLB0_ACR_RDP_2DEEP		0x02000000
+#define PLB0_ACR_RDP_3DEEP		0x04000000
+#define PLB0_ACR_RDP_4DEEP		0x06000000
+#define PLB0_ACR_WRP_MASK		0x01000000
+#define PLB0_ACR_WRP_DISABLED		0x00000000
+#define PLB0_ACR_WRP_2DEEP		0x01000000
+
+#define PLB1_ACR			(PLB_ARBITER_BASE + 0x09)
+#define PLB1_ACR_PPM_MASK		0xF0000000
+#define PLB1_ACR_PPM_FIXED		0x00000000
+#define PLB1_ACR_PPM_FAIR		0xD0000000
+#define PLB1_ACR_HBU_MASK		0x08000000
+#define PLB1_ACR_HBU_DISABLED		0x00000000
+#define PLB1_ACR_HBU_ENABLED		0x08000000
+#define PLB1_ACR_RDP_MASK		0x06000000
+#define PLB1_ACR_RDP_DISABLED		0x00000000
+#define PLB1_ACR_RDP_2DEEP		0x02000000
+#define PLB1_ACR_RDP_3DEEP		0x04000000
+#define PLB1_ACR_RDP_4DEEP		0x06000000
+#define PLB1_ACR_WRP_MASK		0x01000000
+#define PLB1_ACR_WRP_DISABLED		0x00000000
+#define PLB1_ACR_WRP_2DEEP		0x01000000
 
 #endif /* 440EP/EPX 440GR/GRX 440SP/SPE 460EX/GT/SX 405EX*/
 
@@ -156,35 +144,35 @@
 						     line aligned data. */
 
 #define CPR0_DCR_BASE	0x0C
-#define cprcfga		(CPR0_DCR_BASE+0x0)
-#define cprcfgd		(CPR0_DCR_BASE+0x1)
+#define CPR0_CFGADDR	(CPR0_DCR_BASE + 0x0)
+#define CPR0_CFGDATA	(CPR0_DCR_BASE + 0x1)
 
 #define SDR_DCR_BASE	0x0E
-#define sdrcfga		(SDR_DCR_BASE+0x0)
-#define sdrcfgd		(SDR_DCR_BASE+0x1)
+#define SDR0_CFGADDR	(SDR_DCR_BASE + 0x0)
+#define SDR0_CFGDATA	(SDR_DCR_BASE + 0x1)
 
 #define SDRAM_DCR_BASE	0x10
-#define memcfga		(SDRAM_DCR_BASE+0x0)
-#define memcfgd		(SDRAM_DCR_BASE+0x1)
+#define SDRAM0_CFGADDR	(SDRAM_DCR_BASE + 0x0)
+#define SDRAM0_CFGDATA	(SDRAM_DCR_BASE + 0x1)
 
 #define EBC_DCR_BASE	0x12
-#define ebccfga		(EBC_DCR_BASE+0x0)
-#define ebccfgd		(EBC_DCR_BASE+0x1)
+#define EBC0_CFGADDR	(EBC_DCR_BASE + 0x0)
+#define EBC0_CFGDATA	(EBC_DCR_BASE + 0x1)
 
 /*
  * Macros for indirect DCR access
  */
-#define mtcpr(reg, d)	do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0)
-#define mfcpr(reg, d)	do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0)
+#define mtcpr(reg, d)	do { mtdcr(CPR0_CFGADDR,reg);mtdcr(CPR0_CFGDATA,d); } while (0)
+#define mfcpr(reg, d)	do { mtdcr(CPR0_CFGADDR,reg);d = mfdcr(CPR0_CFGDATA); } while (0)
 
-#define mtebc(reg, d)	do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0)
-#define mfebc(reg, d)	do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0)
+#define mtebc(reg, d)	do { mtdcr(EBC0_CFGADDR,reg);mtdcr(EBC0_CFGDATA,d); } while (0)
+#define mfebc(reg, d)	do { mtdcr(EBC0_CFGADDR,reg);d = mfdcr(EBC0_CFGDATA); } while (0)
 
-#define mtsdram(reg, d)	do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0)
-#define mfsdram(reg, d)	do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0)
+#define mtsdram(reg, d)	do { mtdcr(SDRAM0_CFGADDR,reg);mtdcr(SDRAM0_CFGDATA,d); } while (0)
+#define mfsdram(reg, d)	do { mtdcr(SDRAM0_CFGADDR,reg);d = mfdcr(SDRAM0_CFGDATA); } while (0)
 
-#define mtsdr(reg, d)	do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0)
-#define mfsdr(reg, d)	do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0)
+#define mtsdr(reg, d)	do { mtdcr(SDR0_CFGADDR,reg);mtdcr(SDR0_CFGDATA,d); } while (0)
+#define mfsdr(reg, d)	do { mtdcr(SDR0_CFGADDR,reg);d = mfdcr(SDR0_CFGDATA); } while (0)
 
 #ifndef __ASSEMBLY__