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authorMasahiro Yamada <yamada.m@jp.panasonic.com>2014-03-05 17:25:37 +0900
committerTom Rini <trini@ti.com>2014-03-07 10:59:06 -0500
commitcfda6bd2d803d0c01f485668eb8d952deb23cf2b (patch)
tree9cf1befd008b380886ebd87545f8b452a584fbcf /include
parent026f9cf24f3c9d30c47c42bac622a64338caf596 (diff)
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mips: move CONFIG_MIPS{32, 64} definition to config.mk
All mips32 boards define CONFIG_MIPS32 in config headers except malta boards which define it in boards.cfg. We can consolidate them by defining it in arch/mips/cpu/mips32/config.mk. CONFIG_MIPS64 definition can be moved to arch/mips/cpu/mips64/config.mk as well. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Diffstat (limited to 'include')
-rw-r--r--include/configs/dbau1x00.h1
-rw-r--r--include/configs/incaip.h1
-rw-r--r--include/configs/pb1x00.h1
-rw-r--r--include/configs/qemu-mips.h1
-rw-r--r--include/configs/qemu-mips64.h1
-rw-r--r--include/configs/vct.h1
6 files changed, 0 insertions, 6 deletions
diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h
index da4ff8e..e0bf3dc 100644
--- a/include/configs/dbau1x00.h
+++ b/include/configs/dbau1x00.h
@@ -12,7 +12,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
#define CONFIG_DBAU1X00 1
#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
diff --git a/include/configs/incaip.h b/include/configs/incaip.h
index 7d2715d..e11d184 100644
--- a/include/configs/incaip.h
+++ b/include/configs/incaip.h
@@ -12,7 +12,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core */
#define CONFIG_INCA_IP 1 /* on a INCA-IP Board */
#define CONFIG_XWAY_SWAP_BYTES
diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h
index e929b23..f924965 100644
--- a/include/configs/pb1x00.h
+++ b/include/configs/pb1x00.h
@@ -12,7 +12,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
#define CONFIG_PB1X00 1
#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index dd3babb..98ed8bc 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -12,7 +12,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_MIPS32 /* MIPS32 CPU core */
#define CONFIG_QEMU_MIPS
#define CONFIG_MISC_INIT_R
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
index a1422fc..e8f5a4c 100644
--- a/include/configs/qemu-mips64.h
+++ b/include/configs/qemu-mips64.h
@@ -12,7 +12,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_MIPS64 /* MIPS64 CPU core */
#define CONFIG_QEMU_MIPS
#define CONFIG_MISC_INIT_R
diff --git a/include/configs/vct.h b/include/configs/vct.h
index 9983116..5ab4de3 100644
--- a/include/configs/vct.h
+++ b/include/configs/vct.h
@@ -25,7 +25,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_MIPS32 /* MIPS 4Kc CPU core */
#define CPU_CLOCK_RATE 324000000 /* Clock for the MIPS core */
#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2)