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| author | Kim Phillips <kim.phillips@freescale.com> | 2007-08-16 22:52:48 -0500 |
|---|---|---|
| committer | Kim Phillips <kim.phillips@freescale.com> | 2007-08-16 23:12:24 -0500 |
| commit | bbea46f76f767b919070b4829bf34c86bd223248 (patch) | |
| tree | 1c4eec552cd1ede648ef3c8e4a6d6c70f431e536 /include | |
| parent | 14778585d1389d86d5846efec29e5fce892680ce (diff) | |
| download | u-boot-imx-bbea46f76f767b919070b4829bf34c86bd223248.zip u-boot-imx-bbea46f76f767b919070b4829bf34c86bd223248.tar.gz u-boot-imx-bbea46f76f767b919070b4829bf34c86bd223248.tar.bz2 | |
mpc83xx: implement board_add_ram_info
add board_add_ram_info, to make memory diagnostic output more
consistent. u-boot banner output now looks like:
DRAM: 256 MB (DDR1, 64-bit, ECC on)
and for boards with SDRAM on the local bus, a line such as this is
added:
SDRAM: 64 MB (local bus)
also replaced some magic numbers with their equivalent define names.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/MPC8313ERDB.h | 4 | ||||
| -rw-r--r-- | include/mpc83xx.h | 5 |
2 files changed, 5 insertions, 4 deletions
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index e2ec0bc..db79ce2 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -113,12 +113,12 @@ /* 0x03200064 */ #if defined(CONFIG_DDR_2T_TIMING) #define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ - | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ | SDRAM_CFG_2T_EN \ | SDRAM_CFG_DBW_32 ) #else #define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ - | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ | SDRAM_CFG_32_BE ) /* 0x43080000 */ #endif diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 829dbf9..4d32c6a 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -705,8 +705,9 @@ #define SDRAM_CFG_SREN 0x40000000 #define SDRAM_CFG_ECC_EN 0x20000000 #define SDRAM_CFG_RD_EN 0x10000000 -#define SDRAM_CFG_SDRAM_TYPE 0x03000000 -#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000 +#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000 +#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000 +#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 #define SDRAM_CFG_DYN_PWR 0x00200000 #define SDRAM_CFG_32_BE 0x00080000 |