Remove lh7a40x cpu and serial driver

Since commit 957731ed (ARM: remove broken "lpd7a40x" boards),
lh7a40x cpu and serial driver have become unused. Remove them.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>

4 files changed, 0 insertions, 632 deletions

diff --git a/include/lh7a400.h b/include/lh7a400.h
deleted file mode 100644
index d1e70a2..0000000
--- a/include/lh7a400.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * lh7a400 SoC interface
- */
-
-#ifndef __LH7A400_H__
-#define __LH7A400_H__
-
-#include "lh7a40x.h"
-
-/* Interrupt Controller (userguide 8.2.1) */
-typedef struct {
-	volatile u32  intsr;
-	volatile u32  intrsr;
-	volatile u32  intens;
-	volatile u32  intenc;
-	volatile u32  rsvd1;
-	volatile u32  rsvd2;
-	volatile u32  rsvd3;
-} /*__attribute__((__packed__))*/ lh7a400_interrupt_t;
-#define LH7A400_INTERRUPT_BASE    (0x80000500)
-#define LH7A400_INTERRUPT_PTR     ((lh7a400_interrupt_t*) LH7A400_INTERRUPT_BASE)
-
-/* (DMA) Direct Memory Access Controller (userguide 9.2.1) */
-typedef struct {
-	lh7a40x_dmachan_t  chan[15];
-	volatile u32       glblint;
-	volatile u32       rsvd1;
-	volatile u32       rsvd2;
-	volatile u32       rsvd3;
-} /*__attribute__((__packed__))*/ lh7a400_dma_t;
-
-#define LH7A400_DMA_BASE      (0x80002800)
-#define DMA_USBTX_OFFSET      (0x000)
-#define DMA_USBRX_OFFSET      (0x040)
-#define DMA_MMCTX_OFFSET      (0x080)
-#define DMA_MMCRX_OFFSET      (0x0C0)
-#define DMA_AC97_BASE         (0x80002A00)
-
-#define LH7A400_DMA_PTR    ((lh7a400_dma_t*) LH7A400_DMA_BASE)
-#define LH7A400_DMA_USBTX \
-	((lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_USBTX_OFFSET))
-#define LH7A400_DMA_USBRX \
-	((lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_USBRX_OFFSET))
-#define LH7A400_DMA_MMCTX \
-	((lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_MMCTX_OFFSET))
-#define LH7A400_DMA_MMCRX \
-	((lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_MMCRX_OFFSET))
-#define LH7A400_AC97RX(n) \
-	((lh7a400_dmachan_t*) (LH7A400_AC97_BASE + \
-	((2*n) * sizeof(lh7a400_dmachan_t))))
-#define LH7A400_AC97TX(n) \
-	((lh7a400_dmachan_t*) (LH7A400_AC97_BASE + \
-	(((2*n)+1) * sizeof(lh7a400_dmachan_t))))
-
-#endif  /* __LH7A400_H__ */
diff --git a/include/lh7a404.h b/include/lh7a404.h
deleted file mode 100644
index 4098af3..0000000
--- a/include/lh7a404.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * lh7a404 SoC interface
- */
-
-#ifndef __LH7A404_H__
-#define __LH7A404_H__
-
-#include "lh7a40x.h"
-
-/* Interrupt Controller (userguide 8.2.1) */
-typedef struct {
-	volatile u32  irqstatus;
-	volatile u32  fiqstatus;
-	volatile u32  rawintr;
-	volatile u32  intsel;
-	volatile u32  inten;
-	volatile u32  intenclr;
-	volatile u32  softint;
-	volatile u32  softintclr;
-	volatile u32  protect;
-	volatile u32  unused1;
-	volatile u32  unused2;
-	volatile u32  vectaddr;
-	volatile u32  nvaddr;
-	volatile u32  unused3[32];
-	volatile u32  vad[16];
-	volatile u32  unused4[44];
-	volatile u32  vectcntl[16];
-	volatile u32  unused5[44];
-	volatile u32  itcr;
-	volatile u32  itip1;
-	volatile u32  itip2;
-	volatile u32  itop1;
-	volatile u32  itop2;
-	volatile u32  unused6[333];
-	volatile u32  periphid[4];
-	volatile u32  pcellid[4];
-} /*__attribute__((__packed__))*/ lh7a404_vic_t;
-#define LH7A404_VIC_BASE	(0x80008000)
-#define LH7A400_VIC_PTR(x)  ((lh7a404_vic_t*)(LH7A400_VIC_BASE + (x*0x2000)))
-
-
-typedef struct {
-	lh7a40x_dmachan_t  m2p0_tx;
-	lh7a40x_dmachan_t  m2p1_rx;
-	lh7a40x_dmachan_t  m2p2_tx;
-	lh7a40x_dmachan_t  m2p3_rx;
-	lh7a40x_dmachan_t  m2m0;
-	lh7a40x_dmachan_t  m2m1;
-	lh7a40x_dmachan_t  unused1;
-	lh7a40x_dmachan_t  unused2;
-	lh7a40x_dmachan_t  m2p5_rx;
-	lh7a40x_dmachan_t  m2p4_tx;
-	lh7a40x_dmachan_t  m2p7_rx;
-	lh7a40x_dmachan_t  m2p6_tx;
-	lh7a40x_dmachan_t  m2p9_rx;
-	lh7a40x_dmachan_t  m2p8_tx;
-	volatile u32       chanarb;
-	volatile u32       glblint;
-} /*__attribute__((__packed__))*/ lh7a400_dma_t;
-
-
-#endif  /* __LH7A404_H__ */
diff --git a/include/lh7a40x.h b/include/lh7a40x.h
deleted file mode 100644
index 09a463c..0000000
--- a/include/lh7a40x.h
+++ /dev/null
@@ -1,279 +0,0 @@
-/*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * lh7a40x SoC series common interface
- */
-
-#ifndef __LH7A40X_H__
-#define __LH7A40X_H__
-
-/* (SMC) Static Memory Controller (usersguide 4.2.1) */
-typedef struct {
-	volatile u32  attib;
-	volatile u32  com;
-	volatile u32  io;
-	volatile u32  rsvd1;
-} /*__attribute__((__packed__))*/ lh7a40x_pccard_t;
-
-typedef struct {
-	volatile u32      bcr[8];
-	lh7a40x_pccard_t  pccard[2];
-	volatile u32	  pcmciacon;
-} /*__attribute__((__packed__))*/ lh7a40x_smc_t;
-#define LH7A40X_SMC_BASE  (0x80002000)
-#define LH7A40X_SMC_PTR   ((lh7a40x_smc_t*) LH7A40X_SMC_BASE)
-
-/* (SDMC) Synchronous Dynamic Ram Controller (usersguide 5.3.1) */
-typedef struct {
-	volatile u32  rsvd1;
-	volatile u32  gblcnfg;
-	volatile u32  rfshtmr;
-	volatile u32  bootstat;
-	volatile u32  sdcsc[4];
-} /*__attribute__((__packed__))*/ lh7a40x_sdmc_t;
-#define LH7A40X_SDMC_BASE  (0x80002400)
-#define LH7A40X_SDMC_PTR   ((lh7a40x_sdmc_t*) LH7A40X_SDMC_BASE)
-
-/* (CSC) Clock and State Controller (userguide 6.2.1) */
-typedef struct {
-	volatile u32  pwrsr;
-	volatile u32  pwrcnt;
-	volatile u32  halt;
-	volatile u32  stby;
-	volatile u32  bleoi;
-	volatile u32  mceoi;
-	volatile u32  teoi;
-	volatile u32  stfclr;
-	volatile u32  clkset;
-	volatile u32  scrreg[2];
-	volatile u32  rsvd1;
-	volatile u32  usbreset;
-} /*__attribute__((__packed__))*/ lh7a40x_csc_t;
-#define LH7A40X_STPWR_BASE  (0x80000400)
-#define LH7A40X_CSC_PTR     ((lh7a40x_csc_t*) LH7A40X_STPWR_BASE)
-
-#define CLKSET_SMCROM		(0x01000000)
-#define CLKSET_PS		(0x000C0000)
-#define CLKSET_PS_0		(0x00000000)
-#define CLKSET_PS_1		(0x00040000)
-#define CLKSET_PS_2		(0x00080000)
-#define CLKSET_PS_3		(0x000C0000)
-#define CLKSET_PCLKDIV		(0x00030000)
-#define CLKSET_PCLKDIV_2	(0x00000000)
-#define CLKSET_PCLKDIV_4	(0x00010000)
-#define CLKSET_PCLKDIV_8	(0x00020000)
-#define CLKSET_MAINDIV2		(0x0000f800)
-#define CLKSET_MAINDIV1		(0x00000780)
-#define CLKSET_PREDIV		(0x0000007C)
-#define CLKSET_HCLKDIV		(0x00000003)
-
-/* (DMA) Direct Memory Access Controller (userguide 9.2.1) */
-typedef struct {
-	volatile u32  maxcnt;
-	volatile u32  base;
-	volatile u32  current;
-	volatile u32  rsvd1;
-} lh7a40x_dmabuf_t;
-
-typedef struct {
-	volatile u32      control;
-	volatile u32      interrupt;
-	volatile u32      rsvd1;
-	volatile u32      status;
-	volatile u32      rsvd2;
-	volatile u32      remain;
-	volatile u32      rsvd3;
-	volatile u32      rsvd4;
-	lh7a40x_dmabuf_t  buf[2];
-} /*__attribute__((__packed__))*/ lh7a40x_dmachan_t;
-
-
-/* (WDT) Watchdog Timer (userguide 11.2.1) */
-typedef struct {
-	volatile u32  ctl;
-	volatile u32  rst;
-	volatile u32  status;
-	volatile u32  count[4];
-} /*__attribute__((__packed__))*/ lh7a40x_wdt_t;
-#define LH7A40X_WDT_BASE    (0x80001400)
-#define LH7A40X_WDT_PTR     ((lh7a40x_wdt_t*) LH7A40X_WDT_BASE)
-
-/* (RTC) Real Time Clock (lh7a400 userguide 12.2.1, lh7a404 userguide 13.2.1) */
-typedef struct {
-	volatile u32  rtcdr;
-	volatile u32  rtclr;
-	volatile u32  rtcmr;
-	volatile u32  unk1;
-	volatile u32  rtcstat_eoi;
-	volatile u32  rtccr;
-	volatile u32  rsvd1[58];
-} /*__attribute__((__packed__))*/ lh7a40x_rtc_t;
-#define LH7A40X_RTC_BASE    (0x80000D00)
-#define LH7A40X_RTC_PTR     ((lh7a40x_rtc_t*) LH7A40X_RTC_BASE)
-
-/* Timers (lh7a400 userguide 13.2.1, lh7a404 userguide 11.2.1) */
-typedef struct {
-	volatile u32  load;
-	volatile u32  value;
-	volatile u32  control;
-	volatile u32  tceoi;
-} /*__attribute__((__packed__))*/ lh7a40x_timer_t;
-
-typedef struct {
-	lh7a40x_timer_t  timer1;
-	volatile u32     rsvd1[4];
-	lh7a40x_timer_t  timer2;
-	volatile u32     unk1[4];
-	volatile u32     bzcon;
-	volatile u32     unk2[15];
-	lh7a40x_timer_t  timer3;
-	/*volatile u32     rsvd2;*/
-} /*__attribute__((__packed__))*/ lh7a40x_timers_t;
-#define LH7A40X_TIMERS_BASE    (0x80000C00)
-#define LH7A40X_TIMERS_PTR     ((lh7a40x_timers_t*) LH7A40X_TIMERS_BASE)
-
-#define TIMER_EN	(0x00000080)
-#define TIMER_PER	(0x00000040)
-#define TIMER_FREE	(0x00000000)
-#define TIMER_CLK508K	(0x00000008)
-#define TIMER_CLK2K	(0x00000000)
-
-/* (SSP) Sychronous Serial Ports (lh7a400 userguide 14.2.1, lh7a404 userguide 14.2.1) */
-typedef struct {
-	volatile u32  cr0;
-	volatile u32  cr1;
-	volatile u32  irr_roeoi;
-	volatile u32  dr;
-	volatile u32  cpr;
-	volatile u32  sr;
-	/*volatile u32  rsvd1[58];*/
-} /*__attribute__((__packed__))*/ lh7a40x_ssp_t;
-#define LH7A40X_SSP_BASE    (0x80000B00)
-#define LH7A40X_SSP_PTR     ((lh7a40x_ssp_t*) LH7A40X_SSP_BASE)
-
-/* (UART) Universal Asychronous Receiver/Transmitter (lh7a400 userguide 15.2.1, lh7a404 userguide 15.2.1) */
-typedef struct {
-	volatile u32  data;
-	volatile u32  fcon;
-	volatile u32  brcon;
-	volatile u32  con;
-	volatile u32  status;
-	volatile u32  rawisr;
-	volatile u32  inten;
-	volatile u32  isr;
-	volatile u32  rsvd1[56];
-} /*__attribute__((__packed__))*/ lh7a40x_uart_t;
-#define LH7A40X_UART_BASE    (0x80000600)
-#define LH7A40X_UART_PTR(n) \
-	((lh7a40x_uart_t*) (LH7A40X_UART_BASE + ((n-1) * sizeof(lh7a40x_uart_t))))
-
-#define UART_BE		(0x00000800)      /* the rx error bits */
-#define UART_OE		(0x00000400)
-#define UART_PE		(0x00000200)
-#define UART_FE		(0x00000100)
-
-#define UART_WLEN	(0x00000060)	/* fcon bits */
-#define UART_WLEN_8	(0x00000060)
-#define UART_WLEN_7	(0x00000040)
-#define UART_WLEN_6	(0x00000020)
-#define UART_WLEN_5	(0x00000000)
-#define UART_FEN	(0x00000010)
-#define UART_STP2	(0x00000008)
-#define UART_STP2_2	(0x00000008)
-#define UART_STP2_1	(0x00000000)
-#define UART_EPS	(0x00000004)
-#define UART_EPS_EVEN	(0x00000004)
-#define UART_EPS_ODD	(0x00000000)
-#define UART_PEN	(0x00000002)
-#define UART_BRK	(0x00000001)
-
-#define UART_BAUDDIV	(0x0000ffff)	/* brcon bits */
-
-#define UART_SIRBD	(0x00000080)	/* con bits */
-#define UART_LBE	(0x00000040)
-#define UART_MXP	(0x00000020)
-#define UART_TXP	(0x00000010)
-#define UART_RXP	(0x00000008)
-#define UART_SIRLP	(0x00000004)
-#define UART_SIRD	(0x00000002)
-#define UART_EN		(0x00000001)
-
-#define UART_TXFE	(0x00000080)	/* status bits */
-#define UART_RXFF	(0x00000040)
-#define UART_TXFF	(0x00000020)
-#define UART_RXFE	(0x00000010)
-#define UART_BUSY	(0x00000008)
-#define UART_DCD	(0x00000004)
-#define UART_DSR	(0x00000002)
-#define UART_CTS	(0x00000001)
-
-#define UART_MSEOI	(0xfffffff0)	/* rawisr interrupt bits */
-
-#define UART_RTI	(0x00000008)	/* generic interrupt bits */
-#define UART_MI		(0x00000004)
-#define UART_TI		(0x00000002)
-#define UART_RI		(0x00000001)
-
-/* (GPIO) General Purpose IO and External Interrupts (userguide 16.2.1) */
-typedef struct {
-	volatile u32  pad;
-	volatile u32  pbd;
-	volatile u32  pcd;
-	volatile u32  pdd;
-	volatile u32  padd;
-	volatile u32  pbdd;
-	volatile u32  pcdd;
-	volatile u32  pddd;
-	volatile u32  ped;
-	volatile u32  pedd;
-	volatile u32  kbdctl;
-	volatile u32  pinmux;
-	volatile u32  pfd;
-	volatile u32  pfdd;
-	volatile u32  pgd;
-	volatile u32  pgdd;
-	volatile u32  phd;
-	volatile u32  phdd;
-	volatile u32  rsvd1;
-	volatile u32  inttype1;
-	volatile u32  inttype2;
-	volatile u32  gpiofeoi;
-	volatile u32  gpiointen;
-	volatile u32  intstatus;
-	volatile u32  rawintstatus;
-	volatile u32  gpiodb;
-	volatile u32  papd;
-	volatile u32  pbpd;
-	volatile u32  pcpd;
-	volatile u32  pdpd;
-	volatile u32  pepd;
-	volatile u32  pfpd;
-	volatile u32  pgpd;
-	volatile u32  phpd;
-} /*__attribute__((__packed__))*/ lh7a40x_gpioint_t;
-#define LH7A40X_GPIOINT_BASE    (0x80000E00)
-#define LH7A40X_GPIOINT_PTR     ((lh7a40x_gpioint_t*) LH7A40X_GPIOINT_BASE)
-
-/* Embedded SRAM */
-#define CONFIG_SYS_SRAM_BASE	(0xB0000000)
-#define CONFIG_SYS_SRAM_SIZE	(80*1024)	/* 80kB */
-
-#endif  /* __LH7A40X_H__ */
diff --git a/include/lpd7a400_cpld.h b/include/lpd7a400_cpld.h
deleted file mode 100644
index c70af09..0000000
--- a/include/lpd7a400_cpld.h
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Logic lh7a400-10 Card Engine CPLD interface
- */
-
-#ifndef __LPD7A400_CPLD_H_
-#define __LPD7A400_CPLD_H_
-
-
-/*
- * IO Controller Address and Register Definitions
- *   - using LH7A400-10 Card Engine IO Controller Specification
- *     (logic PN: 70000079)
- */
-
-/*------------------------------------------------------------------
- * Slow Peripherals (nCS6)
- */
-#define LPD7A400_CPLD_CF		(0x60200000)
-#define LPD7A400_CPLD_ISA		(0x60400000)
-
-/*------------------------------------------------------------------
- * Fast Peripherals (nCS7)
- *
- * The CPLD directs access to 0x70000000-0x701fffff to the onboard
- * ethernet controller
- */
-#define LPD7A400_CPLD_WLAN_BASE		(0x70000000)
-
-/* All registers are 8 bit */
-#define LPD7A400_CPLD_CECTL_REG		(0x70200000)
-#define LPD7A400_CPLD_SPIDATA_REG	(0x70600000)
-#define LPD7A400_CPLD_SPICTL_REG	(0x70800000)
-#define LPD7A400_CPLD_EEPSPI_REG	(0x70a00000)
-#define LPD7A400_CPLD_INTMASK_REG	(0x70c00000)
-#define LPD7A400_CPLD_MODE_REG		(0x70e00000)
-#define LPD7A400_CPLD_FLASH_REG		(0x71000000)
-#define LPD7A400_CPLD_PWRMG_REG		(0x71200000)
-#define LPD7A400_CPLD_REV_REG		(0x71400000)
-#define LPD7A400_CPLD_EXTGPIO_REG	(0x71600000)
-#define LPD7A400_CPLD_GPIODATA_REG	(0x71800000)
-#define LPD7A400_CPLD_GPIODIR_REG	(0x71a00000)
-
-#define LPD7A400_CPLD_REGPTR		(volatile u8*)
-
-/* Card Engine Control Register (section 3.1.2) */
-#define CECTL_SWINT	(0x80)	/* Software settable interrupt source
-				   (routed to uP PF3)
-				   0 = generate interrupt, 1 = do not */
-#define CECTL_OCMSK	(0x40)	/* USB1 connection interrupt mask
-				   0 = not masked, 1 = masked */
-#define CECTL_PDRV	(0x20)	/* PCC_nDRV output
-				   0 = active, 1 = inactive */
-#define CECTL_USB1C	(0x10)	/* USB1 connection interrupt
-				   0 = active, 1 = inactive */
-#define CECTL_USB1P	(0x08)  /* USB1 Power enable
-				   0 = enabled, 1 = disabled */
-#define CECTL_AWKP	(0x04)  /* Auto-Wakeup enable
-				   0 = enabled, 1 = disabled */
-#define CECTL_LCDV	(0x02)  /* LCD VEE enable
-				   0 = disabled, 1 = enabled */
-#define CECTL_WLPE	(0x01)  /* Wired LAN power enable
-				   0 = enabled, 1 = disabled */
-
-/* SPI Control Register (section 3.1.5) */
-#define SPICTL_SPLD	(0x20)	/* SPI load (R)
-				   0 = data reg. has not been loaded, shift
-				       count has not been reset
-				   1 = data reg. loaded, shift count reset */
-#define SPICTL_SPST	(0x10)  /* SPI start (RW)
-				   0 = don't load data reg. and reset shift count
-				   1 = ready to load data reg and reset shift count */
-#define SPICTL_SPDN	(0x08)  /* SPI done (R)
-				   0 = not done
-				   1 = access done */
-#define SPICTL_SPRW	(0x04)  /* SPI read/write (RW)
-				   0 = SPI write access
-				   1 = SPI read access */
-#define SPICTL_STCS	(0x02)  /* SPI touch chip select (RW)
-				   0 = not selected
-				   1 = selected */
-#define SPICTL_SCCS	(0x01)  /* SPI CODEC chip select (RW) {not used}
-				   0 = not selected
-				   1 = selected */
-
-/* EEPROM SPI Interface Register (section 3.1.6) */
-#define EEPSPI_EECS	(0x08)	/* EEPROM chip select (RW)
-				   0 = not selected
-				   1 = selected */
-#define EEPSPI_EECK	(0x04)	/* EEPROM SPI clock (RW) */
-#define EEPSPI_EETX	(0x02)  /* EEPROM SPI tx data (RW) */
-#define EEPSPI_EERX	(0x01)  /* EEPROM SPI rx data (R) */
-
-/* Interrupt/Mask Register (section 3.1.7) */
-#define INTMASK_CMSK	(0x80)  /* CPLD_nIRQD interrupt mask (RW)
-				   0 = not masked
-				   1 = masked */
-#define INTMASK_CIRQ	(0x40)	/* interrupt signal to CPLD (R)
-				   0 = interrupt active
-				   1 = no interrupt */
-#define INTMASK_PIRQ	(0x10)	/* legacy, no effect */
-#define INTMASK_TMSK	(0x08)	/* Touch chip interrupt mask (RW)
-				   0 = not masked
-				   1 = masked */
-#define INTMASK_WMSK	(0x04)  /* Wired LAN interrupt mask (RW)
-				   0 = not masked
-				   1 = masked */
-#define INTMASK_TIRQ	(0x02)  /* Touch chip interrupt request (R)
-				   0 = interrupt active
-				   1 = no interrupt */
-#define INTMASK_WIRQ	(0x01)  /* Wired LAN interrupt request (R)
-				   0 = interrupt active
-				   1 = no interrupt */
-
-/* Mode Register (section 3.1.8) */
-#define MODE_VS1	(0x80)  /* PCMCIA Voltage Sense 1 input (PCC_VS1) (R)
-				   0 = active slot VS1 pin is low
-				   1 = active slot VS1 pin is high */
-#define MODE_CD2	(0x40)  /* PCMCIA Card Detect 2 input (PCC_nCD2) (R)
-				   0 = active slot CD2 is low
-				   1 = active slot CD2 is high */
-#define MODE_IOIS16	(0x20)  /* PCMCIA IOIS16 input (PCC_nIOIS16) (R)
-				   0 = 16 bit access area
-				   1 = 8 bit access area */
-#define MODE_CD1	(0x10)  /* PCMCIA Card Detect 1 input (PCC_nCD1) (R)
-				   0 = active slot CD1 is low
-				   1 = active slot CD1 is high */
-#define MODE_upMODE3	(0x08)  /* Mode Pin 3 (R)
-				   0 = off-board boot device
-				   1 = on-board boot device (flash) */
-#define MODE_upMODE2	(0x04)  /* Mode Pin 2 (R) (LH7A400 Little Endian only)
-				   0 = big endian
-				   1 = little endian */
-#define MODE_upMODE1	(0x02)  /* Mode Pin 1 and Mode Pin 2 (R) */
-#define MODE_upMODE0	(0x01)  /*   - bus width at boot */
-
-
-/* Flash Register (section 3.1.9) */
-#define FLASH_FPOP	(0x08)	/* Flash populated (RW)
-				   0 = populated, 1 = not */
-#define FLASH_FST2	(0x04)  /* Flash status (R) (RY/BY# pin for upper 16 bit chip
-				   0 = busy, 1 = ready */
-#define FLASH_FST1	(0x02)  /* Flash status (R) (RY/BY# pin for lower 16 bit chip
-				   0 = busy, 1 = ready */
-#define FLASH_FPEN	(0x01)  /* Flash program enable (RW)
-				   0 = flash write protected
-				   1 = programming enabled */
-
-/* Power Management Register (section 3.1.10)
- *    - when either of these is low an unmaskable interrupt to cpu
- *      is generated
- */
-#define PWRMG_STBY	(0x10)  /* state of nSTANDBY signal to CPLD (R)
-				   0 = low, 1 = high */
-#define PWRMG_SPND	(0x04)  /* state of nSUSPEND signal to CPLD (R)
-				   0 = low, 1 = high */
-
-
-/* Extended GPIO Register (section 3.1.12) */
-#define EXTGPIO_STATUS1	(0x04)  /* Status 1 output (RW) (uP_STATUS_1)
-				   0 = set pin low, 1 = set pin high */
-#define EXTGPIO_STATUS2 (0x02)  /* Status 2 output (RW) (uP_STATUS_2)
-				   0 = set pin low, 1 = set pin high */
-#define EXTGPIO_GPIO1	(0x01)  /* General purpose output (RW) (CPLD_GPIO_1)
-				   0 = set pin low, 1 = set pin high */
-
-/* GPIO Data Register (section 3.1.13) */
-#define GPIODATA_GPIO2	(0x01)  /* General purpose input/output (RW) (CPLD_GPIO_2)
-				   0 = set low (output) / read low (input)
-				   1 = set high (output) / read high (input) */
-
-/* GPIO Direction Register (section 3.1.14) */
-#define GPIODIR_GPDR0	(0x01)  /* GPIO2 direction (RW)
-				   0 = output, 1 = input */
-
-#endif  /* __LH7A400_H__ */