Merge with /home/wd/git/u-boot/custodian/u-boot-testing

23 files changed, 267 insertions, 89 deletions

diff --git a/include/ata.h b/include/ata.h
index 8584226..aa6e90d 100644
--- a/include/ata.h
+++ b/include/ata.h
@@ -83,6 +83,66 @@
 #define ATA_DEVICE(x)	((x & 1)<<4)
 #define ATA_LBA		0xE0
 
+enum {
+	ATA_MAX_DEVICES = 1,	/* per bus/port */
+	ATA_MAX_PRD = 256,	/* we could make these 256/256 */
+	ATA_SECT_SIZE = 256,	/*256 words per sector */
+
+	/* bits in ATA command block registers */
+	ATA_HOB = (1 << 7),	/* LBA48 selector */
+	ATA_NIEN = (1 << 1),	/* disable-irq flag */
+	/*ATA_LBA                 = (1 << 6), */ /* LBA28 selector */
+	ATA_DEV1 = (1 << 4),	/* Select Device 1 (slave) */
+	ATA_DEVICE_OBS = (1 << 7) | (1 << 5),	/* obs bits in dev reg */
+	ATA_DEVCTL_OBS = (1 << 3),	/* obsolete bit in devctl reg */
+	ATA_BUSY = (1 << 7),	/* BSY status bit */
+	ATA_DRDY = (1 << 6),	/* device ready */
+	ATA_DF = (1 << 5),	/* device fault */
+	ATA_DRQ = (1 << 3),	/* data request i/o */
+	ATA_ERR = (1 << 0),	/* have an error */
+	ATA_SRST = (1 << 2),	/* software reset */
+	ATA_ABORTED = (1 << 2),	/* command aborted */
+	/* ATA command block registers */
+	ATA_REG_DATA = 0x00,
+	ATA_REG_ERR = 0x01,
+	ATA_REG_NSECT = 0x02,
+	ATA_REG_LBAL = 0x03,
+	ATA_REG_LBAM = 0x04,
+	ATA_REG_LBAH = 0x05,
+	ATA_REG_DEVICE = 0x06,
+	ATA_REG_STATUS = 0x07,
+	ATA_PCI_CTL_OFS = 0x02,
+	/* and their aliases */
+	ATA_REG_FEATURE = ATA_REG_ERR,
+	ATA_REG_CMD = ATA_REG_STATUS,
+	ATA_REG_BYTEL = ATA_REG_LBAM,
+	ATA_REG_BYTEH = ATA_REG_LBAH,
+	ATA_REG_DEVSEL = ATA_REG_DEVICE,
+	ATA_REG_IRQ = ATA_REG_NSECT,
+
+	/* SETFEATURES stuff */
+	SETFEATURES_XFER = 0x03,
+	XFER_UDMA_7 = 0x47,
+	XFER_UDMA_6 = 0x46,
+	XFER_UDMA_5 = 0x45,
+	XFER_UDMA_4 = 0x44,
+	XFER_UDMA_3 = 0x43,
+	XFER_UDMA_2 = 0x42,
+	XFER_UDMA_1 = 0x41,
+	XFER_UDMA_0 = 0x40,
+	XFER_MW_DMA_2 = 0x22,
+	XFER_MW_DMA_1 = 0x21,
+	XFER_MW_DMA_0 = 0x20,
+	XFER_PIO_4 = 0x0C,
+	XFER_PIO_3 = 0x0B,
+	XFER_PIO_2 = 0x0A,
+	XFER_PIO_1 = 0x09,
+	XFER_PIO_0 = 0x08,
+	XFER_SW_DMA_2 = 0x12,
+	XFER_SW_DMA_1 = 0x11,
+	XFER_SW_DMA_0 = 0x10,
+	XFER_PIO_SLOW = 0x00
+};
 /*
  * ATA Commands (only mandatory commands listed here)
  */
diff --git a/include/configs/JSE.h b/include/configs/JSE.h
index ccd1f19..7fa9ed2 100644
--- a/include/configs/JSE.h
+++ b/include/configs/JSE.h
@@ -49,6 +49,7 @@
   /* Map the SystemACE chip (CS#1) here. (Must be a multiple of 1Meg) */
 #define CONFIG_SYSTEMACE 1
 #define CFG_SYSTEMACE_BASE 0xf0000000
+#define CFG_SYSTEMACE_WIDTH 8
 #define CONFIG_DOS_PARTITION 1
 
   /* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 6976313..7e1005c 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -303,11 +303,11 @@
 #endif
 
 #define CONFIG_GMII			1	/* MII PHY management */
-#define CONFIG_MPC83XX_TSEC1		1
+#define CONFIG_TSEC1		1
 
-#define CONFIG_MPC83XX_TSEC1_NAME	"TSEC0"
-#define CONFIG_MPC83XX_TSEC2		1
-#define CONFIG_MPC83XX_TSEC2_NAME	"TSEC1"
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"TSEC1"
 #define TSEC1_PHY_ADDR			0x1c
 #define TSEC2_PHY_ADDR			4
 #define TSEC1_PHYIDX			0
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 0460be9..20c6d5a 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -432,10 +432,10 @@
 #endif
 
 #define CONFIG_GMII		1	/* MII PHY management */
-#define CONFIG_MPC83XX_TSEC1	1
-#define CONFIG_MPC83XX_TSEC1_NAME	"TSEC0"
-#define CONFIG_MPC83XX_TSEC2	1
-#define CONFIG_MPC83XX_TSEC2_NAME	"TSEC1"
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"TSEC1"
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
 #define TSEC1_PHYIDX		0
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 906339e..834934d 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -374,18 +374,18 @@ boards, we say we have two, but don't display a message if we find only one. */
 #define CONFIG_MII
 #define CONFIG_PHY_GIGE		/* In case CFG_CMD_MII is specified */
 
-#define CONFIG_MPC83XX_TSEC1
+#define CONFIG_TSEC1
 
-#ifdef CONFIG_MPC83XX_TSEC1
-#define CONFIG_MPC83XX_TSEC1_NAME  "TSEC0"
+#ifdef CONFIG_TSEC1
+#define CONFIG_TSEC1_NAME  "TSEC0"
 #define CFG_TSEC1_OFFSET	0x24000
 #define TSEC1_PHY_ADDR		0x1c	/* VSC8201 uses address 0x1c */
 #define TSEC1_PHYIDX		0
 #endif
 
-#ifdef CONFIG_MPC83XX_TSEC2
+#ifdef CONFIG_TSEC2
 #define CONFIG_HAS_ETH1
-#define CONFIG_MPC83XX_TSEC2_NAME  "TSEC1"
+#define CONFIG_TSEC2_NAME  "TSEC1"
 #define CFG_TSEC2_OFFSET	0x25000
 #define CONFIG_UNKNOWN_TSEC	/* TSEC2 is proprietary */
 #define TSEC2_PHY_ADDR		4
@@ -628,11 +628,11 @@ boards, we say we have two, but don't display a message if we find only one. */
  */
 #define CONFIG_ENV_OVERWRITE
 
-#ifdef CONFIG_MPC83XX_TSEC1
+#ifdef CONFIG_TSEC1
 #define CONFIG_ETHADDR		00:E0:0C:00:8C:01
 #endif
 
-#ifdef CONFIG_MPC83XX_TSEC2
+#ifdef CONFIG_TSEC2
 #define CONFIG_ETH1ADDR		00:E0:0C:00:8C:02
 #endif
 
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 5aeea58..9176be3 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -366,10 +366,10 @@
 #endif
 
 #define CONFIG_MII		1	/* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1	1
-#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
-#define CONFIG_MPC85XX_TSEC2	1
-#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"TSEC1"
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
 #define TSEC1_PHYIDX		0
diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h
index 418a3a3..b568cb4 100644
--- a/include/configs/MPC8540EVAL.h
+++ b/include/configs/MPC8540EVAL.h
@@ -212,10 +212,10 @@
 #elif defined(CONFIG_TSEC_ENET)
 #define CONFIG_NET_MULTI 	1
 #define CONFIG_MII		1	/* MII PHY management	*/
-#define CONFIG_MPC85XX_TSEC1    1
-#define CONFIG_MPC85XX_TSEC1_NAME      "TSEC0"
-#define CONFIG_MPC85XX_TSEC2	1
-#define CONFIG_MPC85XX_TSEC2_NAME      "TSEC1"
+#define CONFIG_TSEC1    1
+#define CONFIG_TSEC1_NAME      "TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME      "TSEC1"
 #define CONFIG_MPC85XX_FEC      1
 #define CONFIG_MPC85XX_FEC_NAME                "FEC"
 #define TSEC1_PHY_ADDR          7
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index fb360d2..e047e25 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -373,10 +373,10 @@ extern unsigned long get_clock_freq(void);
 #endif
 
 #define CONFIG_MII		1	/* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1	1
-#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
-#define CONFIG_MPC85XX_TSEC2	1
-#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"TSEC1"
 #undef CONFIG_MPC85XX_FEC
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 4c34308..7cd62e9 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -359,10 +359,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #define CONFIG_MII		1	/* MII PHY management */
 #define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
-#define CONFIG_MPC85XX_TSEC1	1
-#define CONFIG_MPC85XX_TSEC1_NAME	"eTSEC1"
-#define CONFIG_MPC85XX_TSEC3	1
-#define CONFIG_MPC85XX_TSEC3_NAME	"eTSEC3"
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC3	1
+#define CONFIG_TSEC3_NAME	"eTSEC3"
 #undef CONFIG_MPC85XX_FEC
 
 #define TSEC1_PHY_ADDR		0
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 680009d..a0d291e 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -391,14 +391,14 @@ extern unsigned long get_clock_freq(void);
 #endif
 
 #define CONFIG_MII		1	/* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1	1
-#define CONFIG_MPC85XX_TSEC1_NAME	"eTSEC0"
-#define CONFIG_MPC85XX_TSEC2	1
-#define CONFIG_MPC85XX_TSEC2_NAME	"eTSEC1"
-#define CONFIG_MPC85XX_TSEC3	1
-#define CONFIG_MPC85XX_TSEC3_NAME	"eTSEC2"
-#undef CONFIG_MPC85XX_TSEC4
-#define CONFIG_MPC85XX_TSEC4_NAME	"eTSEC3"
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"eTSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"eTSEC1"
+#define CONFIG_TSEC3	1
+#define CONFIG_TSEC3_NAME	"eTSEC2"
+#undef CONFIG_TSEC4
+#define CONFIG_TSEC4_NAME	"eTSEC3"
 #undef CONFIG_MPC85XX_FEC
 
 #define TSEC1_PHY_ADDR		0
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index 4c8b4e7..b7e703c 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -373,10 +373,10 @@ extern unsigned long get_clock_freq(void);
 #endif
 
 #define CONFIG_MII		1	/* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1	1
-#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
-#define CONFIG_MPC85XX_TSEC2	1
-#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"TSEC1"
 #undef CONFIG_MPC85XX_FEC
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 21e6637..043397f 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -356,10 +356,10 @@
 #endif
 
 #define CONFIG_MII		1	/* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1	1
-#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
-#define CONFIG_MPC85XX_TSEC2	1
-#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"TSEC1"
 #undef CONFIG_MPC85XX_FEC
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 3f65644..0ff0416 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -353,12 +353,12 @@ extern unsigned long get_clock_freq(void);
 #endif
 
 #define CONFIG_MII		1	/* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1	1
-#define CONFIG_MPC85XX_TSEC1_NAME	"eTSEC0"
-#define CONFIG_MPC85XX_TSEC2	1
-#define CONFIG_MPC85XX_TSEC2_NAME	"eTSEC1"
-#undef  CONFIG_MPC85XX_TSEC3
-#undef  CONFIG_MPC85XX_TSEC4
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"eTSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"eTSEC1"
+#undef  CONFIG_TSEC3
+#undef  CONFIG_TSEC4
 #undef  CONFIG_MPC85XX_FEC
 
 #define TSEC1_PHY_ADDR		2
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 41daa2b..12af24f 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -359,14 +359,14 @@
 
 #define CONFIG_MII		1	/* MII PHY management */
 
-#define CONFIG_MPC86XX_TSEC1    1
-#define CONFIG_MPC86XX_TSEC1_NAME       "eTSEC1"
-#define CONFIG_MPC86XX_TSEC2    1
-#define CONFIG_MPC86XX_TSEC2_NAME       "eTSEC2"
-#define CONFIG_MPC86XX_TSEC3    1
-#define CONFIG_MPC86XX_TSEC3_NAME       "eTSEC3"
-#define CONFIG_MPC86XX_TSEC4    1
-#define CONFIG_MPC86XX_TSEC4_NAME       "eTSEC4"
+#define CONFIG_TSEC1    1
+#define CONFIG_TSEC1_NAME       "eTSEC1"
+#define CONFIG_TSEC2    1
+#define CONFIG_TSEC2_NAME       "eTSEC2"
+#define CONFIG_TSEC3    1
+#define CONFIG_TSEC3_NAME       "eTSEC3"
+#define CONFIG_TSEC4    1
+#define CONFIG_TSEC4_NAME       "eTSEC4"
 
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
diff --git a/include/configs/PM854.h b/include/configs/PM854.h
index 4fb5440..8f130f5 100644
--- a/include/configs/PM854.h
+++ b/include/configs/PM854.h
@@ -262,10 +262,10 @@
 #endif
 
 #define CONFIG_MII		1	/* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1	1
-#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
-#define CONFIG_MPC85XX_TSEC2	1
-#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"TSEC1"
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
 #define TSEC1_PHYIDX		0
diff --git a/include/configs/PM856.h b/include/configs/PM856.h
index 87ab934..0286b53 100644
--- a/include/configs/PM856.h
+++ b/include/configs/PM856.h
@@ -258,10 +258,10 @@
 #endif
 
 #define CONFIG_MII		1	/* MII PHY management */
-#define CONFIG_MPC85XX_TSEC1	1
-#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
-#define CONFIG_MPC85XX_TSEC2	1
-#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"TSEC1"
 #undef CONFIG_MPC85XX_FEC
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index ed03577..4a5f8b6 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -248,10 +248,10 @@ extern int tqm834x_num_flash_banks;
 #define CONFIG_NET_MULTI
 #endif
 
-#define CONFIG_MPC83XX_TSEC1		1
-#define CONFIG_MPC83XX_TSEC1_NAME	"TSEC0"
-#define CONFIG_MPC83XX_TSEC2		1
-#define CONFIG_MPC83XX_TSEC2_NAME	"TSEC1"
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"TSEC1"
 #define TSEC1_PHY_ADDR			2
 #define TSEC2_PHY_ADDR			1
 #define TSEC1_PHYIDX			0
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index f45f3a2..b0b9dd3 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -258,10 +258,10 @@
 #define CONFIG_NET_MULTI	1
 
 #define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_MPC85XX_TSEC1	1
-#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
-#define CONFIG_MPC85XX_TSEC2	1
-#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"TSEC1"
 #define TSEC1_PHY_ADDR		2
 #define TSEC2_PHY_ADDR		1
 #define TSEC1_PHYIDX		0
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 65aac5c..e6e3866 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -401,10 +401,10 @@
 #define CONFIG_NET_MULTI	1
 #endif
 
-#define CONFIG_MPC83XX_TSEC1	1
-#define CONFIG_MPC83XX_TSEC1_NAME	"TSEC0"
-#define CONFIG_MPC83XX_TSEC2	1
-#define CONFIG_MPC83XX_TSEC2_NAME	"TSEC1"
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"TSEC1"
 #define CONFIG_PHY_BCM5421S	1
 #define TSEC1_PHY_ADDR		0x19
 #define TSEC2_PHY_ADDR		0x1a
diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h
index d7d07a6..8b2ec07 100644
--- a/include/configs/sc520_cdp.h
+++ b/include/configs/sc520_cdp.h
@@ -182,6 +182,15 @@
 #undef  CONFIG_IDE_RESET_ROUTINE	/* no special reset function */
 
 /************************************************************
+*SATA/Native Stuff
+************************************************************/
+#define CFG_SATA_SUPPORTED      1
+#define CFG_SATA_MAXBUS         2       /*Max Sata buses supported */
+#define CFG_SATA_DEVS_PER_BUS   2      /*Max no. of devices per bus/port */
+#define CFG_SATA_MAXDEVICES     (CFG_SATA_MAXBUS* CFG_SATA_DEVS_PER_BUS)
+#define CFG_ATA_PIIX            1       /*Supports ata_piix driver */
+
+/************************************************************
  * ATAPI support (experimental)
  ************************************************************/
 #define CONFIG_ATAPI			/* enable ATAPI Support */
diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h
index 625cf20..21065b9 100644
--- a/include/configs/stxgp3.h
+++ b/include/configs/stxgp3.h
@@ -230,10 +230,10 @@
 
 #define CONFIG_MII		1	/* MII PHY management		*/
 
-#define CONFIG_MPC85XX_TSEC1	1
-#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
-#define CONFIG_MPC85XX_TSEC2	1
-#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"TSEC1"
 #undef CONFIG_MPS85XX_FEC
 
 #define TSEC1_PHY_ADDR		2
diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h
index 1978a32..a14cd50 100644
--- a/include/configs/stxssa.h
+++ b/include/configs/stxssa.h
@@ -256,10 +256,10 @@
 
 #define CONFIG_MII		1	/* MII PHY management		*/
 
-#define CONFIG_MPC85XX_TSEC1	1
-#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
-#define CONFIG_MPC85XX_TSEC2	1
-#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"TSEC1"
 #undef CONFIG_MPS85XX_FEC
 
 #define TSEC1_PHY_ADDR		2
diff --git a/include/sata.h b/include/sata.h
new file mode 100644
index 0000000..165b471
--- /dev/null
+++ b/include/sata.h
@@ -0,0 +1,108 @@
+
+#if (DEBUG_SATA)
+#define PRINTF(fmt,args...)	printf (fmt ,##args)
+#else
+#define PRINTF(fmt,args...)
+#endif
+
+struct sata_ioports {
+	unsigned long cmd_addr;
+	unsigned long data_addr;
+	unsigned long error_addr;
+	unsigned long feature_addr;
+	unsigned long nsect_addr;
+	unsigned long lbal_addr;
+	unsigned long lbam_addr;
+	unsigned long lbah_addr;
+	unsigned long device_addr;
+	unsigned long status_addr;
+	unsigned long command_addr;
+	unsigned long altstatus_addr;
+	unsigned long ctl_addr;
+	unsigned long bmdma_addr;
+	unsigned long scr_addr;
+};
+
+struct sata_port {
+	unsigned char port_no;		/* primary=0, secondary=1	*/
+	struct sata_ioports ioaddr;	/* ATA cmd/ctl/dma reg blks	*/
+	unsigned char ctl_reg;
+	unsigned char last_ctl;
+	unsigned char port_state;	/* 1-port is available and	*/
+					/* 0-port is not available	*/
+	unsigned char dev_mask;
+};
+
+/***********SATA LIBRARY SPECIFIC DEFINITIONS AND DECLARATIONS**************/
+#ifdef SATA_DECL		/*SATA library specific declarations */
+#define ata_id_has_lba48(id)    ((id)[83] & (1 << 10))
+#define ata_id_has_lba(id)      ((id)[49] & (1 << 9))
+#define ata_id_has_dma(id)      ((id)[49] & (1 << 8))
+#define ata_id_u32(id,n)        \
+	(((u32) (id)[(n) + 1] << 16) | ((u32) (id)[(n)]))
+#define ata_id_u64(id,n)        \
+	(((u64) (id)[(n) + 3] << 48) | \
+	((u64) (id)[(n) + 2] << 32) | \
+	((u64) (id)[(n) + 1] << 16) | \
+	((u64) (id)[(n) + 0]) )
+#endif
+
+#ifdef SATA_DECL		/*SATA library specific declarations */
+static inline void
+ata_dump_id (u16 * id)
+{
+	PRINTF ("49==0x%04x  "
+		"53==0x%04x  "
+		"63==0x%04x  "
+		"64==0x%04x  "
+		"75==0x%04x  \n", id[49], id[53], id[63], id[64], id[75]);
+	PRINTF ("80==0x%04x  "
+		"81==0x%04x  "
+		"82==0x%04x  "
+		"83==0x%04x  "
+		"84==0x%04x  \n", id[80], id[81], id[82], id[83], id[84]);
+	PRINTF ("88==0x%04x  " "93==0x%04x\n", id[88], id[93]);
+}
+#endif
+
+#ifdef SATA_DECL		/*SATA library specific declarations */
+int sata_bus_softreset (int num);
+void sata_identify (int num, int dev);
+void sata_port (struct sata_ioports *ioport);
+void set_Feature_cmd (int num, int dev);
+int sata_devchk (struct sata_ioports *ioaddr, int dev);
+void dev_select (struct sata_ioports *ioaddr, int dev);
+u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits, unsigned int max);
+u8 sata_chk_status (struct sata_ioports *ioaddr);
+ulong sata_read (int device, ulong blknr,lbaint_t blkcnt, void * buffer);
+ulong sata_write (int device,ulong blknr, lbaint_t blkcnt, void * buffer);
+void msleep (int count);
+#else
+extern int sata_bus_softreset (int num);
+extern void sata_identify (int num, int dev);
+extern void sata_port (struct sata_ioports *ioport);
+extern void set_Feature_cmd (int num, int dev);
+extern ulong sata_read (int device, ulong blknr,
+			lbaint_t blkcnt, void * buffer);
+extern ulong sata_write (int device, ulong blknr,
+			lbaint_t blkcnt, void * buffer);
+extern void msleep (int count);
+#endif
+
+/************DRIVER SPECIFIC DEFINITIONS AND DECLARATIONS**************/
+
+#ifdef DRV_DECL			/*Driver specific declaration */
+int init_sata (void);
+#else
+extern int init_sata (void);
+#endif
+
+#ifdef DRV_DECL			/*Defines Driver Specific variables */
+struct sata_port port[CFG_SATA_MAXBUS];
+block_dev_desc_t sata_dev_desc[CFG_SATA_MAXDEVICES];
+int curr_dev = -1;
+#else
+extern struct sata_port port[CFG_SATA_MAXBUS];
+extern block_dev_desc_t sata_dev_desc[CFG_SATA_MAXDEVICES];
+extern int curr_dev;
+#endif