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| author | Wolfgang Denk <wd@denx.de> | 2008-11-25 11:45:34 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-11-25 11:45:34 +0100 |
| commit | 95d4b70d50f8e426062bf9b7613829325cf779ad (patch) | |
| tree | 7fc9746f1fdb7bc9de779114ae92b6e5975b60b4 /include | |
| parent | f9b354faa0417b7f8888de246ff5f267f7cb17f2 (diff) | |
| parent | facdad5f2602e899a01746916beddbf9e856b5ee (diff) | |
| download | u-boot-imx-95d4b70d50f8e426062bf9b7613829325cf779ad.zip u-boot-imx-95d4b70d50f8e426062bf9b7613829325cf779ad.tar.gz u-boot-imx-95d4b70d50f8e426062bf9b7613829325cf779ad.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/MPC8315ERDB.h | 12 | ||||
| -rw-r--r-- | include/mpc83xx.h | 4 |
2 files changed, 9 insertions, 7 deletions
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 1225270..add65f0 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -118,23 +118,23 @@ | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) /* 0x00220802 */ -#define CONFIG_SYS_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ - | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ - | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ +#define CONFIG_SYS_DDR_TIMING_1 ( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \ + | ( 7 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ + | ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \ | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ | ( 6 << TIMING_CFG1_REFREC_SHIFT ) \ | ( 2 << TIMING_CFG1_WRREC_SHIFT ) \ | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) - /* 0x39356222 */ + /* 0x27256222 */ #define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ | ( 4 << TIMING_CFG2_CPO_SHIFT ) \ | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ - | ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) ) - /* 0x121048c7 */ + | ( 5 << TIMING_CFG2_FOUR_ACT_SHIFT) ) + /* 0x121048c5 */ #define CONFIG_SYS_DDR_INTERVAL ( ( 0x0360 << SDRAM_INTERVAL_REFINT_SHIFT ) \ | ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) /* 0x03600100 */ diff --git a/include/mpc83xx.h b/include/mpc83xx.h index a2c0ed9..43553f5 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -887,7 +887,9 @@ #define TIMING_CFG1_WRTORD_SHIFT 0 #define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ #define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ -#define TIMING_CFG1_CASLAT_30 0x00050000 /* CAS latency = 2.5 */ +#define TIMING_CFG1_CASLAT_30 0x00050000 /* CAS latency = 3.0 */ +#define TIMING_CFG1_CASLAT_35 0x00060000 /* CAS latency = 3.5 */ +#define TIMING_CFG1_CASLAT_40 0x00070000 /* CAS latency = 4.0 */ /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 */ |