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authorTom Rini <trini@ti.com>2015-02-06 12:02:59 -0500
committerTom Rini <trini@ti.com>2015-02-06 12:02:59 -0500
commit5c123f5fbfa2f7ae43f08a0f92073e90330d704a (patch)
tree8f79c94d7a04301d3ef51b4bc10571acc7bc9706 /include
parent4e79908044e4ebf186464cf118497458faf0903c (diff)
parent68102b81e8fb699087ec5757a75676c6c65af3fd (diff)
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Merge git://git.denx.de/u-boot-marvell
Diffstat (limited to 'include')
-rw-r--r--include/configs/db-mv784mp-gp.h49
-rw-r--r--include/configs/maxbcm.h49
-rw-r--r--include/configs/sheevaplug.h7
3 files changed, 104 insertions, 1 deletions
diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h
index cb03e33..1683a15 100644
--- a/include/configs/db-mv784mp-gp.h
+++ b/include/configs/db-mv784mp-gp.h
@@ -11,6 +11,8 @@
* High Level Configuration Options (easy to change)
*/
#define CONFIG_ARMADA_XP /* SOC Family Name */
+#define CONFIG_DB_784MP_GP /* Board target name for DDR training */
+
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_BOARDINFO_LATE
@@ -65,4 +67,51 @@
*/
#include "mv-common.h"
+/*
+ * Memory layout while starting into the bin_hdr via the
+ * BootROM:
+ *
+ * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
+ * 0x4000.4030 bin_hdr start address
+ * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
+ * 0x4007.fffc BootROM stack top
+ *
+ * The address space between 0x4007.fffc and 0x400f.fff is not locked in
+ * L2 cache thus cannot be used.
+ */
+
+/* SPL */
+/* Defines for SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE 0x40004030
+#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
+
+#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
+#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
+
+#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
+ CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10)
+
+#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
+#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mvebu-common/u-boot-spl.lds"
+
+/* SPL related SPI defines */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
+
+/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
+#define CONFIG_SYS_MVEBU_DDR
+#define CONFIG_SPD_EEPROM 0x4e
+
#endif /* _CONFIG_DB_MV7846MP_GP_H */
diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h
index 72217bd..5999d60 100644
--- a/include/configs/maxbcm.h
+++ b/include/configs/maxbcm.h
@@ -43,6 +43,8 @@
#define CONFIG_SF_DEFAULT_SPEED 1000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_BAR
/* Environment in SPI NOR flash */
#define CONFIG_ENV_IS_IN_SPI_FLASH
@@ -65,4 +67,51 @@
*/
#include "mv-common.h"
+/*
+ * Memory layout while starting into the bin_hdr via the
+ * BootROM:
+ *
+ * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
+ * 0x4000.4030 bin_hdr start address
+ * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
+ * 0x4007.fffc BootROM stack top
+ *
+ * The address space between 0x4007.fffc and 0x400f.fff is not locked in
+ * L2 cache thus cannot be used.
+ */
+
+/* SPL */
+/* Defines for SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE 0x40004030
+#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
+
+#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
+#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
+
+#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
+ CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10)
+
+#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
+#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mvebu-common/u-boot-spl.lds"
+
+/* SPL related SPI defines */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
+
+/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
+#define CONFIG_SYS_MVEBU_DDR
+#define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */
+
#endif /* _CONFIG_DB_MV7846MP_GP_H */
diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h
index 21c8bda..84029cb 100644
--- a/include/configs/sheevaplug.h
+++ b/include/configs/sheevaplug.h
@@ -33,6 +33,11 @@
#define CONFIG_LZO
/*
+ * Enable device tree support
+ */
+#define CONFIG_OF_LIBFDT
+
+/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
@@ -51,6 +56,7 @@
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB
+
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
@@ -141,6 +147,5 @@
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS
#define CONFIG_CMD_MTDPARTS
-#define CONFIG_LZO
#endif /* _CONFIG_SHEEVAPLUG_H */