Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

9 files changed, 105 insertions, 107 deletions

diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 1c0eb74..3169665 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -22,7 +22,7 @@
 
 /*
  * P2041 RDB board configuration file
- *
+ * Also supports P2040 RDB
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
@@ -36,6 +36,15 @@
 #define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
 #endif
 
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+/* Set 1M boot space */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_NO_FLASH
+#endif
+
 /* High Level Configuration Options */
 #define CONFIG_BOOKE
 #define CONFIG_E500			/* BOOKE e500 family */
@@ -73,7 +82,7 @@
 #define CONFIG_ENV_OVERWRITE
 
 #ifdef CONFIG_SYS_NO_FLASH
-#ifndef CONFIG_RAMBOOT_PBL
+#if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 #define CONFIG_ENV_IS_NOWHERE
 #endif
 #else
@@ -104,8 +113,12 @@
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
 #define CONFIG_ENV_OFFSET		(5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_IS_IN_REMOTE
+#define CONFIG_ENV_ADDR		0xffe20000
+#define CONFIG_ENV_SIZE		0x2000
 #elif defined(CONFIG_ENV_IS_NOWHERE)
-	#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SIZE		0x2000
 #else
 	#define CONFIG_ENV_IS_IN_FLASH
 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE \
@@ -374,6 +387,35 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */
 
 /*
+ * for slave u-boot IMAGE instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000	/* 512K */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+/*
+ * for slave UCODE and ENV instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000	/* 256K */
+
+/* slave core release by master*/
+#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+
+/*
+ * SRIO_PCIE_BOOT - SLAVE
+ */
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+#endif
+
+/*
  * eSPI - Enhanced SPI
  */
 #define CONFIG_FSL_ESPI
@@ -485,6 +527,16 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_QE_FMAN_FW_ADDR	(6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0xFFE00000
 #else
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_QE_FMAN_FW_ADDR	0xEF000000
diff --git a/include/configs/P3060QDS.h b/include/configs/P3060QDS.h
deleted file mode 100644
index 8006547..0000000
--- a/include/configs/P3060QDS.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * P3060 QDS board configuration file
- */
-#define CONFIG_P3060QDS
-#define CONFIG_PHYS_64BIT
-#define CONFIG_PPC_P3060
-#define CONFIG_FSL_QIXIS
-
-#define CONFIG_NAND_FSL_ELBC
-
-#define CONFIG_ICS307_REFCLK_HZ	25000000  /* ICS307 ref clk freq */
-
-#define CONFIG_SPI_FLASH_ATMEL
-#define CONFIG_SPI_FLASH_EON
-#define CONFIG_SPI_FLASH_SST
-
-#include "corenet_ds.h"
-
-#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
-#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
-#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
-#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
-
-/* There is a PCA9547 8-channel I2C-bus multiplexer on P3060QDS board */
-#define CONFIG_I2C_MUX
-#define CONFIG_I2C_MULTI_BUS
diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h
index 4a2e475..d6f2f5c 100644
--- a/include/configs/P4080DS.h
+++ b/include/configs/P4080DS.h
@@ -22,6 +22,7 @@
 
 /*
  * P4080 DS board configuration file
+ * Also supports P4040 DS
  */
 #define CONFIG_P4080DS
 #define CONFIG_PHYS_64BIT
diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h
index 4afc4f1..8625f76 100644
--- a/include/configs/P5020DS.h
+++ b/include/configs/P5020DS.h
@@ -22,7 +22,7 @@
 
 /*
  * P5020 DS board configuration file
- *
+ * Also supports P5010 DS
  */
 #define CONFIG_P5020DS
 #define CONFIG_PHYS_64BIT
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index f8f7a82..f4f9bd1 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -31,13 +31,21 @@
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
 #define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
+#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg
+#if defined(CONFIG_P3041DS)
+#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p3041ds.cfg
+#elif defined(CONFIG_P4080DS)
+#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p4080ds.cfg
+#elif defined(CONFIG_P5020DS)
+#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5020ds.cfg
+#endif
 #endif
 
-#ifdef CONFIG_SRIOBOOT_SLAVE
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 /* Set 1M boot space */
-#define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
-#define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS \
-		(0x300000000ull | CONFIG_SYS_SRIOBOOT_SLAVE_ADDR)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 #define CONFIG_SYS_NO_FLASH
 #endif
@@ -77,7 +85,7 @@
 #define CONFIG_ENV_OVERWRITE
 
 #ifdef CONFIG_SYS_NO_FLASH
-#if !defined(CONFIG_SRIOBOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
+#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
 #define CONFIG_ENV_IS_NOWHERE
 #endif
 #else
@@ -108,7 +116,7 @@
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
 #define CONFIG_ENV_OFFSET		(5 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_SRIOBOOT_SLAVE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 #define CONFIG_ENV_IS_IN_REMOTE
 #define CONFIG_ENV_ADDR		0xffe20000
 #define CONFIG_ENV_SIZE		0x2000
@@ -186,11 +194,7 @@
 #define CONFIG_DDR_SPD
 #define CONFIG_FSL_DDR3
 
-#ifdef CONFIG_P3060QDS
-#define CONFIG_SYS_SPD_BUS_NUM	0
-#else
 #define CONFIG_SYS_SPD_BUS_NUM	1
-#endif
 #define SPD_EEPROM_ADDRESS1	0x51
 #define SPD_EEPROM_ADDRESS2	0x52
 #define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1	/* for p3041/p5010 */
@@ -389,51 +393,32 @@
 #define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */
 
 /*
- * SRIOBOOT - MASTER
- */
-#ifdef CONFIG_SRIOBOOT_MASTER
-/* master port for srioboot*/
-#define CONFIG_SRIOBOOT_MASTER_PORT 0
-/* #define CONFIG_SRIOBOOT_MASTER_PORT 1 */
-/*
  * for slave u-boot IMAGE instored in master memory space,
  * PHYS must be aligned based on the SIZE
  */
-#define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 0xfef080000ull
-#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 0xfff80000ull
-#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE 0x80000	/* 512K */
-#define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2 0xfef080000ull
-#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 0x3fff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000	/* 512K */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
 /*
- * for slave UCODE instored in master memory space,
+ * for slave UCODE and ENV instored in master memory space,
  * PHYS must be aligned based on the SIZE
  */
-#define CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS 0xfef020000ull
-#define CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS 0x3ffe00000ull
-#define CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE 0x10000	/* 64K */
-/*
- * for slave ENV instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#define CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS 0xfef060000ull
-#define CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS 0x3ffe20000ull
-#define CONFIG_SRIOBOOT_SLAVE_ENV_SIZE 0x20000	/* 128K */
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000	/* 256K */
+
 /* slave core release by master*/
-#define CONFIG_SRIOBOOT_SLAVE_HOLDOFF
-#define CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET 0xe00e4
-#define CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK 0x00000001 /* release core 0 */
-#endif
+#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 
 /*
- * SRIOBOOT - SLAVE
+ * SRIO_PCIE_BOOT - SLAVE
  */
-#ifdef CONFIG_SRIOBOOT_SLAVE
-/* slave port for srioboot */
-#define CONFIG_SRIOBOOT_SLAVE_PORT0
-/* #define CONFIG_SRIOBOOT_SLAVE_PORT1 */
-#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR 0xFFE00000
-#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS \
-		(0x300000000ull | CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR)
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 #endif
 
 /*
@@ -556,13 +541,13 @@
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_QE_FMAN_FW_ADDR	(6 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_SRIOBOOT_SLAVE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 /*
  * Slave has no ucode locally, it can fetch this from remote. When implementing
  * in two corenet boards, slave's ucode could be stored in master's memory
  * space, the address can be mapped from slave TLB->slave LAW->
- * slave SRIO outbound window->master inbound window->master LAW->
- * the ucode address in master's NOR flash.
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 #define CONFIG_SYS_QE_FMAN_FW_ADDR	0xFFE00000
@@ -724,7 +709,7 @@
 
 #define CONFIG_BAUDRATE	115200
 
-#if defined(CONFIG_P4080DS) || defined(CONFIG_P3060QDS)
+#ifdef CONFIG_P4080DS
 #define __USB_PHY_TYPE	ulpi
 #else
 #define __USB_PHY_TYPE	utmi
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index a8882d4..b18f4a0 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -31,7 +31,7 @@
 #endif
 
 #if defined(CONFIG_P1020MBG)
-#define CONFIG_BOARDNAME "P1020MBG"
+#define CONFIG_BOARDNAME "P1020MBG-PC"
 #define CONFIG_P1020
 #define CONFIG_VSC7385_ENET
 #define CONFIG_SLIC
@@ -41,7 +41,7 @@
 #endif
 
 #if defined(CONFIG_P1020UTM)
-#define CONFIG_BOARDNAME "P1020UTM"
+#define CONFIG_BOARDNAME "P1020UTM-PC"
 #define CONFIG_P1020
 #define __SW_BOOT_MASK		0x03
 #define __SW_BOOT_NOR		0xe0
@@ -49,7 +49,7 @@
 #endif
 
 #if defined(CONFIG_P1020RDB)
-#define CONFIG_BOARDNAME "P1020RDB"
+#define CONFIG_BOARDNAME "P1020RDB-PC"
 #define CONFIG_NAND_FSL_ELBC
 #define CONFIG_P1020
 #define CONFIG_SPI_FLASH
@@ -64,7 +64,7 @@
 #endif
 
 #if defined(CONFIG_P1021RDB)
-#define CONFIG_BOARDNAME "P1021RDB"
+#define CONFIG_BOARDNAME "P1021RDB-PC"
 #define CONFIG_NAND_FSL_ELBC
 #define CONFIG_P1021
 #define CONFIG_QE
@@ -111,7 +111,7 @@
 #endif
 
 #if defined(CONFIG_P2020RDB)
-#define CONFIG_BOARDNAME "P2020RDB"
+#define CONFIG_BOARDNAME "P2020RDB-PCA"
 #define CONFIG_NAND_FSL_ELBC
 #define CONFIG_P2020
 #define CONFIG_SPI_FLASH
diff --git a/include/ddr_spd.h b/include/ddr_spd.h
index a9230b9..9e74d87 100644
--- a/include/ddr_spd.h
+++ b/include/ddr_spd.h
@@ -221,7 +221,12 @@ typedef struct ddr3_spd_eeprom_s {
 	unsigned char therm_ref_opt;   /* 31 SDRAM Thermal and Refresh Opts */
 	unsigned char therm_sensor;    /* 32 Module Thermal Sensor */
 	unsigned char device_type;     /* 33 SDRAM device type */
-	unsigned char res_34_59[26];   /* 34-59 Reserved, General Section */
+	int8_t fine_tCK_min;	       /* 34 Fine offset for tCKmin */
+	int8_t fine_tAA_min;	       /* 35 Fine offset for tAAmin */
+	int8_t fine_tRCD_min;	       /* 36 Fine offset for tRCDmin */
+	int8_t fine_tRP_min;	       /* 37 Fine offset for tRPmin */
+	int8_t fine_tRC_min;	       /* 38 Fine offset for tRCmin */
+	unsigned char res_39_59[21];   /* 39-59 Reserved, General Section */
 
 	/* Module-Specific Section: Bytes 60-116 */
 	union {
diff --git a/include/fm_eth.h b/include/fm_eth.h
index c7c6882..e56541d 100644
--- a/include/fm_eth.h
+++ b/include/fm_eth.h
@@ -35,6 +35,7 @@ enum fm_port {
 	FM2_DTSEC2,
 	FM2_DTSEC3,
 	FM2_DTSEC4,
+	FM2_DTSEC5,
 	FM2_10GEC1,
 	NUM_FM_PORTS,
 };
@@ -109,6 +110,7 @@ void fman_enet_init(void);
 void fdt_fixup_fman_ethernet(void *fdt);
 phy_interface_t fm_info_get_enet_if(enum fm_port port);
 void fm_info_set_phy_address(enum fm_port port, int address);
+int fm_info_get_phy_address(enum fm_port port);
 void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus);
 void fm_disable_port(enum fm_port port);
 
diff --git a/include/image.h b/include/image.h
index aa9daa2..e5f6649 100644
--- a/include/image.h
+++ b/include/image.h
@@ -164,6 +164,7 @@
 #define IH_TYPE_OMAPIMAGE	12	/* TI OMAP Config Header Image	*/
 #define IH_TYPE_AISIMAGE	13	/* TI Davinci AIS Image		*/
 #define IH_TYPE_KERNEL_NOLOAD	14	/* OS Kernel Image, can run from any load address */
+#define IH_TYPE_PBLIMAGE	15	/* Freescale PBL Boot Image	*/
 
 /*
  * Compression Types