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| author | Prabhakar Kushwaha <prabhakar@freescale.com> | 2014-01-27 14:41:55 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-02-03 08:38:49 -0800 |
| commit | 48aee3913d1e99b9f0b91ff0eb52700b4dd24d25 (patch) | |
| tree | 2c4c6157a99780d546ee855ba0c5f0d1b3a21390 /include | |
| parent | 9b444be32230160ee6b3e4dbf625b4201ac3897d (diff) | |
| download | u-boot-imx-48aee3913d1e99b9f0b91ff0eb52700b4dd24d25.zip u-boot-imx-48aee3913d1e99b9f0b91ff0eb52700b4dd24d25.tar.gz u-boot-imx-48aee3913d1e99b9f0b91ff0eb52700b4dd24d25.tar.bz2 | |
powerpc/t104xrdb: Update T1042RDB.h in config folder
Add usb2 node entry to hwconfig default
Remove DDR controller interleaving from hwconfig
Move SPI related macros out of "#ifdef CONFIG_SPIFLASH"
Add CONFIG_SYS_CSPR2_EXT to make CPLD accessible in u-boot
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Fix commit message]
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/T1042RDB_PI.h | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/include/configs/T1042RDB_PI.h b/include/configs/T1042RDB_PI.h index aafa813..1cbc375 100644 --- a/include/configs/T1042RDB_PI.h +++ b/include/configs/T1042RDB_PI.h @@ -79,10 +79,6 @@ #if defined(CONFIG_SPIFLASH) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 10000000 -#define CONFIG_ENV_SPI_MODE 0 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ #define CONFIG_ENV_SECT_SIZE 0x10000 @@ -202,6 +198,7 @@ /* CPLD on IFC */ #define CONFIG_SYS_CPLD_BASE 0xffdf0000 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) +#define CONFIG_SYS_CSPR2_EXT (0xf) #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ @@ -394,6 +391,10 @@ #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 /* * General PCI @@ -631,9 +632,9 @@ #define __USB_PHY_TYPE utmi #define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ - "bank_intlv=cs0_cs1;" \ - "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ + "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ "netdev=eth0\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ |