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| author | Grzegorz Bernacki <gjb@semihalf.com> | 2008-01-28 10:15:02 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-02-07 01:10:04 +0100 |
| commit | 37e3c62fa07a823e7569c872e3a9395d227ed8e3 (patch) | |
| tree | 5d75dc16dac6e0da06ca67c879eeed4d150b735b /include | |
| parent | ac9152830d7fdebace8a260b7737ef2870c21ca0 (diff) | |
| download | u-boot-imx-37e3c62fa07a823e7569c872e3a9395d227ed8e3.zip u-boot-imx-37e3c62fa07a823e7569c872e3a9395d227ed8e3.tar.gz u-boot-imx-37e3c62fa07a823e7569c872e3a9395d227ed8e3.tar.bz2 | |
ADS5121e: DDR2 init/timing update.
Signed-off-by: John Rigby <jrigby@freescale.com>
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/ads5121.h | 15 |
1 files changed, 6 insertions, 9 deletions
diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index 973f348..8d90ea1 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -109,25 +109,22 @@ * [04:00] DRAM tRPA */ -#define CFG_MDDRC_SYS_CFG 0xF8604200 -#define CFG_MDDRC_SYS_CFG_RUN 0xE8604200 -#define CFG_MDDRC_SYS_CFG_EN 0x30000000 -#define CFG_MDDRC_TIME_CFG0 0x0000281E -#define CFG_MDDRC_TIME_CFG0_RUN 0x01F4281E +#define CFG_MDDRC_SYS_CFG 0xF8604A00 +#define CFG_MDDRC_SYS_CFG_RUN 0xE8604A00 +#define CFG_MDDRC_SYS_CFG_EN 0xF0000000 +#define CFG_MDDRC_TIME_CFG0 0x00003D2E +#define CFG_MDDRC_TIME_CFG0_RUN 0x06183D2E #define CFG_MDDRC_TIME_CFG1 0x54EC1168 #define CFG_MDDRC_TIME_CFG2 0x35210864 #define CFG_MICRON_NOP 0x01380000 #define CFG_MICRON_PCHG_ALL 0x01100400 -#define CFG_MICRON_MR 0x01000022 #define CFG_MICRON_EM2 0x01020000 #define CFG_MICRON_EM3 0x01030000 #define CFG_MICRON_EN_DLL 0x01010000 -#define CFG_MICRON_RST_DLL 0x01000932 #define CFG_MICRON_RFSH 0x01080000 -#define CFG_MICRON_INIT_DEV_OP 0x01000832 +#define CFG_MICRON_INIT_DEV_OP 0x01000432 #define CFG_MICRON_OCD_DEFAULT 0x01010780 -#define CFG_MICRON_OCD_EXIT 0x01010400 /* DDR Priority Manager Configuration */ #define CFG_MDDRCGRP_PM_CFG1 0x000777AA |