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| author | Michal Simek <michal.simek@xilinx.com> | 2014-07-16 10:47:13 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2015-01-21 10:25:03 +0100 |
| commit | 345f9e195675207372efbb492f29dcfdcb938fd7 (patch) | |
| tree | 62ffafb6bc841da866df454a46ec8c6a69521f1c /include | |
| parent | a3607365f78ce79f8592e3acb4a04ab4d4ac8f36 (diff) | |
| download | u-boot-imx-345f9e195675207372efbb492f29dcfdcb938fd7.zip u-boot-imx-345f9e195675207372efbb492f29dcfdcb938fd7.tar.gz u-boot-imx-345f9e195675207372efbb492f29dcfdcb938fd7.tar.bz2 | |
fpga: xilinx: zynqpl: Setup NULL fpga_op without driver
Set fpga operations to NULL for cases where
FPGA is setup in board file but driver is not added
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/zynqpl.h | 23 |
1 files changed, 17 insertions, 6 deletions
diff --git a/include/zynqpl.h b/include/zynqpl.h index 8a9ec32..d0ff0d9 100644 --- a/include/zynqpl.h +++ b/include/zynqpl.h @@ -12,7 +12,12 @@ #include <xilinx.h> +#if defined(CONFIG_FPGA_ZYNQPL) extern struct xilinx_fpga_op zynq_op; +# define FPGA_ZYNQPL_OPS &zynq_op +#else +# define FPGA_ZYNQPL_OPS NULL +#endif #define XILINX_ZYNQ_7010 0x2 #define XILINX_ZYNQ_7015 0x1b @@ -31,21 +36,27 @@ extern struct xilinx_fpga_op zynq_op; /* Descriptor Macros */ #define XILINX_XC7Z010_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, &zynq_op, "7z010" } +{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ + "7z010" } #define XILINX_XC7Z015_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, &zynq_op, "7z015" } +{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ + "7z015" } #define XILINX_XC7Z020_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, &zynq_op, "7z020" } +{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ + "7z020" } #define XILINX_XC7Z030_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, &zynq_op, "7z030" } +{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ + "7z030" } #define XILINX_XC7Z045_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, &zynq_op, "7z045" } +{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ + "7z045" } #define XILINX_XC7Z100_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, &zynq_op, "7z100" } +{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ + "7z100" } #endif /* _ZYNQPL_H_ */ |