ppc4xx: Add Mnemonics for AMCC/IBM DDR2 SDRAM Controller

This patch completes the preprocessor mneomics for the IBM DDR2 SDRAM
controller registers (MODT and INITPLR) used by the
PowerPC405EX(r). The MMODE and MEMODE registers are unified with their
peer values used for the INITPLR MR and EMR registers,
respectively. Finally, a spelling typo is correct (MANUEL to MANUAL).

With these mnemonics in place, the CFG_SDRAM0_* magic numbers for
Kilauea are replaced by equivalent mnemonics to make it easier to
compare and contrast other 405EX(r)-based boards (e.g. during board
bring-up).

Finally, unified the SDRAM controller register dump routine such that
it can be used across all processor variants that utilize the IBM DDR2
SDRAM controller core. It produces output of the form:

	PPC4xx IBM DDR2 Register Dump:
		...
	        SDRAM_MB0CF[40] = 0x00006701
		...

which is '<mnemonic>[<DCR #>] = <value>'. The DCR number is included
since it is not uncommon that the DCR values in header files get mixed
up and it helps to validate, at a glance, they match what is printed
in the user manual.

Tested on:
  AMCC Kilauea/Haleakala:
  - NFS Linux Boot: PASSED
  - NAND Linux Boot: PASSED

Signed-off-by: Grant Erickson <gerickson@nuovations.com>
Signed-off-by: Stefan Roese <sr@denx.de>

2 files changed, 336 insertions, 76 deletions

diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h
index d01e07e..df787b3 100644
--- a/include/asm-ppc/ppc4xx-sdram.h
+++ b/include/asm-ppc/ppc4xx-sdram.h
@@ -562,7 +562,7 @@
  * SDRAM Delay Line Calibration Register
  */
 #define SDRAM_DLCR_DCLM_MASK		0x80000000
-#define SDRAM_DLCR_DCLM_MANUEL		0x80000000
+#define SDRAM_DLCR_DCLM_MANUAL		0x80000000
 #define SDRAM_DLCR_DCLM_AUTO		0x00000000
 #define SDRAM_DLCR_DLCR_MASK		0x08000000
 #define SDRAM_DLCR_DLCR_CALIBRATE	0x08000000
@@ -578,59 +578,234 @@
 #define SDRAM_DLCR_DLCV_DECODE(n)	((((u32)(n))>>0)&0x1FF)
 
 /*
+ * SDRAM Memory On Die Terimination Control Register
+ */
+#define SDRAM_MODT_ODTON_DISABLE		PPC_REG_VAL(0, 0)
+#define SDRAM_MODT_ODTON_ENABLE			PPC_REG_VAL(0, 1)
+#define SDRAM_MODT_EB1W_DISABLE			PPC_REG_VAL(1, 0)
+#define SDRAM_MODT_EB1W_ENABLE			PPC_REG_VAL(1, 1)
+#define SDRAM_MODT_EB1R_DISABLE			PPC_REG_VAL(2, 0)
+#define SDRAM_MODT_EB1R_ENABLE			PPC_REG_VAL(2, 1)
+#define SDRAM_MODT_EB0W_DISABLE			PPC_REG_VAL(7, 0)
+#define SDRAM_MODT_EB0W_ENABLE			PPC_REG_VAL(7, 1)
+#define SDRAM_MODT_EB0R_DISABLE			PPC_REG_VAL(8, 0)
+#define SDRAM_MODT_EB0R_ENABLE			PPC_REG_VAL(8, 1)
+
+/*
  * SDRAM Controller On Die Termination Register
  */
-#define SDRAM_CODT_ODT_ON			0x80000000
-#define SDRAM_CODT_ODT_OFF			0x00000000
-#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK		0x00000020
-#define SDRAM_CODT_DQS_2_5_V_DDR1		0x00000000
-#define SDRAM_CODT_DQS_1_8_V_DDR2		0x00000020
-#define SDRAM_CODT_DQS_MASK			0x00000010
-#define SDRAM_CODT_DQS_DIFFERENTIAL		0x00000000
-#define SDRAM_CODT_DQS_SINGLE_END		0x00000010
-#define SDRAM_CODT_CKSE_DIFFERENTIAL		0x00000000
-#define SDRAM_CODT_CKSE_SINGLE_END		0x00000008
-#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END	0x00000004
-#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END	0x00000002
-#define SDRAM_CODT_IO_HIZ			0x00000000
-#define SDRAM_CODT_IO_NMODE			0x00000001
+#define SDRAM_CODT_ODT_ON			PPC_REG_VAL(0, 1)
+#define SDRAM_CODT_ODT_OFF			PPC_REG_VAL(0, 0)
+#define SDRAM_CODT_RK1W_ON			PPC_REG_VAL(1, 1)
+#define SDRAM_CODT_RK1W_OFF			PPC_REG_VAL(1, 0)
+#define SDRAM_CODT_RK1R_ON			PPC_REG_VAL(2, 1)
+#define SDRAM_CODT_RK1R_OFF			PPC_REG_VAL(2, 0)
+#define SDRAM_CODT_RK0W_ON			PPC_REG_VAL(7, 1)
+#define SDRAM_CODT_RK0W_OFF			PPC_REG_VAL(7, 0)
+#define SDRAM_CODT_RK0R_ON			PPC_REG_VAL(8, 1)
+#define SDRAM_CODT_RK0R_OFF			PPC_REG_VAL(8, 0)
+#define SDRAM_CODT_ODTSH_NORMAL			PPC_REG_VAL(10, 0)
+#define SDRAM_CODT_ODTSH_REMOVE_ONE_AT_END	PPC_REG_VAL(10, 1)
+#define SDRAM_CODT_ODTSH_ADD_ONE_AT_START	PPC_REG_VAL(10, 2)
+#define SDRAM_CODT_ODTSH_SHIFT_ONE_EARLIER	PPC_REG_VAL(10, 3)
+#define SDRAM_CODT_CODTZ_75OHM			PPC_REG_VAL(11, 0)
+#define SDRAM_CODT_CKEG_ON			PPC_REG_VAL(12, 1)
+#define SDRAM_CODT_CKEG_OFF			PPC_REG_VAL(12, 0)
+#define SDRAM_CODT_CTLG_ON			PPC_REG_VAL(13, 1)
+#define SDRAM_CODT_CTLG_OFF			PPC_REG_VAL(13, 0)
+#define SDRAM_CODT_FBDG_ON			PPC_REG_VAL(14, 1)
+#define SDRAM_CODT_FBDG_OFF			PPC_REG_VAL(14, 0)
+#define SDRAM_CODT_FBRG_ON			PPC_REG_VAL(15, 1)
+#define SDRAM_CODT_FBRG_OFF			PPC_REG_VAL(15, 0)
+#define SDRAM_CODT_CKLZ_36OHM			PPC_REG_VAL(18, 1)
+#define SDRAM_CODT_CKLZ_18OHM			PPC_REG_VAL(18, 0)
+#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK		PPC_REG_VAL(26, 1)
+#define SDRAM_CODT_DQS_2_5_V_DDR1		PPC_REG_VAL(26, 0)
+#define SDRAM_CODT_DQS_1_8_V_DDR2		PPC_REG_VAL(26, 1)
+#define SDRAM_CODT_DQS_MASK			PPC_REG_VAL(27, 1)
+#define SDRAM_CODT_DQS_DIFFERENTIAL		PPC_REG_VAL(27, 0)
+#define SDRAM_CODT_DQS_SINGLE_END		PPC_REG_VAL(27, 1)
+#define SDRAM_CODT_CKSE_DIFFERENTIAL		PPC_REG_VAL(28, 0)
+#define SDRAM_CODT_CKSE_SINGLE_END		PPC_REG_VAL(28, 1)
+#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END	PPC_REG_VAL(29, 1)
+#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END	PPC_REG_VAL(30, 1)
+#define SDRAM_CODT_IO_HIZ			PPC_REG_VAL(31, 0)
+#define SDRAM_CODT_IO_NMODE			PPC_REG_VAL(31, 1)
+
+/*
+ * SDRAM Initialization Preload Register
+ */
+#define SDRAM_INITPLR_ENABLE			PPC_REG_VAL(0, 1)
+#define SDRAM_INITPLR_DISABLE			PPC_REG_VAL(0, 0)
+#define SDRAM_INITPLR_IMWT_MASK			PPC_REG_VAL(8, 0xFF)
+#define SDRAM_INITPLR_IMWT_ENCODE(n)		PPC_REG_VAL(8, \
+							    (static_cast(u32, \
+									 n)) \
+							    & 0xFF)
+#define SDRAM_INITPLR_ICMD_MASK			PPC_REG_VAL(12, 0x7)
+#define SDRAM_INITPLR_ICMD_ENCODE(n)		PPC_REG_VAL(12, \
+							    (static_cast(u32, \
+									 n)) \
+							    & 0x7)
+#define SDRAM_INITPLR_IBA_MASK			PPC_REG_VAL(15, 0x7)
+#define SDRAM_INITPLR_IBA_ENCODE(n)		PPC_REG_VAL(15, \
+							    (static_cast(u32, \
+									 n)) \
+							    & 0x7)
+#define SDRAM_INITPLR_IMA_MASK			PPC_REG_VAL(31, 0x7FFF)
+#define SDRAM_INITPLR_IMA_ENCODE(n)		PPC_REG_VAL(31, \
+							    (static_cast(u32, \
+									 n)) \
+							    & 0x7FFF)
+
+/*
+ * JEDEC DDR Initialization Commands
+ */
+#define JEDEC_CMD_NOP				7
+#define JEDEC_CMD_PRECHARGE			2
+#define JEDEC_CMD_REFRESH			1
+#define JEDEC_CMD_EMR				0
+#define JEDEC_CMD_READ				5
+#define JEDEC_CMD_WRITE				4
+
+/*
+ * JEDEC Precharge Command Memory Address Arguments
+ */
+#define JEDEC_MA_PRECHARGE_ONE			(0 << 10)
+#define JEDEC_MA_PRECHARGE_ALL			(1 << 10)
+
+/*
+ * JEDEC DDR EMR Command Bank Address Arguments
+ */
+#define JEDEC_BA_MR				0
+#define JEDEC_BA_EMR				1
+#define JEDEC_BA_EMR2				2
+#define JEDEC_BA_EMR3				3
+
+/*
+ * JEDEC DDR Mode Register
+ */
+#define JEDEC_MA_MR_PDMODE_FAST_EXIT		(0 << 12)
+#define JEDEC_MA_MR_PDMODE_SLOW_EXIT		(1 << 12)
+#define JEDEC_MA_MR_WR_MASK			(0x7 << 9)
+#define JEDEC_MA_MR_WR_DDR1			(0x0 << 9)
+#define JEDEC_MA_MR_WR_DDR2_2_CYC		(0x1 << 9)
+#define JEDEC_MA_MR_WR_DDR2_3_CYC		(0x2 << 9)
+#define JEDEC_MA_MR_WR_DDR2_4_CYC		(0x3 << 9)
+#define JEDEC_MA_MR_WR_DDR2_5_CYC		(0x4 << 9)
+#define JEDEC_MA_MR_WR_DDR2_6_CYC		(0x5 << 9)
+#define JEDEC_MA_MR_DLL_RESET			(1 << 8)
+#define JEDEC_MA_MR_MODE_NORMAL			(0 << 8)
+#define JEDEC_MA_MR_MODE_TEST			(1 << 8)
+#define JEDEC_MA_MR_CL_MASK			(0x7 << 4)
+#define JEDEC_MA_MR_CL_DDR1_2_0_CLK		(0x2 << 4)
+#define JEDEC_MA_MR_CL_DDR1_2_5_CLK		(0x6 << 4)
+#define JEDEC_MA_MR_CL_DDR1_3_0_CLK		(0x3 << 4)
+#define JEDEC_MA_MR_CL_DDR2_2_0_CLK		(0x2 << 4)
+#define JEDEC_MA_MR_CL_DDR2_3_0_CLK		(0x3 << 4)
+#define JEDEC_MA_MR_CL_DDR2_4_0_CLK		(0x4 << 4)
+#define JEDEC_MA_MR_CL_DDR2_5_0_CLK		(0x5 << 4)
+#define JEDEC_MA_MR_CL_DDR2_6_0_CLK		(0x6 << 4)
+#define JEDEC_MA_MR_CL_DDR2_7_0_CLK		(0x7 << 4)
+#define JEDEC_MA_MR_BTYP_SEQUENTIAL		(0 << 3)
+#define JEDEC_MA_MR_BTYP_INTERLEAVED		(1 << 3)
+#define JEDEC_MA_MR_BLEN_MASK			(0x7 << 0)
+#define JEDEC_MA_MR_BLEN_4			(2 << 0)
+#define JEDEC_MA_MR_BLEN_8			(3 << 0)
+
+/*
+ * JEDEC DDR Extended Mode Register
+ */
+#define JEDEC_MA_EMR_OUTPUT_MASK		(1 << 12)
+#define JEDEC_MA_EMR_OUTPUT_ENABLE		(0 << 12)
+#define JEDEC_MA_EMR_OUTPUT_DISABLE		(1 << 12)
+#define JEDEC_MA_EMR_RQDS_MASK			(1 << 11)
+#define JEDEC_MA_EMR_RDQS_DISABLE		(0 << 11)
+#define JEDEC_MA_EMR_RDQS_ENABLE		(1 << 11)
+#define JEDEC_MA_EMR_DQS_MASK			(1 << 10)
+#define JEDEC_MA_EMR_DQS_DISABLE		(1 << 10)
+#define JEDEC_MA_EMR_DQS_ENABLE			(0 << 10)
+#define JEDEC_MA_EMR_OCD_MASK			(0x7 << 7)
+#define JEDEC_MA_EMR_OCD_EXIT			(0 << 7)
+#define JEDEC_MA_EMR_OCD_ENTER			(7 << 7)
+#define JEDEC_MA_EMR_AL_DDR1_0_CYC		(0 << 3)
+#define JEDEC_MA_EMR_AL_DDR2_1_CYC		(1 << 3)
+#define JEDEC_MA_EMR_AL_DDR2_2_CYC		(2 << 3)
+#define JEDEC_MA_EMR_AL_DDR2_3_CYC		(3 << 3)
+#define JEDEC_MA_EMR_AL_DDR2_4_CYC		(4 << 3)
+#define JEDEC_MA_EMR_RTT_MASK			(0x11 << 2)
+#define JEDEC_MA_EMR_RTT_DISABLED		(0x00 << 2)
+#define JEDEC_MA_EMR_RTT_75OHM			(0x01 << 2)
+#define JEDEC_MA_EMR_RTT_150OHM			(0x10 << 2)
+#define JEDEC_MA_EMR_RTT_50OHM			(0x11 << 2)
+#define JEDEC_MA_EMR_ODS_MASK			(1 << 1)
+#define JEDEC_MA_EMR_ODS_NORMAL			(0 << 1)
+#define JEDEC_MA_EMR_ODS_WEAK			(1 << 1)
+#define JEDEC_MA_EMR_DLL_MASK			(1 << 0)
+#define JEDEC_MA_EMR_DLL_ENABLE			(0 << 0)
+#define JEDEC_MA_EMR_DLL_DISABLE		(1 << 0)
+
+/*
+ * JEDEC DDR Extended Mode Register 2
+ */
+#define JEDEC_MA_EMR2_TEMP_COMMERCIAL		(0 << 7)
+#define JEDEC_MA_EMR2_TEMP_INDUSTRIAL		(1 << 7)
 
 /*
- * SDRAM Mode Register
+ * SDRAM Mode Register (Corresponds 1:1 w/ JEDEC Mode Register)
  */
-#define SDRAM_MMODE_WR_MASK		0x00000E00
-#define SDRAM_MMODE_WR_DDR1		0x00000000
-#define SDRAM_MMODE_WR_DDR2_3_CYC	0x00000400
-#define SDRAM_MMODE_WR_DDR2_4_CYC	0x00000600
-#define SDRAM_MMODE_WR_DDR2_5_CYC	0x00000800
-#define SDRAM_MMODE_WR_DDR2_6_CYC	0x00000A00
-#define SDRAM_MMODE_DCL_MASK		0x00000070
-#define SDRAM_MMODE_DCL_DDR1_2_0_CLK	0x00000020
-#define SDRAM_MMODE_DCL_DDR1_2_5_CLK	0x00000060
-#define SDRAM_MMODE_DCL_DDR1_3_0_CLK	0x00000030
-#define SDRAM_MMODE_DCL_DDR2_2_0_CLK	0x00000020
-#define SDRAM_MMODE_DCL_DDR2_3_0_CLK	0x00000030
-#define SDRAM_MMODE_DCL_DDR2_4_0_CLK	0x00000040
-#define SDRAM_MMODE_DCL_DDR2_5_0_CLK	0x00000050
-#define SDRAM_MMODE_DCL_DDR2_6_0_CLK	0x00000060
-#define SDRAM_MMODE_DCL_DDR2_7_0_CLK	0x00000070
+#define SDRAM_MMODE_WR_MASK			JEDEC_MA_MR_WR_MASK
+#define SDRAM_MMODE_WR_DDR1			JEDEC_MA_MR_WR_DDR1
+#define SDRAM_MMODE_WR_DDR2_2_CYC		JEDEC_MA_MR_WR_DDR2_2_CYC
+#define SDRAM_MMODE_WR_DDR2_3_CYC		JEDEC_MA_MR_WR_DDR2_3_CYC
+#define SDRAM_MMODE_WR_DDR2_4_CYC		JEDEC_MA_MR_WR_DDR2_4_CYC
+#define SDRAM_MMODE_WR_DDR2_5_CYC		JEDEC_MA_MR_WR_DDR2_5_CYC
+#define SDRAM_MMODE_WR_DDR2_6_CYC		JEDEC_MA_MR_WR_DDR2_6_CYC
+#define SDRAM_MMODE_DCL_MASK			JEDEC_MA_MR_CL_MASK
+#define SDRAM_MMODE_DCL_DDR1_2_0_CLK		JEDEC_MA_MR_CL_DDR1_2_0_CLK
+#define SDRAM_MMODE_DCL_DDR1_2_5_CLK		JEDEC_MA_MR_CL_DDR1_2_5_CLK
+#define SDRAM_MMODE_DCL_DDR1_3_0_CLK		JEDEC_MA_MR_CL_DDR1_3_0_CLK
+#define SDRAM_MMODE_DCL_DDR2_2_0_CLK		JEDEC_MA_MR_CL_DDR2_2_0_CLK
+#define SDRAM_MMODE_DCL_DDR2_3_0_CLK		JEDEC_MA_MR_CL_DDR2_3_0_CLK
+#define SDRAM_MMODE_DCL_DDR2_4_0_CLK		JEDEC_MA_MR_CL_DDR2_4_0_CLK
+#define SDRAM_MMODE_DCL_DDR2_5_0_CLK		JEDEC_MA_MR_CL_DDR2_5_0_CLK
+#define SDRAM_MMODE_DCL_DDR2_6_0_CLK		JEDEC_MA_MR_CL_DDR2_6_0_CLK
+#define SDRAM_MMODE_DCL_DDR2_7_0_CLK		JEDEC_MA_MR_CL_DDR2_7_0_CLK
+#define SDRAM_MMODE_BTYP_SEQUENTIAL		JEDEC_MA_MR_BTYP_SEQUENTIAL
+#define SDRAM_MMODE_BTYP_INTERLEAVED		JEDEC_MA_MR_BTYP_INTERLEAVED
+#define SDRAM_MMODE_BLEN_MASK			JEDEC_MA_MR_BLEN_MASK
+#define SDRAM_MMODE_BLEN_4			JEDEC_MA_MR_BLEN_4
+#define SDRAM_MMODE_BLEN_8			JEDEC_MA_MR_BLEN_8
 
 /*
- * SDRAM Extended Mode Register
+ * SDRAM Extended Mode Register (Corresponds 1:1 w/ JEDEC Extended
+ * Mode Register)
  */
-#define SDRAM_MEMODE_DIC_MASK		0x00000002
-#define SDRAM_MEMODE_DIC_NORMAL		0x00000000
-#define SDRAM_MEMODE_DIC_WEAK		0x00000002
-#define SDRAM_MEMODE_DLL_MASK		0x00000001
-#define SDRAM_MEMODE_DLL_DISABLE	0x00000001
-#define SDRAM_MEMODE_DLL_ENABLE		0x00000000
-#define SDRAM_MEMODE_RTT_MASK		0x00000044
-#define SDRAM_MEMODE_RTT_DISABLED	0x00000000
-#define SDRAM_MEMODE_RTT_75OHM		0x00000004
-#define SDRAM_MEMODE_RTT_150OHM		0x00000040
-#define SDRAM_MEMODE_DQS_MASK		0x00000400
-#define SDRAM_MEMODE_DQS_DISABLE	0x00000400
-#define SDRAM_MEMODE_DQS_ENABLE		0x00000000
+#define SDRAM_MEMODE_QOFF_MASK			JEDEC_MA_EMR_OUTPUT_MASK
+#define SDRAM_MEMODE_QOFF_DISABLE		JEDEC_MA_EMR_OUTPUT_DISABLE
+#define SDRAM_MEMODE_QOFF_ENABLE		JEDEC_MA_EMR_OUTPUT_ENABLE
+#define SDRAM_MEMODE_RDQS_MASK			JEDEC_MA_EMR_RQDS_MASK
+#define SDRAM_MEMODE_RDQS_DISABLE		JEDEC_MA_EMR_RDQS_DISABLE
+#define SDRAM_MEMODE_RDQS_ENABLE		JEDEC_MA_EMR_RDQS_ENABLE
+#define SDRAM_MEMODE_DQS_MASK			JEDEC_MA_EMR_DQS_MASK
+#define SDRAM_MEMODE_DQS_DISABLE		JEDEC_MA_EMR_DQS_DISABLE
+#define SDRAM_MEMODE_DQS_ENABLE			JEDEC_MA_EMR_DQS_ENABLE
+#define SDRAM_MEMODE_AL_DDR1_0_CYC		JEDEC_MA_EMR_AL_DDR1_0_CYC
+#define SDRAM_MEMODE_AL_DDR2_1_CYC		JEDEC_MA_EMR_AL_DDR2_1_CYC
+#define SDRAM_MEMODE_AL_DDR2_2_CYC		JEDEC_MA_EMR_AL_DDR2_2_CYC
+#define SDRAM_MEMODE_AL_DDR2_3_CYC		JEDEC_MA_EMR_AL_DDR2_3_CYC
+#define SDRAM_MEMODE_AL_DDR2_4_CYC		JEDEC_MA_EMR_AL_DDR2_4_CYC
+#define SDRAM_MEMODE_RTT_MASK			JEDEC_MA_EMR_RTT_MASK
+#define SDRAM_MEMODE_RTT_DISABLED		JEDEC_MA_EMR_RTT_DISABLED
+#define SDRAM_MEMODE_RTT_75OHM			JEDEC_MA_EMR_RTT_75OHM
+#define SDRAM_MEMODE_RTT_150OHM			JEDEC_MA_EMR_RTT_150OHM
+#define SDRAM_MEMODE_RTT_50OHM			JEDEC_MA_EMR_RTT_50OHM
+#define SDRAM_MEMODE_DIC_MASK			JEDEC_MA_EMR_ODS_MASK
+#define SDRAM_MEMODE_DIC_NORMAL			JEDEC_MA_EMR_ODS_NORMAL
+#define SDRAM_MEMODE_DIC_WEAK			JEDEC_MA_EMR_ODS_WEAK
+#define SDRAM_MEMODE_DLL_MASK			JEDEC_MA_EMR_DLL_MASK
+#define SDRAM_MEMODE_DLL_DISABLE		JEDEC_MA_EMR_DLL_DISABLE
+#define SDRAM_MEMODE_DLL_ENABLE			JEDEC_MA_EMR_DLL_ENABLE
 
 /*
  * SDRAM Clock Timing Register
diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h
index 9c1a3a4..f3d048c 100644
--- a/include/configs/kilauea.h
+++ b/include/configs/kilauea.h
@@ -233,39 +233,124 @@
 #define CFG_SDRAM0_MB1CF	SDRAM_RXBAS_SDBE_DISABLE
 #define CFG_SDRAM0_MB2CF	SDRAM_RXBAS_SDBE_DISABLE
 #define CFG_SDRAM0_MB3CF	SDRAM_RXBAS_SDBE_DISABLE
-#define CFG_SDRAM0_MCOPT1	0x04322000
+#define CFG_SDRAM0_MCOPT1	(SDRAM_MCOPT1_PMU_OPEN		| \
+				 SDRAM_MCOPT1_8_BANKS		| \
+				 SDRAM_MCOPT1_DDR2_TYPE		| \
+				 SDRAM_MCOPT1_QDEP		| \
+				 SDRAM_MCOPT1_DCOO_DISABLED)
 #define CFG_SDRAM0_MCOPT2	0x00000000
-#define CFG_SDRAM0_MODT0	0x01800000
+#define CFG_SDRAM0_MODT0	(SDRAM_MODT_EB0W_ENABLE | \
+				 SDRAM_MODT_EB0R_ENABLE)
 #define CFG_SDRAM0_MODT1	0x00000000
-#define CFG_SDRAM0_CODT		0x0080f837
-#define CFG_SDRAM0_RTR		0x06180000
-#define CFG_SDRAM0_INITPLR0	0xa8380000
-#define CFG_SDRAM0_INITPLR1	0x81900400
-#define CFG_SDRAM0_INITPLR2	0x81020000
-#define CFG_SDRAM0_INITPLR3	0x81030000
-#define CFG_SDRAM0_INITPLR4	0x81010404
-#define CFG_SDRAM0_INITPLR5	0x81000542
-#define CFG_SDRAM0_INITPLR6	0x81900400
-#define CFG_SDRAM0_INITPLR7	0x8D080000
-#define CFG_SDRAM0_INITPLR8	0x8D080000
-#define CFG_SDRAM0_INITPLR9	0x8D080000
-#define CFG_SDRAM0_INITPLR10	0x8D080000
-#define CFG_SDRAM0_INITPLR11	0x81000442
-#define CFG_SDRAM0_INITPLR12	0x81010780
-#define CFG_SDRAM0_INITPLR13	0x81010400
-#define CFG_SDRAM0_INITPLR14	0x00000000
-#define CFG_SDRAM0_INITPLR15	0x00000000
-#define CFG_SDRAM0_RQDC		0x80000038
-#define CFG_SDRAM0_RFDC		0x00000209
-#define CFG_SDRAM0_RDCC		0x40000000
-#define CFG_SDRAM0_DLCR		0x030000a5
-#define CFG_SDRAM0_CLKTR	0x80000000
+#define CFG_SDRAM0_CODT		(SDRAM_CODT_RK0R_ON		| \
+				 SDRAM_CODT_CKLZ_36OHM		| \
+				 SDRAM_CODT_DQS_1_8_V_DDR2	| \
+				 SDRAM_CODT_IO_NMODE)
+#define CFG_SDRAM0_RTR		SDRAM_RTR_RINT_ENCODE(1560)
+#define CFG_SDRAM0_INITPLR0	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(80)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
+#define CFG_SDRAM0_INITPLR1	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(3)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)		| \
+		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)			| \
+		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
+#define CFG_SDRAM0_INITPLR2	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(2)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)		| \
+		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2)			| \
+		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
+#define CFG_SDRAM0_INITPLR3	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(2)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)		| \
+		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3)			| \
+		SDRAM_INITPLR_IMA_ENCODE(0))
+#define CFG_SDRAM0_INITPLR4	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(2)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)		| \
+		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)			| \
+		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \
+					 JEDEC_MA_EMR_RTT_75OHM))
+#define CFG_SDRAM0_INITPLR5	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(2)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)		| \
+		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)			| \
+		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
+					 JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
+					 JEDEC_MA_MR_BLEN_4 | \
+					 JEDEC_MA_MR_DLL_RESET))
+#define CFG_SDRAM0_INITPLR6	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(3)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)		| \
+		SDRAM_INITPLR_IBA_ENCODE(0x0)				| \
+		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
+#define CFG_SDRAM0_INITPLR7	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(26)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
+#define CFG_SDRAM0_INITPLR8	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(26)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
+#define CFG_SDRAM0_INITPLR9	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(26)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
+#define CFG_SDRAM0_INITPLR10	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(26)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
+#define CFG_SDRAM0_INITPLR11	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(2)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)		| \
+		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)			| \
+		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
+					 JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
+					 JEDEC_MA_MR_BLEN_4))
+#define CFG_SDRAM0_INITPLR12	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(2)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)		| \
+		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)			| \
+		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER	| \
+					 JEDEC_MA_EMR_RDQS_DISABLE | \
+					 JEDEC_MA_EMR_DQS_DISABLE | \
+					 JEDEC_MA_EMR_RTT_DISABLED | \
+					 JEDEC_MA_EMR_ODS_NORMAL))
+#define CFG_SDRAM0_INITPLR13	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(2)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)		| \
+		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)			| \
+		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
+					 JEDEC_MA_EMR_RDQS_DISABLE | \
+					 JEDEC_MA_EMR_DQS_DISABLE | \
+					 JEDEC_MA_EMR_RTT_DISABLED | \
+					 JEDEC_MA_EMR_ODS_NORMAL))
+#define CFG_SDRAM0_INITPLR14	(SDRAM_INITPLR_DISABLE)
+#define CFG_SDRAM0_INITPLR15	(SDRAM_INITPLR_DISABLE)
+#define CFG_SDRAM0_RQDC		(SDRAM_RQDC_RQDE_ENABLE | \
+				 SDRAM_RQDC_RQFD_ENCODE(56))
+#define CFG_SDRAM0_RFDC		SDRAM_RFDC_RFFD_ENCODE(521)
+#define CFG_SDRAM0_RDCC		(SDRAM_RDCC_RDSS_T2)
+#define CFG_SDRAM0_DLCR		(SDRAM_DLCR_DCLM_AUTO		| \
+				 SDRAM_DLCR_DLCS_CONT_DONE	| \
+				 SDRAM_DLCR_DLCV_ENCODE(165))
+#define CFG_SDRAM0_CLKTR	(SDRAM_CLKTR_CLKP_180_DEG_ADV)
 #define CFG_SDRAM0_WRDTR	0x00000000
-#define CFG_SDRAM0_SDTR1	0x80201000
-#define CFG_SDRAM0_SDTR2	0x32204232
-#define CFG_SDRAM0_SDTR3	0x080b0d1a
-#define CFG_SDRAM0_MMODE	0x00000442
-#define CFG_SDRAM0_MEMODE	0x00000404
+#define CFG_SDRAM0_SDTR1	(SDRAM_SDTR1_LDOF_2_CLK	| \
+				 SDRAM_SDTR1_RTW_2_CLK	| \
+				 SDRAM_SDTR1_RTRO_1_CLK)
+#define CFG_SDRAM0_SDTR2	(SDRAM_SDTR2_RCD_3_CLK		| \
+				 SDRAM_SDTR2_WTR_2_CLK		| \
+				 SDRAM_SDTR2_XSNR_32_CLK	| \
+				 SDRAM_SDTR2_WPC_4_CLK		| \
+				 SDRAM_SDTR2_RPC_2_CLK		| \
+				 SDRAM_SDTR2_RP_3_CLK		| \
+				 SDRAM_SDTR2_RRD_2_CLK)
+#define CFG_SDRAM0_SDTR3	(SDRAM_SDTR3_RAS_ENCODE(8)	| \
+				 SDRAM_SDTR3_RC_ENCODE(11)	| \
+				 SDRAM_SDTR3_XCS		| \
+				 SDRAM_SDTR3_RFC_ENCODE(26))
+#define CFG_SDRAM0_MMODE	(SDRAM_MMODE_WR_DDR2_3_CYC | \
+				 SDRAM_MMODE_DCL_DDR2_4_0_CLK | \
+				 SDRAM_MMODE_BLEN_4)
+#define CFG_SDRAM0_MEMODE	(SDRAM_MEMODE_DQS_DISABLE | \
+				 SDRAM_MEMODE_RTT_75OHM)
 
 /*-----------------------------------------------------------------------
  * I2C