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| author | Marek Vasut <marex@denx.de> | 2014-09-08 14:08:45 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2014-10-06 17:46:49 +0200 |
| commit | 2110eeaf0fdf9b3b200076554d266459ca7ac26d (patch) | |
| tree | 17420a2d561027e861b4d77f00aa67efa87954a9 /include | |
| parent | 498d1a62db4374c9d6223771bcbe8ae612a0f59f (diff) | |
| download | u-boot-imx-2110eeaf0fdf9b3b200076554d266459ca7ac26d.zip u-boot-imx-2110eeaf0fdf9b3b200076554d266459ca7ac26d.tar.gz u-boot-imx-2110eeaf0fdf9b3b200076554d266459ca7ac26d.tar.bz2 | |
arm: socfpga: timer: Pull the timer reload value from config file
The timer reload value is a property of the timer hardware and there
is no reason for this to be configurable. Place this into the timer
driver just like on the other hardware.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/socfpga_cyclone5.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 708309b..54343b8 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -195,8 +195,6 @@ /* This timer use eosc1 where the clock frequency is fixed * throughout any condition */ #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS -/* reload value when timer count to zero */ -#define TIMER_LOAD_VAL 0xFFFFFFFF /* Timer info */ #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET #define CONFIG_SYS_TIMER_RATE 2400000 |