Patch by Jon Loeliger, 16 Jul 2004:

- support larger DDR memories up to 2G on the PC8540/8560ADS and
  STXGP3 boards
- Made MPC8540/8560ADS be 33Mhz PCI by default.
- Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16
  and CONFIG_L2_INIT_RAM options.
- Refactor Local Bus initialization out of SDRAM setup.
- Re-implement new version of LBC11/DDR11 errata workarounds.
- Moved board specific PCI init parts out of CPU directory.
- Added TLB entry for PCI-1 IO Memory
- Updated README.mpc85xxads

4 files changed, 227 insertions, 254 deletions

diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index b967b1e..74e15c7 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -49,12 +49,6 @@
 #define CONFIG_DDR_DLL			/* possible DLL fix needed */
 #define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
 
-/*
- * Use Localbus SDRAM to emulate flash before we can program the flash.
- * Normally you need a flash-boot image(u-boot.bin).
- * If unsure #undef this.
- */
-#undef CONFIG_RAM_AS_FLASH
 
 /*
  * sysclk for MPC85xx
@@ -64,24 +58,17 @@
  *    66000000
  *
  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
- * is likely the desired value here.  The board, however, can run and
- * defaults to 66Mhz.  In any event, this value must match the settings
- * of SW15[1] and SW17[8], and likely SW6[0:1], the SYSCLK as well.
- *
- *	SW17[8] ------+    SW6
- *	SW15[1] ----+ |   [0:1]
- *		    V V    V V
- *	33MHz	    1 1    1 0
- *	66MHz	    0 0    0 1
+ * is likely the desired value here, so that is now the default.
+ * The board, however, can run at 66MHz.  In any event, this value
+ * must match the settings of some switches.  Details can be found
+ * in the README.mpc85xxads.
  */
 
-#define CONFIG_SYS_CLK_FREQ	66000000
-
-
-#if !defined(CONFIG_SPD_EEPROM)
-#define CONFIG_DDR_SETTING	/* manually set up DDR parameters */
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ	33000000
 #endif
 
+
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
@@ -104,27 +91,42 @@
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
+
+/*
+ * DDR Setup
+ */
 #define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
 #define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
-#define CFG_SDRAM_SIZE		128             /* DDR is 128MB */
+
+#if defined(CONFIG_SPD_EEPROM)
+    /*
+     * Determine DDR configuration from I2C interface.
+     */
+    #define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+
+#else
+    /*
+     * Manually set up DDR parameters
+     */
+    #define CFG_SDRAM_SIZE	128		/* DDR is 128MB */
+    #define CFG_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
+    #define CFG_DDR_CS0_CONFIG	0x80000002
+    #define CFG_DDR_TIMING_1	0x37344321
+    #define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
+    #define CFG_DDR_CONTROL	0xc2000000	/* unbuffered,no DYN_PWR */
+    #define CFG_DDR_MODE	0x00000062	/* DLL,normal,seq,4/2.5 */
+    #define CFG_DDR_INTERVAL	0x05200100	/* autocharge,no open page */
+#endif
+
 
 /*
  * SDRAM on the Local Bus
  */
-#if defined(CONFIG_RAM_AS_FLASH)
-#define CFG_LBC_SDRAM_BASE	0xfc000000	/* Localbus SDRAM */
-#else
 #define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
-#endif
 #define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
 
-#if defined(CONFIG_RAM_AS_FLASH)
-#define CFG_FLASH_BASE		0xf8000000	/* start of FLASH 16M */
-#define CFG_BR0_PRELIM		0xf8001801	/* port size 32bit */
-#else /* Boot from real Flash */
 #define CFG_FLASH_BASE		0xff000000	/* start of FLASH 16M */
 #define CFG_BR0_PRELIM		0xff001801	/* port size 32bit */
-#endif
 
 #define CFG_OR0_PRELIM		0xff006ff7	/* 16MB Flash */
 #define CFG_MAX_FLASH_BANKS	1		/* number of banks */
@@ -142,20 +144,9 @@
 #undef  CFG_RAMBOOT
 #endif
 
-#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
-#if defined(CONFIG_DDR_SETTING)
-#define CFG_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
-#define CFG_DDR_CS0_CONFIG	0x80000002
-#define CFG_DDR_TIMING_1	0x37344321
-#define CFG_DDR_TIMING_2	0x00000800  /* P9-45,may need tuning */
-#define CFG_DDR_CONTROL		0xc2000000  /* unbuffered,no DYN_PWR */
-#define CFG_DDR_MODE		0x00000062  /* DLL,normal,seq,4/2.5 */
-#define CFG_DDR_INTERVAL	0x05200100  /* autocharge,no open page */
-#endif
-
 
 /*
  * Local Bus Definitions
@@ -244,28 +235,27 @@
  * SDRAM Controller configuration sequence.
  */
 #define CFG_LBC_LSDMR_1		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_PCHALL)  /*0x2861b723*/
+				| CFG_LBC_LSDMR_OP_PCHALL)
 #define CFG_LBC_LSDMR_2		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_ARFRSH)  /*0x0861b723*/
+				| CFG_LBC_LSDMR_OP_ARFRSH)
 #define CFG_LBC_LSDMR_3		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_ARFRSH)  /*0x0861b723*/
+				| CFG_LBC_LSDMR_OP_ARFRSH)
 #define CFG_LBC_LSDMR_4		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_MRW)     /*0x1861b723*/
+				| CFG_LBC_LSDMR_OP_MRW)
 #define CFG_LBC_LSDMR_5		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_NORMAL)  /*0x4061b723*/
+				| CFG_LBC_LSDMR_OP_NORMAL)
 
 
-#if defined(CONFIG_RAM_AS_FLASH)
-#define CFG_BR4_PRELIM          0xf8000801      /* 32KB, 8-bit wide for ADS config reg */
-#else
-#define CFG_BR4_PRELIM          0xf8000801      /* 32KB, 8-bit wide for ADS config reg */
-#endif
+/*
+ * 32KB, 8-bit wide for ADS config reg
+ */
+#define CFG_BR4_PRELIM          0xf8000801
 #define CFG_OR4_PRELIM		0xffffe1f1
 #define CFG_BCSR		(CFG_BR4_PRELIM & 0xffff8000)
 
 #define CONFIG_L1_INIT_RAM
 #define CFG_INIT_RAM_LOCK 	1
-#define CFG_INIT_RAM_ADDR	0x40000000	/* Initial RAM address */
+#define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
 #define CFG_INIT_RAM_END    	0x4000	    	/* End of used area in RAM */
 
 #define CFG_GBL_DATA_SIZE  	128		/* num bytes initial data */
@@ -321,7 +311,7 @@
 #if defined(CONFIG_PCI)
 
 #define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP		       	/* do pci plug-and-play */
+#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
 
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP
@@ -347,13 +337,15 @@
 #define CONFIG_MII		1	/* MII PHY management */
 #define CONFIG_MPC85XX_TSEC1	1
 #define CONFIG_MPC85XX_TSEC2	1
-#define CONFIG_MPC85XX_FEC	1
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
-#define FEC_PHY_ADDR		3
 #define TSEC1_PHYIDX		0
 #define TSEC2_PHYIDX		0
+
+#define CONFIG_MPC85XX_FEC	1
+#define FEC_PHY_ADDR		3
 #define FEC_PHYIDX		0
+
 #define CONFIG_ETHPRIME		"MOTO ENET0"
 
 #endif	/* CONFIG_TSEC_ENET */
@@ -363,27 +355,21 @@
  * Environment
  */
 #ifndef CFG_RAMBOOT
-  #if defined(CONFIG_RAM_AS_FLASH)
-  #define CFG_ENV_IS_NOWHERE
-  #define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x100000)
-  #define CFG_ENV_SIZE		0x2000
-  #else
   #define CFG_ENV_IS_IN_FLASH	1
   #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
   #define CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
-  #endif
   #define CFG_ENV_SIZE		0x2000
 #else
-#define CFG_NO_FLASH		1	/* Flash is not usable now */
-#define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
-#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
-#define CFG_ENV_SIZE		0x2000
+  #define CFG_NO_FLASH		1	/* Flash is not usable now */
+  #define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+  #define CFG_ENV_SIZE		0x2000
 #endif
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
-#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
+#if defined(CFG_RAMBOOT)
   #if defined(CONFIG_PCI)
     #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL	\
 				 | CFG_CMD_PING		\
@@ -462,9 +448,10 @@
 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
-/*****************************/
-/* Environment Configuration */
-/*****************************/
+
+/*
+ * Environment Configuration
+ */
 
 /* The mac addresses for all ethernet interface */
 #if defined(CONFIG_TSEC_ENET)
@@ -490,13 +477,13 @@
 
 #define CONFIG_BAUDRATE	115200
 
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
+#define	CONFIG_EXTRA_ENV_SETTINGS				        \
    "netdev=eth0\0"                                                      \
    "consoledev=ttyS0\0"                                                 \
    "ramdiskaddr=400000\0"						\
    "ramdiskfile=your.ramdisk.u-boot\0"
 
-#define CONFIG_NFSBOOTCOMMAND						\
+#define CONFIG_NFSBOOTCOMMAND	                                        \
    "setenv bootargs root=/dev/nfs rw "                                  \
       "nfsroot=$serverip:$rootpath "                                    \
       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index f681b50..3876747 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -45,17 +45,11 @@
 #define CONFIG_TSEC_ENET 		/* tsec ethernet support */
 #undef  CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
 #define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
 #define CONFIG_DDR_ECC			/* only for ECC DDR module */
-#define CONFIG_DDR_DLL                  /* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING            /* Sets the 2T timing bit */
+#define CONFIG_DDR_DLL			/* possible DLL fix needed */
+#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
 
-/*
- * Use Localbus SDRAM to emulate flash before we can program the flash.
- * Normally you need a flash-boot image(u-boot.bin).
- * If unsure #undef this.
- */
-#undef CONFIG_RAM_AS_FLASH
 
 /*
  * sysclk for MPC85xx
@@ -65,24 +59,17 @@
  *    66000000
  *
  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
- * is likely the desired value here.  The board, however, can run and
- * defaults to 66Mhz.  In any event, this value must match the settings
- * of SW15[1] and SW17[8], and likely SW6[0:1], the SYSCLK as well.
- *
- *	SW17[8] ------+    SW6
- *	SW15[1] ----+ |   [0:1]
- *		    V V    V V
- *	33MHz	    1 1    1 0
- *	66MHz	    0 0    0 1
+ * is likely the desired value here, so that is now the default.
+ * The board, however, can run at 66MHz.  In any event, this value
+ * must match the settings of some switches.  Details can be found
+ * in the README.mpc85xxads.
  */
 
-#define CONFIG_SYS_CLK_FREQ	66000000
-
-
-#if !defined(CONFIG_SPD_EEPROM)
-#define CONFIG_DDR_SETTING	/* manually set up DDR parameters */
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ	33000000
 #endif
 
+
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
@@ -94,7 +81,7 @@
 
 #define CFG_INIT_DBCR DBCR_IDM		/* Enable Debug Exceptions */
 
-#undef  CFG_DRAM_TEST                  /* memory test, takes time */
+#undef	CFG_DRAM_TEST			/* memory test, takes time */
 #define CFG_MEMTEST_START	0x00200000	/* memtest region */
 #define CFG_MEMTEST_END		0x00400000
 
@@ -104,30 +91,45 @@
  * actual resources get mapped (not physical addresses)
  */
 #define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
-#define CFG_CCSRBAR             0xe0000000      /* relocated CCSRBAR */
+#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
+
+/*
+ * DDR Setup
+ */
 #define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
 #define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
-#define CFG_SDRAM_SIZE		128		/* DDR is 128MB	*/
+
+#if defined(CONFIG_SPD_EEPROM)
+    /*
+     * Determine DDR configuration from I2C interface.
+     */
+    #define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+
+#else
+    /*
+     * Manually set up DDR parameters
+     */
+    #define CFG_SDRAM_SIZE	128		/* DDR is 128MB */
+    #define CFG_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
+    #define CFG_DDR_CS0_CONFIG	0x80000002
+    #define CFG_DDR_TIMING_1	0x37344321
+    #define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
+    #define CFG_DDR_CONTROL	0xc2000000	/* unbuffered,no DYN_PWR */
+    #define CFG_DDR_MODE	0x00000062	/* DLL,normal,seq,4/2.5 */
+    #define CFG_DDR_INTERVAL	0x05200100	/* autocharge,no open page */
+#endif
+
 
 /*
  * SDRAM on the Local Bus
  */
-#if defined(CONFIG_RAM_AS_FLASH)
-#define CFG_LBC_SDRAM_BASE	0xfc000000	/* Localbus SDRAM */
-#else
 #define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
-#endif
 #define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
 
-#if defined(CONFIG_RAM_AS_FLASH)
-#define CFG_FLASH_BASE		0xf8000000	/* start of FLASH 16M */
-#define CFG_BR0_PRELIM		0xf8001801	/* port size 32bit */
-#else /* Boot from real Flash */
 #define CFG_FLASH_BASE		0xff000000	/* start of FLASH 16M */
 #define CFG_BR0_PRELIM		0xff001801	/* port size 32bit */
-#endif
 
 #define CFG_OR0_PRELIM		0xff006ff7	/* 16MB Flash */
 #define CFG_MAX_FLASH_BANKS	1		/* number of banks */
@@ -145,20 +147,9 @@
 #undef  CFG_RAMBOOT
 #endif
 
-#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
-#if defined(CONFIG_DDR_SETTING)
-#define CFG_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
-#define CFG_DDR_CS0_CONFIG	0x80000002
-#define CFG_DDR_TIMING_1	0x37344321
-#define CFG_DDR_TIMING_2	0x00000800  /* P9-45,may need tuning */
-#define CFG_DDR_CONTROL		0xc2000000  /* unbuffered,no DYN_PWR */
-#define CFG_DDR_MODE		0x00000062  /* DLL,normal,seq,4/2.5 */
-#define CFG_DDR_INTERVAL	0x05200100  /* autocharge,no open page */
-#endif
-
 
 /*
  * Local Bus Definitions
@@ -247,28 +238,27 @@
  * SDRAM Controller configuration sequence.
  */
 #define CFG_LBC_LSDMR_1		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_PCHALL)  /*0x2861b723*/
+				| CFG_LBC_LSDMR_OP_PCHALL)
 #define CFG_LBC_LSDMR_2		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_ARFRSH)  /*0x0861b723*/
+				| CFG_LBC_LSDMR_OP_ARFRSH)
 #define CFG_LBC_LSDMR_3		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_ARFRSH)  /*0x0861b723*/
+				| CFG_LBC_LSDMR_OP_ARFRSH)
 #define CFG_LBC_LSDMR_4		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_MRW)     /*0x1861b723*/
+				| CFG_LBC_LSDMR_OP_MRW)
 #define CFG_LBC_LSDMR_5		( CFG_LBC_LSDMR_COMMON \
-				| CFG_LBC_LSDMR_OP_NORMAL)  /*0x4061b723*/
+				| CFG_LBC_LSDMR_OP_NORMAL)
 
 
-#if defined(CONFIG_RAM_AS_FLASH)
-#define CFG_BR4_PRELIM          0xf8000801      /* 32KB, 8-bit wide for ADS config reg */
-#else
-#define CFG_BR4_PRELIM          0xf8000801      /* 32KB, 8-bit wide for ADS config reg */
-#endif
+/*
+ * 32KB, 8-bit wide for ADS config reg
+ */
+#define CFG_BR4_PRELIM          0xf8000801
 #define CFG_OR4_PRELIM		0xffffe1f1
 #define CFG_BCSR		(CFG_BR4_PRELIM & 0xffff8000)
 
 #define CONFIG_L1_INIT_RAM
 #define CFG_INIT_RAM_LOCK 	1
-#define CFG_INIT_RAM_ADDR	0x40000000	/* Initial RAM address */
+#define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
 #define CFG_INIT_RAM_END    	0x4000	    	/* End of used area in RAM */
 
 #define CFG_GBL_DATA_SIZE  	128		/* num bytes initial data */
@@ -295,11 +285,11 @@
 #endif
 
 /* I2C */
-#define  CONFIG_HARD_I2C    		/* I2C with hardware support*/
+#define  CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES        {0x69}  /* Don't probe these addrs */
+#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
 
 /* RapidIO MMU */
 #define CFG_RIO_MEM_BASE	0xc0000000	/* base address */
@@ -320,7 +310,7 @@
 #if defined(CONFIG_PCI)
 
 #define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP		       	/* do pci plug-and-play */
+#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
 
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP
@@ -402,34 +392,28 @@
  * Environment
  */
 #ifndef CFG_RAMBOOT
-  #if defined(CONFIG_RAM_AS_FLASH)
-  #define CFG_ENV_IS_NOWHERE
-  #define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x100000)
-  #define CFG_ENV_SIZE		0x2000
-  #else
   #define CFG_ENV_IS_IN_FLASH	1
   #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
   #define CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
-  #endif
   #define CFG_ENV_SIZE		0x2000
 #else
-#define CFG_NO_FLASH		1	/* Flash is not usable now */
-#define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
-#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
-#define CFG_ENV_SIZE		0x2000
+  #define CFG_NO_FLASH		1	/* Flash is not usable now */
+  #define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+  #define CFG_ENV_SIZE		0x2000
 #endif
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
-#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
+#if defined(CFG_RAMBOOT)
   #if defined(CONFIG_PCI)
     #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL	\
-				 | CFG_CMD_PCI		\
 				 | CFG_CMD_PING		\
+				 | CFG_CMD_PCI		\
 				 | CFG_CMD_I2C)		\
 				&			\
-				 ~(CFG_CMD_ENV \
+				 ~(CFG_CMD_ENV		\
 				  | CFG_CMD_LOADS))
   #elif defined(CONFIG_TSEC_ENET)
     #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL	\
@@ -510,6 +494,11 @@
 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
+
+/*
+ * Environment Configuration
+ */
+
 /* The mac addresses for all ethernet interface */
 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 #define CONFIG_ETHADDR   00:E0:0C:00:00:FD
@@ -529,18 +518,18 @@
 
 #define CONFIG_LOADADDR  200000	/* default location for tftp and bootm */
 
-#define CONFIG_BOOTDELAY  10	/* -1 disables auto-boot */
+#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 #define CONFIG_BAUDRATE	115200
 
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
+#define	CONFIG_EXTRA_ENV_SETTINGS				        \
    "netdev=eth0\0"                                                      \
    "consoledev=ttyS0\0"                                                 \
    "ramdiskaddr=400000\0"						\
    "ramdiskfile=your.ramdisk.u-boot\0"
 
-#define CONFIG_NFSBOOTCOMMAND						\
+#define CONFIG_NFSBOOTCOMMAND	                                        \
    "setenv bootargs root=/dev/nfs rw "                                  \
       "nfsroot=$serverip:$rootpath "                                    \
       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h
index 8460944..f5b4836 100644
--- a/include/configs/stxgp3.h
+++ b/include/configs/stxgp3.h
@@ -39,7 +39,6 @@
 #define CONFIG_BOOKE		1	/* BOOKE		*/
 #define CONFIG_E500		1	/* BOOKE e500 family	*/
 #define CONFIG_MPC85xx		1	/* MPC8540/MPC8560	*/
-#define CONFIG_MPC85xx_REV1	1	/* MPC85xx Rev 1.0 chip */
 #define CONFIG_MPC8560		1	/* MPC8560 specific	*/
 #define CONFIG_STXGP3		1	/* Silicon Tx GPPP board specific*/
 
@@ -49,15 +48,12 @@
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
 #undef  CONFIG_DDR_ECC			/* only for ECC DDR module */
-
-#if defined(CONFIG_MPC85xx_REV1)
 #define CONFIG_DDR_DLL                  /* possible DLL fix needed */
-#endif
+#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
+
 
-/* Using Localbus SDRAM to emulate flash before we can program the flash,
- * normally you need a flash-boot image(u-boot.bin), if so undef this.
+/* sysclk for MPC85xx
  */
-#undef CONFIG_RAM_AS_FLASH
 
 #define CONFIG_SYS_CLK_FREQ     33333333 /* most pci cards are 33Mhz */
 
@@ -65,55 +61,29 @@
 */
 #define CONFIG_SHOW_ACTIVITY 1
 
-#if !defined(CONFIG_SPD_EEPROM)		/* manually set up DDR parameters */
-#define CONFIG_DDR_SETTING
-#endif
-
-/* below can be toggled for performance analysis. otherwise use default */
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
 #define CONFIG_L2_CACHE                     /* toggle L2 cache         */
-#undef  CONFIG_BTB                          /* toggle branch predition */
-#undef  CONFIG_ADDR_STREAMING               /* toggle addr streaming   */
+#define  CONFIG_BTB                          /* toggle branch predition */
+#define  CONFIG_ADDR_STREAMING               /* toggle addr streaming   */
 
-#define CONFIG_BOARD_PRE_INIT   1           /* Call board_pre_init      */
+#define CONFIG_BOARD_EARLY_INIT_F   1        /* Call board_pre_init      */
 
 #undef  CFG_DRAM_TEST                       /* memory test, takes time  */
 #define CFG_MEMTEST_START       0x00200000  /* memtest region */
 #define CFG_MEMTEST_END         0x00400000
 
-#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
-     defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
-     defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
-#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
-#endif
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory  */
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
-
-/* GPPP supports up to 2G of DRAM.  Allocate up to 1G until we get
- * a chance to try it out.  Actual size is always read from sdram eeprom.
- */
-#define CFG_SDRAM_SIZE		1024		/* DDR is 1GB	*/
 
 /* Localbus SDRAM is an option, not all boards have it.
-*/
-#if defined(CONFIG_RAM_AS_FLASH)
-#define CFG_LBC_SDRAM_BASE      0xfc000000      /* Localbus SDRAM */
-#else
-#define CFG_LBC_SDRAM_BASE      0xf8000000      /* Localbus SDRAM */
-#endif
-#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB	*/
+ * This address, however, is used to configure a 256M local bus
+ * window that includes the Config latch below.
+ */
+#define CFG_LBC_SDRAM_BASE      0xf0000000      /* Localbus SDRAM */
+#define CFG_LBC_SDRAM_SIZE	256		/* LBC SDRAM is 64MB	*/
 
-#if defined(CONFIG_RAM_AS_FLASH)
-#define CFG_FLASH_BASE        0xf8000000      /* start of FLASH  16M  */
-#define CFG_BR0_PRELIM        0xf8001801      /* port size 32bit */
-#else /* Boot from real Flash */
 #define CFG_FLASH_BASE        0xff000000      /* start of FLASH 16M    */
 #define CFG_BR0_PRELIM        0xff001801      /* port size 32bit      */
-#endif
 
 #define CFG_OR0_PRELIM          0xff000ff7      /* 16 MB Flash           */
 #define CFG_MAX_FLASH_BANKS	1		/* number of banks	*/
@@ -123,7 +93,7 @@
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 /* The configuration latch is Chip Select 1.
- * It's an 8-bit latch in the upper 8 bits of the word.
+ * It's an 8-bit latch in the lower 8 bits of the word.
  */
 #define CFG_BR1_PRELIM		0xfc001801	/* 32-bit port */
 #define CFG_OR1_PRELIM		0xffff0ff7      /* 64K is enough */
@@ -146,17 +116,18 @@
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
 
 
-#define SPD_EEPROM_ADDRESS 	0x54     	/*  DDR DIMM */
+/*
+ * DDR Setup
+ */
 
-#if defined(CONFIG_DDR_SETTING)
-#define	CFG_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
-#define CFG_DDR_CS0_CONFIG	0x80000002
-#define CFG_DDR_TIMING_1	0x37344321
-#define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning*/
-#define CFG_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR*/
-#define CFG_DDR_MODE		0x00000062	/* DLL,normal,seq,4/2.5 */
-#define CFG_DDR_INTERVAL	0x05200100	/* autocharge,no open page*/
-#endif
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory  */
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+
+#define SPD_EEPROM_ADDRESS 	0x54     	/*  DDR DIMM */
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
@@ -213,37 +184,65 @@
 #undef CFG_I2C_NOPROBES
 #endif
 
-#define CFG_PCI_MEM_BASE	0xe0000000
-#define CFG_PCI_MEM_PHYS	0xe0000000
-#define CFG_PCI_MEM_SIZE	0x10000000
+/* RapdIO Map configuration, mapped 1:1.
+*/
+#define CFG_RIO_MEM_BASE	0xc0000000
+#define CFG_RIO_MEM_PHYS	CFG_RIO_MEM_BASE
+#define CFG_RIO_MEM_SIZE	0x200000000	/* 512 M */
+
+/* Standard 8560 PCI addressing, mapped 1:1.
+*/
+#define CFG_PCI1_MEM_BASE	0x80000000
+#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCI1_IO_BASE	0xe2000000
+#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
+#define CFG_PCI1_IO_SIZE	0x01000000	/* 16 M */
 
 #if defined(CONFIG_PCI) 		/* PCI Ethernet card */
+
 #define CONFIG_NET_MULTI
-#define CONFIG_EEPRO100
-#undef CONFIG_TULIP
 #define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
-  #if !defined(CONFIG_PCI_PNP)
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
   #define PCI_ENET0_IOADDR    	0xe0000000
   #define PCI_ENET0_MEMADDR     0xe0000000
   #define PCI_IDSEL_NUMBER      0x0c 	/* slot0->3(IDSEL)=12->15 */
-  #endif
-#define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
-#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
-#if defined(CONFIG_MPC85xx_REV1) 	/* Errata PCI 7 */
-  #define CFG_PCI_SUBSYS_DEVICEID 0x0003
-#else
-  #define CFG_PCI_SUBSYS_DEVICEID 0x0009
 #endif
-#elif defined(CONFIG_TSEC_ENET) 	/* TSEC Ethernet port */
+
+#undef CONFIG_PCI_SCAN_SHOW
+#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
 #define CONFIG_NET_MULTI 	1
-#define CONFIG_PHY_M88E1011      1       /* GigaBit Ether PHY        */
+#endif
+
 #define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		8	/* PHY address			*/
+
+#define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC2	1
+#undef CONFIG_MPS85XX_FEC
+
+#define TSEC1_PHY_ADDR		2
+#define TSEC2_PHY_ADDR		4
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define CONFIG_ETHPRIME		"MOTO ENET0"
+
 #elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */
+
 #define CONFIG_ETHER_ON_FCC2             /* define if ether on FCC   */
 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 #define CONFIG_ETHER_INDEX      2       /* which channel for ether  */
-  #if (CONFIG_ETHER_INDEX == 2)
+
+#if (CONFIG_ETHER_INDEX == 2)
   /*
    * - Rx-CLK is CLK13
    * - Tx-CLK is CLK14
@@ -259,59 +258,41 @@
   #define CFG_FCC_PSMR          0
 #endif
   #define FETH2_RST		0x01
-  #elif (CONFIG_ETHER_INDEX == 3)
+#elif (CONFIG_ETHER_INDEX == 3)
   /* need more definitions here for FE3 */
   #define FETH3_RST		0x80
-  #endif  				/* CONFIG_ETHER_INDEX */
+#endif  				/* CONFIG_ETHER_INDEX */
+
+/* MDIO is done through the TSEC0 control.
+*/
 #define CONFIG_MII			/* MII PHY management */
 #undef CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
-/*
- * GPIO pins used for bit-banged MII communications
- */
-#define MDIO_PORT	2		/* Port C */
-#define MDIO_ACTIVE	(iop->pdir |=  0x00400000)
-#define MDIO_TRISTATE	(iop->pdir &= ~0x00400000)
-#define MDIO_READ	((iop->pdat &  0x00400000) != 0)
-
-#define MDIO(bit)	if(bit) iop->pdat |=  0x00400000; \
-			else	iop->pdat &= ~0x00400000
 
-#define MDC(bit)	if(bit) iop->pdat |=  0x00200000; \
-			else	iop->pdat &= ~0x00200000
-
-#define MIIDELAY	udelay(1)
 #endif
 
 /* Environment */
 /* We use the top boot sector flash, so we have some 16K sectors for env
- * But....functions don't seem smart enough yet.
  */
 #ifndef CFG_RAMBOOT
-  #if defined(CONFIG_RAM_AS_FLASH)
-  #define CFG_ENV_IS_NOWHERE
-  #define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x100000)
-  #define CFG_ENV_SIZE		0x2000
-  #else
   #define CFG_ENV_IS_IN_FLASH	1
   #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x60000)
   #define CFG_ENV_SECT_SIZE	0x4000	/* 16K (one top sector) for env */
-  #endif
   #define CFG_ENV_SIZE		0x2000
 #else
-#define CFG_NO_FLASH		1	/* Flash is not usable now	*/
-#define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only	*/
-#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
-#define CFG_ENV_SIZE		0x2000
+  #define CFG_NO_FLASH		1	/* Flash is not usable now	*/
+  #define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only	*/
+  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+  #define CFG_ENV_SIZE		0x2000
 #endif
 
 #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,38400"
-#define CONFIG_BOOTCOMMAND	"bootm 0xff800000 0xff900000"
+#define CONFIG_BOOTCOMMAND	"bootm 0xff000000 0xff100000"
 #define CONFIG_BOOTDELAY	3	/* -1 disable autoboot */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
-#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
+#if defined(CFG_RAMBOOT)
   #if defined(CONFIG_PCI)
   #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL | CFG_CMD_PCI | \
 				CFG_CMD_PING | CFG_CMD_I2C) & \
@@ -329,13 +310,13 @@
 #else
   #if defined(CONFIG_PCI)
   #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_PCI | \
-				CFG_CMD_PING | CFG_CMD_I2C)
+				CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C)
   #elif defined(CONFIG_TSEC_ENET)
   #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_PING | \
-				CFG_CMD_MII | CFG_CMD_I2C)
+				CFG_CMD_ELF | CFG_CMD_MII | CFG_CMD_I2C)
   #elif defined(CONFIG_ETHER_ON_FCC)
   #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_MII | \
-				CFG_CMD_PING | CFG_CMD_I2C)
+				CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C)
   #endif
 #endif
 #include <cmd_confdefs.h>
@@ -387,9 +368,9 @@
 
 /*Note: change below for your network setting!!! */
 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
-#define CONFIG_ETHADDR  00:01:af:07:9b:8a
-#define CONFIG_ETH1ADDR  00:01:af:07:9b:8b
-#define CONFIG_ETH2ADDR  00:01:af:07:9b:8c
+#define CONFIG_ETHADDR  00:e0:0c:07:9b:8a
+#define CONFIG_ETH1ADDR  00:e0:0c:07:9b:8b
+#define CONFIG_ETH2ADDR  00:e0:0c:07:9b:8c
 #endif
 
 #define CONFIG_SERVERIP 	192.168.85.1
@@ -399,5 +380,6 @@
 #define CONFIG_HOSTNAME 	STX_GP3
 #define CONFIG_ROOTPATH 	/gppproot
 #define CONFIG_BOOTFILE 	uImage
+#define CONFIG_LOADADDR		0x1000000
 
 #endif	/* __CONFIG_H */
diff --git a/include/e500.h b/include/e500.h
index 5489ba2..8e3bf8c 100644
--- a/include/e500.h
+++ b/include/e500.h
@@ -20,14 +20,29 @@ typedef struct
  * initial memory mapping like legacy BAT registers do. Usually we
  * use four MAS registers(MAS0-3) to operate on TLB1 entries.
  *
+ * While there are 16 Entries with variable Page Sizes in TLB1,
+ * there are also 256 Entries with fixed 4K pages in TLB0.
+ *
  * We also need LAWs(Local Access Window) to associate a range of
  * the local 32-bit address space with a particular target interface
  * such as PCI/PCI-X, RapidIO, Local Bus and DDR SDRAM.
  *
  * We put TLB1/LAW code here because memory mapping is board-specific
  * instead of cpu-specific.
+ *
+ * While these macros are all nominally for TLB1 by name, they can
+ * also be used for TLB0 as well.
  */
 
+
+/*
+ * Convert addresses to Effective and Real Page Numbers.
+ * Grab the high 20-bits and shift 'em down, dropping the "byte offset".
+ */
+#define E500_TLB_EPN(addr)	(((addr) >> 12) & 0xfffff)
+#define E500_TLB_RPN(addr)	(((addr) >> 12) & 0xfffff)
+
+
 /* MAS0
  * tlbsel(TLB Select):0,1
  * esel(Entry Select): 0,1,2,...,15 for TLB1