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authorRafal Jaworowski <raj@semihalf.com>2006-08-10 12:43:17 +0200
committerRafal Jaworowski <raj@pollux.denx.de>2006-08-10 12:43:17 +0200
commit692519b1edfd5803cd2a841921492889f46f0ce3 (patch)
tree1a761268c5b203444769a19257a317d09ce396c4 /include
parentedd6cf20e1be63f84e0f5af0280473cf31f0e86c (diff)
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Add support for PCI-Express on PPC440SPe (Yucca board).
Diffstat (limited to 'include')
-rw-r--r--include/common.h4
-rw-r--r--include/configs/yucca.h32
2 files changed, 25 insertions, 11 deletions
diff --git a/include/common.h b/include/common.h
index 6d7c41a..5f00f91 100644
--- a/include/common.h
+++ b/include/common.h
@@ -244,6 +244,9 @@ void pciinfo (int, int);
void pci_master_init (struct pci_controller *);
# endif
int is_pci_host (struct pci_controller *);
+#if defined(CONFIG_440SPE)
+ void pcie_setup_hoses(void);
+#endif
#endif
int misc_init_f (void);
@@ -461,6 +464,7 @@ void get_sys_info ( sys_info_t * );
# if defined(CONFIG_440SPE)
unsigned long determine_sysper(void);
unsigned long determine_pci_clock_per(void);
+ int ppc440spe_revB(void);
# endif
# else
typedef PPC405_SYS_INFO sys_info_t;
diff --git a/include/configs/yucca.h b/include/configs/yucca.h
index 0e58e7e..9dd9e5e 100644
--- a/include/configs/yucca.h
+++ b/include/configs/yucca.h
@@ -63,17 +63,26 @@
#define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */
#define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */
-#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
-#define CFG_PCI_MEMBASE1 0x90000000 /* mapped pci memory */
-#define CFG_PCI_MEMBASE2 0xa0000000 /* mapped pci memory */
-#define CFG_PCI_MEMBASE3 0xb0000000 /* mapped pci memory */
-
+#define CFG_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
-#define CFG_PCI_TARGBASE 0x80000000 /*PCIaddr mapped to CFG_PCI_MEMBASE*/
+#define CFG_PCI_TARGBASE CFG_PCI_MEMBASE
+
+#define CFG_PCIE_MEMBASE 0xB0000000 /* mapped PCIe memory */
+#define CFG_PCIE_MEMSIZE 0x01000000
-/* #define CFG_PCI_BASE_IO 0xB8000000 */ /* internal PCI I-O */
-/* #define CFG_PCI_BASE_REGS 0xBEC00000 */ /* internal PCI regs */
-/* #define CFG_PCI_BASE_CYCLE 0xBED00000 */ /* internal PCI regs */
+#define CFG_PCIE0_CFGBASE 0xc0000000
+#define CFG_PCIE0_XCFGBASE 0xc0000400
+#define CFG_PCIE1_CFGBASE 0xc0001000
+#define CFG_PCIE1_XCFGBASE 0xc0001400
+#define CFG_PCIE2_CFGBASE 0xc0002000
+#define CFG_PCIE2_XCFGBASE 0xc0002400
+
+#define CFG_PCIE0_REGBASE 0xc0003000
+#define CFG_PCIE1_REGBASE 0xc0003400
+#define CFG_PCIE2_REGBASE 0xc0004000
+#define CFG_PCIE3_REGBASE 0xc0004400
+#define CFG_PCIE4_REGBASE 0xc0005000
+#define CFG_PCIE5_REGBASE 0xc0005400
/* System RAM mapped to PCI space */
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
@@ -292,6 +301,7 @@
*/
/* Support for Intel 82557/82559/82559ER chips. */
#define CONFIG_EEPRO100
+
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
@@ -506,8 +516,8 @@
#define FPGA_REG1C_PE1_WAKE 0x0040
#define FPGA_REG1C_PE2_WAKE 0x0020
#define FPGA_REG1C_PE0_PERST 0x0010
-#define FPGA_REG1C_PE1_PERST 0x0080
-#define FPGA_REG1C_PE2_PERST 0x0040
+#define FPGA_REG1C_PE1_PERST 0x0008
+#define FPGA_REG1C_PE2_PERST 0x0004
/*----------------------------------------------------------------------------+
| Defines