Merge branch 'master' of git://www.denx.de/git/u-boot-blackfin

5 files changed, 56 insertions, 251 deletions

diff --git a/include/asm-blackfin/blackfin-config-post.h b/include/asm-blackfin/blackfin-config-post.h
index 4422225..6a1ffa1 100644
--- a/include/asm-blackfin/blackfin-config-post.h
+++ b/include/asm-blackfin/blackfin-config-post.h
@@ -14,9 +14,9 @@
 # error Memory Map does not fit into configuration
 #endif
 
-/* Sanity check BFIN_CPU */
-#ifndef BFIN_CPU
-# error BFIN_CPU: your board config needs to define this
+/* Sanity check CONFIG_BFIN_CPU */
+#ifndef CONFIG_BFIN_CPU
+# error CONFIG_BFIN_CPU: your board config needs to define this
 #endif
 
 /* Make sure the structure is properly aligned */
diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h
index f2c8703..2f551ad 100644
--- a/include/configs/bf533-ezkit.h
+++ b/include/configs/bf533-ezkit.h
@@ -8,7 +8,6 @@
 #include <asm/blackfin-config-pre.h>
 
 #define CONFIG_BAUDRATE		57600
-#define CONFIG_STAMP		1
 
 #define CONFIG_BOOTDELAY	5
 #define CFG_AUTOLOAD		"no"	/*rarpb, bootp or dhcp commands will perform only a */
@@ -30,28 +29,15 @@
 #define CONFIG_RTC_BFIN		1
 #define CONFIG_BOOT_RETRY_TIME	-1	/* Enable this if bootretry required, currently its disabled */
 
-/*
- * Boot Mode Set
- * Blackfin can support several boot modes
- */
-#define BF533_BYPASS_BOOT	0x0001	/* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */
-#define BF533_PARA_BOOT		0x0002	/* Bootmode 1: Boot from 8-bit or 16-bit flash */
-#define BF533_SPI_BOOT		0x0004	/* Bootmode 3: Boot from SPI flash */
-/* Define the boot mode */
-#define BFIN_BOOT_MODE		BF533_BYPASS_BOOT
-/* #define BFIN_BOOT_MODE	BF533_SPI_BOOT */
-
 #define CONFIG_PANIC_HANG 1
 
 #define CONFIG_BFIN_CPU	bf533-0.3
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
 
 /* This sets the default state of the cache on U-Boot's boot */
 #define CONFIG_ICACHE_ON
 #define CONFIG_DCACHE_ON
 
-/* Define where the uboot will be loaded by on-chip boot rom */
-#define APP_ENTRY 0x00001000
-
 /* CONFIG_CLKIN_HZ is any value in Hz				*/
 #define CONFIG_CLKIN_HZ		27000000
 /* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN	*/
@@ -216,24 +202,14 @@
 
 #define CFG_BOOTM_LEN		0x4000000	/* Large Image Length, set to 64 Meg */
 
-/* 0xFF, 0x7BB07BB0, 0x22547BB0 */
-/* #define AMGCTLVAL		(AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
-#define AMBCTL0VAL		(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \
-				~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN)
-#define AMBCTL1VAL		(B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \
-				B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN)
-*/
-#define AMGCTLVAL		0xFF
-#define AMBCTL0VAL		0x7BB07BB0
-#define AMBCTL1VAL		0xFFC27BB0
-
-#define CONFIG_VDSP		1
-
-#ifdef CONFIG_VDSP
-#define ET_EXEC_VDSP		0x8
-#define SHT_STRTAB_VDSP		0x1
-#define ELFSHDRSIZE_VDSP	0x2C
-#define VDSP_ENTRY_ADDR		0xFFA00000
-#endif
+#define CONFIG_EBIU_SDRRC_VAL  0x398
+#define CONFIG_EBIU_SDGCTL_VAL 0x91118d
+#define CONFIG_EBIU_SDBCTL_VAL 0x13
+
+#define CONFIG_EBIU_AMGCTL_VAL		0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL		0x7BB07BB0
+#define CONFIG_EBIU_AMBCTL1_VAL		0xFFC27BB0
+
+#include <asm/blackfin-config-post.h>
 
 #endif
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h
index 76dd2fa..66a0af6 100644
--- a/include/configs/bf533-stamp.h
+++ b/include/configs/bf533-stamp.h
@@ -7,37 +7,17 @@
 
 #include <asm/blackfin-config-pre.h>
 
-#define CONFIG_STAMP			1
 #define CONFIG_RTC_BFIN			1
-#define CONFIG_BF533			1
-/*
- * Boot Mode Set
- * Blackfin can support several boot modes
- */
-#define BF533_BYPASS_BOOT	0x0001	/* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */
-#define BF533_PARA_BOOT		0x0002	/* Bootmode 1: Boot from 8-bit or 16-bit flash */
-#define BF533_SPI_BOOT		0x0004	/* Bootmode 3: Boot from SPI flash */
-/* Define the boot mode */
-#define BFIN_BOOT_MODE		BF533_BYPASS_BOOT
-/* #define BFIN_BOOT_MODE	BF533_SPI_BOOT */
 
 #define CONFIG_PANIC_HANG 1
 
 #define CONFIG_BFIN_CPU	bf533-0.3
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
 
 /* This sets the default state of the cache on U-Boot's boot */
 #define CONFIG_ICACHE_ON
 #define CONFIG_DCACHE_ON
 
-/* Define where the uboot will be loaded by on-chip boot rom */
-#define APP_ENTRY 0x00001000
-
-/*
- * Stringize definitions - needed for environmental settings
- */
-#define STRINGIZE2(x) #x
-#define STRINGIZE(x) STRINGIZE2(x)
-
 /*
  * Board settings
  */
@@ -61,8 +41,6 @@
  */
 #define  CONFIG_VIDEO		0
 
-#define CONFIG_VDSP		1
-
 /*
  * Clock settings
  */
@@ -88,10 +66,7 @@
 /* Values can range from 2-65535				*/
 /* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD)			*/
 #define CONFIG_SPI_BAUD		2
-
-#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
 #define CONFIG_SPI_BAUD_INITBLOCK	4
-#endif
 
 /*
  * Network settings
@@ -126,14 +101,14 @@
 #define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
 #define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip */
 
-#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		0x20004000
-#define	CFG_ENV_OFFSET		(CFG_ENV_ADDR - CFG_FLASH_BASE)
-#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
 #define CFG_ENV_IS_IN_EEPROM	1
 #define CFG_ENV_OFFSET		0x4000
 #define CFG_ENV_HEADER		(CFG_ENV_OFFSET + 0x12A)	/* 0x12A is the length of LDR file header */
+#else
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		0x20004000
+#define	CFG_ENV_OFFSET		(CFG_ENV_ADDR - CFG_FLASH_BASE)
 #endif
 
 #define	CFG_ENV_SIZE		0x2000
@@ -165,11 +140,7 @@
 #define CONFIG_MEM_ADD_WDTH     11	/* 8, 9, 10, 11    */
 #define CONFIG_MEM_MT48LC64M4A2FB_7E	1
 
-#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
 #define CFG_MEMTEST_START	0x00000000	/* memtest works on */
-#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#endif
 
 #define	CFG_SDRAM_BASE		0x00000000
 
@@ -207,14 +178,6 @@
 #define CONFIG_SCLK_HZ		CONFIG_CLKIN_HZ
 #endif
 
-#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
-#if (CONFIG_SCLK_HZ / (2*CONFIG_SPI_BAUD) > 20000000)
-#define CONFIG_SPI_FLASH_FAST_READ 1 /* Needed if SPI_CLK > 20 MHz */
-#else
-#undef CONFIG_SPI_FLASH_FAST_READ
-#endif
-#endif
-
 /*
  * Command settings
  */
@@ -222,26 +185,18 @@
 #define CFG_LONGHELP		1
 #define CONFIG_CMDLINE_EDITING	1
 
-#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
 #define CFG_AUTOLOAD		"no"	/*rarpb, bootp or dhcp commands will perform only a */
-#endif
 
 /* configuration lookup from the BOOTP/DHCP server, */
 /* but not try to load any image using TFTP	    */
 
 #define CONFIG_BOOTDELAY	5
 #define CONFIG_BOOT_RETRY_TIME	-1	/* Enable this if bootretry required, currently its disabled */
-#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
 #define CONFIG_BOOTCOMMAND	"run ramboot"
-#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
-#define CONFIG_BOOTCOMMAND 	"eeprom read 0x1000000 0x100000 0x180000;icache on;dcache on;bootm 0x1000000"
-#endif
 
 #define CONFIG_BOOTARGS		"root=/dev/mtdblock0 rw console=ttyBF0,57600"
 
 
-#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
-#if (CONFIG_DRIVER_SMC91111)
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
 	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
@@ -257,29 +212,6 @@
 		"protect off 0x20000000 0x2003FFFF; erase 0x20000000 0x2003FFFF;" \
 		"cp.b $(loadaddr) 0x20000000 $(filesize)\0" \
 	""
-#else
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
-	"flashboot=bootm 0x20100000\0" \
-	"
-#endif
-
-#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
-	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
-		"$(rootpath) console=ttyBF0,57600\0"	\
-	"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
-		"$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
-	"ramboot=tftpboot $(loadaddr) linux; " \
-		"run ramargs;run addip;bootelf\0" \
-	"nfsboot=tftpboot $(loadaddr) linux; "	\
-		"run nfsargs;run addip;bootelf\0" \
-	"flashboot=bootm 0x20100000\0" \
-	"update=tftpboot $(loadaddr) u-boot.ldr;"	\
-		"eeprom write $(loadaddr) 0x0 $(filesize);\0"\
-	""
-#endif
 
 #ifdef CONFIG_SOFT_I2C
 #if (!CONFIG_SOFT_I2C)
@@ -316,9 +248,7 @@
 #define CONFIG_CMD_I2C
 #endif
 
-#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
 #define CONFIG_CMD_DHCP
-#endif
 
 
 /*
@@ -428,25 +358,16 @@
 /*
  * FLASH organization and environment definitions
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)/* Initial Memory map for Linux */
-
-/* 0xFF, 0xBBC3BBc3, 0x99B39983 */
-/*#define AMGCTLVAL		(AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
-#define AMBCTL0VAL		(B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL | \
-				B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN)
-#define AMBCTL1VAL   		(B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL | \
-				B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN)
-*/
-#define AMGCTLVAL		0xFF
-#define AMBCTL0VAL		0xBBC3BBC3
-#define AMBCTL1VAL		0x99B39983
-#define CF_AMBCTL1VAL		0x99B3ffc2
-
-#ifdef CONFIG_VDSP
-#define ET_EXEC_VDSP		0x8
-#define SHT_STRTAB_VDSP		0x1
-#define ELFSHDRSIZE_VDSP	0x2C
-#define VDSP_ENTRY_ADDR		0xFFA00000
-#endif
+
+#define CONFIG_EBIU_SDRRC_VAL  0x268
+#define CONFIG_EBIU_SDGCTL_VAL 0x911109
+#define CONFIG_EBIU_SDBCTL_VAL 0x37
+
+#define CONFIG_EBIU_AMGCTL_VAL		0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL		0xBBC3BBC3
+#define CONFIG_EBIU_AMBCTL1_VAL		0x99B39983
+#define CF_CONFIG_EBIU_AMBCTL1_VAL		0x99B3ffc2
+
+#include <asm/blackfin-config-post.h>
 
 #endif
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index 0e189d4..39c7359 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@ -12,28 +12,15 @@
 #define CONFIG_BAUDRATE		57600
 /* Set default serial console for bf537 */
 #define CONFIG_UART_CONSOLE	0
-#define CONFIG_BF537		1
 #define CONFIG_BOOTDELAY	5
 /* define CONFIG_BF537_STAMP_LEDCMD to enable LED command*/
 /*#define CONFIG_BF537_STAMP_LEDCMD	1*/
 
-/*
- * Boot Mode Set
- * Blackfin can support several boot modes
- */
-#define BF537_BYPASS_BOOT	0x0011	/* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM)  */
-#define BF537_PARA_BOOT		0x0012	/* Bootmode 1: Boot from 8-bit or 16-bit flash                          */
-#define BF537_SPI_MASTER_BOOT	0x0014	/* Bootmode 3: SPI master mode boot from SPI flash                      */
-#define BF537_SPI_SLAVE_BOOT	0x0015	/* Bootmode 4: SPI slave mode boot from SPI flash                       */
-#define BF537_TWI_MASTER_BOOT	0x0016	/* Bootmode 5: TWI master mode boot from EEPROM                         */
-#define BF537_TWI_SLAVE_BOOT	0x0017	/* Bootmode 6: TWI slave mode boot from EEPROM                          */
-#define BF537_UART_BOOT		0x0018	/* Bootmode 7: UART slave mdoe boot via UART host                       */
-/* Define the boot mode */
-#define BFIN_BOOT_MODE		BF537_BYPASS_BOOT
-
 #define CONFIG_PANIC_HANG 1
 
 #define CONFIG_BFIN_CPU	bf537-0.2
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
+
 #define CONFIG_BFIN_MAC
 
 /* This sets the default state of the cache on U-Boot's boot */
@@ -43,9 +30,6 @@
 /* Define if want to do post memory test */
 #undef CONFIG_POST_TEST
 
-/* Define where the uboot will be loaded by on-chip boot rom */
-#define APP_ENTRY 0x00001000
-
 #define CONFIG_RTC_BFIN		1
 #define CONFIG_BOOT_RETRY_TIME	-1	/* Enable this if bootretry required, currently its disabled */
 
@@ -70,9 +54,7 @@
 /* Values can range from 2-65535				*/
 /* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD)			*/
 #define CONFIG_SPI_BAUD			2
-#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
 #define CONFIG_SPI_BAUD_INITBLOCK	4
-#endif
 
 #if ( CONFIG_CLKIN_HALF == 0 )
 #define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
@@ -88,14 +70,6 @@
 #define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
 #endif
 
-#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
-#if (CONFIG_SCLK_HZ / (2*CONFIG_SPI_BAUD) > 20000000)
-#define CONFIG_SPI_FLASH_FAST_READ 1	/* Needed if SPI_CLK > 20 MHz */
-#else
-#undef CONFIG_SPI_FLASH_FAST_READ
-#endif
-#endif
-
 #define CONFIG_MEM_SIZE			64	/* 128, 64, 32, 16 */
 #define CONFIG_MEM_ADD_WDTH		10	/* 8, 9, 10, 11 */
 #define CONFIG_MEM_MT48LC32M8A2_75	1
@@ -131,7 +105,7 @@
 #define CONFIG_BOOT_RETRY_TIME	-1	/* Enable this if bootretry required, currently its disabled */
 #define CONFIG_BOOTCOMMAND 	"run ramboot"
 
-#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) && defined(CONFIG_POST_TEST)
+#if defined(CONFIG_POST_TEST)
 /* POST support */
 #define CONFIG_POST 		( CFG_POST_MEMORY | \
 				  CFG_POST_UART	  | \
@@ -177,8 +151,6 @@
  */
 #include <config_cmd_default.h>
 
-#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) || (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
-
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_CACHE
@@ -198,10 +170,6 @@
 #define CONFIG_CMD_IDE
 #endif
 
-#endif
-
-#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
-
 #define CONFIG_CMD_DHCP
 
 #if defined(CONFIG_POST)
@@ -212,14 +180,10 @@
 #define CONFIG_CMD_NAND
 #endif
 
-#endif
-
 
 #define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
 #define CONFIG_LOADADDR	0x1000000
 
-#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
-#ifdef CONFIG_BFIN_MAC
 #define CONFIG_EXTRA_ENV_SETTINGS				\
 	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0"	\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "		\
@@ -236,36 +200,6 @@
 	"protect off 0x20000000 0x2007FFFF;"			\
 	"erase 0x20000000 0x2007FFFF;cp.b 0x1000000 0x20000000 $(filesize)\0"	\
 	""
-#else
-#define CONFIG_EXTRA_ENV_SETTINGS				\
-	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0"	\
-	"flashboot=bootm 0x20100000\0"				\
-	""
-#endif
-#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
-#ifdef CONFIG_BFIN_MAC
-#define CONFIG_EXTRA_ENV_SETTINGS				\
-	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0"	\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "		\
-	"nfsroot=$(serverip):$(rootpath) console=ttyBF0,57600\0"\
-	"addip=setenv bootargs $(bootargs) "			\
-	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
-	":$(hostname):eth0:off\0"				\
-	"ramboot=tftpboot $(loadaddr) linux;"			\
-	"run ramargs;run addip;bootelf\0"			\
-	"nfsboot=tftpboot $(loadaddr) linux;"			\
-	"run nfsargs;run addip;bootelf\0"			\
-	"flashboot=bootm 0x20100000\0"				\
-	"update=tftpboot $(loadaddr) u-boot.ldr;"		\
-	"eeprom write $(loadaddr) 0x0 $(filesize);\0"		\
-	""
-#else
-#define CONFIG_EXTRA_ENV_SETTINGS				\
-	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0"	\
-	"flashboot=bootm 0x20100000\0"				\
-	""
-#endif
-#endif
 
 #define	CFG_PROMPT		"bfin> "	/* Monitor Command Prompt */
 
@@ -300,21 +234,18 @@
 #define CFG_GBL_DATA_ADDR	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
 #define CONFIG_STACKBASE	(CFG_GBL_DATA_ADDR  - 4)
 
-#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) || (BFIN_BOOT_MODE == BF537_UART_BOOT)
-/* for bf537-stamp, usrt boot mode still store env in flash */
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		0x20004000
-#define CFG_ENV_OFFSET		(CFG_ENV_ADDR - CFG_FLASH_BASE)
-#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
 #define CFG_ENV_IS_IN_EEPROM	1
 #define CFG_ENV_OFFSET		0x4000
 #define CFG_ENV_HEADER		(CFG_ENV_OFFSET + 0x16e) /* 0x12A is the length of LDR file header */
+#else
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		0x20004000
+#define CFG_ENV_OFFSET		(CFG_ENV_ADDR - CFG_FLASH_BASE)
 #endif
 #define CFG_ENV_SIZE		0x2000
 #define	CFG_ENV_SECT_SIZE	0x2000	/* Total Size of Environment Sector */
-/* #if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) */
 #define ENV_IS_EMBEDDED
-/* #endif */
 
 /* JFFS Partition offset set  */
 #define CFG_JFFS2_FIRST_BANK	0
@@ -383,6 +314,14 @@
 #define CONFIG_TWICLK_KHZ	50
 #endif
 
+#define CONFIG_EBIU_SDRRC_VAL  0x306
+#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
+#define CONFIG_EBIU_SDBCTL_VAL 0x25
+
+#define CONFIG_EBIU_AMGCTL_VAL		0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL		0x7BB07BB0
+#define CONFIG_EBIU_AMBCTL1_VAL		0xFFC27BB0
+
 #if defined CONFIG_SOFT_I2C
 /*
  * Software (bit-bang) I2C driver configuration
@@ -428,15 +367,6 @@
 #define AMBCTL0VAL		0x7BB07BB0
 #define AMBCTL1VAL		0xFFC27BB0
 
-#define CONFIG_VDSP		1
-
-#ifdef CONFIG_VDSP
-#define ET_EXEC_VDSP		0x8
-#define SHT_STRTAB_VDSP		0x1
-#define ELFSHDRSIZE_VDSP	0x2C
-#define VDSP_ENTRY_ADDR		0xFFA00000
-#endif
-
 #if defined(CONFIG_BFIN_IDE)
 
 #define CONFIG_DOS_PARTITION	1
@@ -492,4 +422,6 @@
 
 #endif				/*CONFIG_BFIN_IDE */
 
+#include <asm/blackfin-config-post.h>
+
 #endif
diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h
index c29555a..641548d 100644
--- a/include/configs/bf561-ezkit.h
+++ b/include/configs/bf561-ezkit.h
@@ -7,9 +7,6 @@
 
 #include <asm/blackfin-config-pre.h>
 
-#define CONFIG_VDSP		1
-#define CONFIG_BF561		1
-
 #define CFG_LONGHELP		1
 #define CONFIG_CMDLINE_EDITING	1
 #define CONFIG_BAUDRATE		57600
@@ -21,30 +18,12 @@
 #define CONFIG_PANIC_HANG 1
 
 #define CONFIG_BFIN_CPU	bf561-0.3
-
-/*
-* Boot Mode Set
-* Blackfin can support several boot modes
-*/
-#define BF561_BYPASS_BOOT	0x21
-#define BF561_PARA_BOOT		0x22
-#define BF561_SPI_BOOT		0x24
-/* Define the boot mode */
-#define BFIN_BOOT_MODE	BF561_BYPASS_BOOT
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
 
 /* This sets the default state of the cache on U-Boot's boot */
 #define CONFIG_ICACHE_ON
 #define CONFIG_DCACHE_ON
 
-/* Define where the uboot will be loaded by on-chip boot rom */
-#define APP_ENTRY 0x00001000
-
-/*
- * Stringize definitions - needed for environmental settings
- */
-#define STRINGIZE2(x) #x
-#define STRINGIZE(x) STRINGIZE2(x)
-
 /*
  * Board settings
  */
@@ -242,17 +221,14 @@
 /*
  * FLASH organization and environment definitions
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_EBIU_SDRRC_VAL  0x306
+#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
+#define CONFIG_EBIU_SDBCTL_VAL 0x15
 
-#define AMGCTLVAL		0x3F
-#define AMBCTL0VAL		0x7BB07BB0
-#define AMBCTL1VAL		0xFFC27BB0
+#define CONFIG_EBIU_AMGCTL_VAL		0x3F
+#define CONFIG_EBIU_AMBCTL0_VAL		0x7BB07BB0
+#define CONFIG_EBIU_AMBCTL1_VAL		0xFFC27BB0
 
-#ifdef CONFIG_VDSP
-#define ET_EXEC_VDSP		0x8
-#define SHT_STRTAB_VDSP		0x1
-#define ELFSHDRSIZE_VDSP	0x2C
-#define VDSP_ENTRY_ADDR		0xFFA00000
-#endif
+#include <asm/blackfin-config-post.h>
 
 #endif				/* __CONFIG_EZKIT561_H__ */