ENGR00221135: imx6x: clear PowerDown Enable bit of WDOG1_WMCR

From IC spec:
---
The Power down Counter inside WDOG-1 will be enabled out of reset.
This counter has a fixed time-out value of 16 seconds, after which
it will drive the WDOG-1 signal low.

To prevent this, the software must disable this counter by clearing
the PDE bit of Watchdog Miscellaneous Control Register (WDOG_WMCR)
within 16 seconds of reset de-assertion. Once disabled, this counter
cannot be enabled again until the next system reset occurs. This
feature is provided to prevent the hanging up of cores after reset, as
WDOG-1 is not enabled out of reset.
---

NOTE for the last sentence:
This feature requires a dedicated WDOG_B pin for it. The fact that changing
the IOMUX configuration can alter the WDOG_B functionality (GPIO by default)
is not ideal as it defeats the purpose of this feature. But it still
takes effect when the muxed pin is configured as WDOG_B within 16 seconds.

Clear PDE bit to avoid WDOG_B (aka, WDOG-1) assertion.

Tested on MX6SL. May add this for other MX6x.

Signed-off-by: Robby Cai <R63905@freescale.com>

0 files changed, 0 insertions, 0 deletions