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| author | Priyanka Jain <Priyanka.Jain@freescale.com> | 2014-09-17 15:57:54 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-11-14 11:12:14 -0800 |
| commit | 0921de67440ac5dfc3dbf687217cdecc6335f15e (patch) | |
| tree | 89177cc55c1417f668e0b381b3328d68614e123c /include/xilinx.h | |
| parent | ab06b236f76cfa42f264ee161be190b3e479298f (diff) | |
| download | u-boot-imx-0921de67440ac5dfc3dbf687217cdecc6335f15e.zip u-boot-imx-0921de67440ac5dfc3dbf687217cdecc6335f15e.tar.gz u-boot-imx-0921de67440ac5dfc3dbf687217cdecc6335f15e.tar.bz2 | |
t104xrdb: Add Errata A_007662, A_008007 workaround in pbi.cfg
-A_007662 states that for x1 link width, PCIe2 controller trains in
Gen1 speed while configured for Gen2 speed.
Workaround:Set the width to x1 and speed to Gen2 by writing to
CCSR registers in PBI phase
-A_008007 states that PVR register may show random value.
Workaround: Reset PVR register using DCSR space in PBI phase
Add PBI based software workaround for A_007662 and A_008007
in t104x_pbi.cfg. This is required for SPL-based bootloaders
like NAND-boot, SD-boot, SPI-boot
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'include/xilinx.h')
0 files changed, 0 insertions, 0 deletions