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authorPrabhakar Kushwaha <prabhakar@freescale.com>2013-05-07 11:19:55 +0530
committerAndy Fleming <afleming@freescale.com>2013-06-20 17:08:47 -0500
commitf64bd7c038468de7b6cfa47e88dd0f5ce6c38504 (patch)
tree89bb895f51f24167e88ecdb7a96b8f5dbd4df519 /include/spd_sdram.h
parent8bd00c9494a19ef4ea2a0a9aa695ff111a380850 (diff)
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powerpc/mpc85xx:Fix "boot page TLB" entry size for NAND SPL
e500v2 processor does not support 8K page size TLB entries. So create new TLB entry only during NAND SPL boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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