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authorMatt Porter <mporter@ti.com>2012-05-07 16:49:21 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-05-15 08:31:41 +0200
commita3c3fabb0f65455068e01197e16927f0589beaa2 (patch)
tree1b6d04f49c674210f8f6e6abe83627d3d088b846 /include/sja1000.h
parentc176dd0442c40d4e98c86848091f628707f9c50a (diff)
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arm, omap3: fix warm reset serial output on OMAP36xx/AM/DM37xx
In warm reset conditions on OMAP36xx/AM/DM37xx the rom code incorrectly sets the DPLL4 clock input divider to /6.5 which is an invalid value unless the input clock is 13MHz. When a JTAG emulator is attached, a warm reset is necessary after the emulator gains control of the process. This results in a loss of serial output due to the invalid DPLL4 settings. This patch fixes the issue by resetting the DPLL4 clock input divider to /1 when the input clock is not 13MHz. AM/DM37x TRM section 3.5.3.3.3.2.1 specifies that the /6.5 setting is only used when the input clock is 13MHz. Signed-off-by: Matt Porter <mporter@ti.com>
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