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authorYork Sun <yorksun@freescale.com>2011-03-02 14:24:11 -0800
committerKumar Gala <galak@kernel.crashing.org>2011-03-05 10:13:50 -0600
commitf5b6fb7c1b988cdec8db9e96dd05d1df46c22e6b (patch)
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parent8e29ebabf825ee0c85cb0c93d6aa495cc54811ab (diff)
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powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers
The write recovery time of both registers should match. Since mode register doesn't support cycles of 9,11,13,15, we should use next higher number for both registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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