summaryrefslogtreecommitdiff
path: root/include/ppc4xx_enet.h
diff options
context:
space:
mode:
authorStefan Roese <sr@denx.de>2007-10-15 11:39:00 +0200
committerStefan Roese <sr@denx.de>2007-10-15 11:39:00 +0200
commite2e93442e558cf1500e92861f99713b2f045ea22 (patch)
treead0949eac45569d114ff409ec59d485942e567ea /include/ppc4xx_enet.h
parent5a5958b7de70ae99f0e7cbd5c97ec1346e051587 (diff)
downloadu-boot-imx-e2e93442e558cf1500e92861f99713b2f045ea22.zip
u-boot-imx-e2e93442e558cf1500e92861f99713b2f045ea22.tar.gz
u-boot-imx-e2e93442e558cf1500e92861f99713b2f045ea22.tar.bz2
ppc4xx: Fix bug in I2C bootstrap values for Sequoia/Rainier
The I2C bootstrap values that can be setup via the "bootstrap" command, were setup incorrect regarding the generation of the internal sync PCI clock. The values for PLB clock == 133MHz were slighly incorrect and the values for PLB clock == 166MHz were totally incorrect. This could lead to a hangup upon booting while PCI configuration scan. This patch fixes this issue and configures valid PCI divisor values for the sync PCI clock, with respect to the provided external async PCI frequency. Here the values of the formula in the chapter 14.2 "PCI clocking" from the 440EPx users manual: AsyncPCICLK - 1MHz <= SyncPCIClk <= (2 * AsyncPCIClk) - 1MHz 33MHz async PCI frequency: PLB = 133: => 32 <= 44.3 <= 65 (div = 3) PLB = 166: => 32 <= 55.3 <= 65 (div = 3) 66MHz async PCI frequency: PLB = 133: => 65 <= 66.5 <= 132 (div = 2) PLB = 166: => 65 <= 83 <= 132 (div = 2) Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include/ppc4xx_enet.h')
0 files changed, 0 insertions, 0 deletions