Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx

1 files changed, 0 insertions, 93 deletions

diff --git a/include/ppc440.h b/include/ppc440.h
index 01f6eaf..6ce53a6 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -48,99 +48,6 @@
 
 #define CONFIG_SYS_DCACHE_SIZE		(32 << 10)	/* For AMCC 440 CPUs	*/
 
-/*--------------------------------------------------------------------- */
-/* Special Purpose Registers						*/
-/*--------------------------------------------------------------------- */
-#define	 xer_reg 0x001
-#define	 lr_reg	0x008
-#define	 dec	0x016	/* decrementer */
-#define	 srr0	0x01a	/* save/restore register 0 */
-#define	 srr1	0x01b	/* save/restore register 1 */
-#define	 pid	0x030	/* process id */
-#define	 decar	0x036	/* decrementer auto-reload */
-#define	 csrr0	0x03a	/* critical save/restore register 0 */
-#define	 csrr1	0x03b	/* critical save/restore register 1 */
-#define	 dear	0x03d	/* data exception address register */
-#define	 esr	0x03e	/* exception syndrome register */
-#define	 ivpr	0x03f	/* interrupt prefix register */
-#define	 usprg0 0x100	/* user special purpose register general 0 */
-#define	 usprg1 0x110	/* user special purpose register general 1 */
-#define	 tblr	0x10c	/* time base lower, read only */
-#define	 tbur	0x10d	/* time base upper, read only */
-#define	 sprg1	0x111	/* special purpose register general 1 */
-#define	 sprg2	0x112	/* special purpose register general 2 */
-#define	 sprg3	0x113	/* special purpose register general 3 */
-#define	 sprg4	0x114	/* special purpose register general 4 */
-#define	 sprg5	0x115	/* special purpose register general 5 */
-#define	 sprg6	0x116	/* special purpose register general 6 */
-#define	 sprg7	0x117	/* special purpose register general 7 */
-#define	 tbl	0x11c	/* time base lower (supervisor)*/
-#define	 tbu	0x11d	/* time base upper (supervisor)*/
-#define	 pir	0x11e	/* processor id register */
-#define	 dbsr	0x130	/* debug status register */
-#define	 dbcr0	0x134	/* debug control register 0 */
-#define	 dbcr1	0x135	/* debug control register 1 */
-#define	 dbcr2	0x136	/* debug control register 2 */
-#define	 iac1	0x138	/* instruction address compare 1 */
-#define	 iac2	0x139	/* instruction address compare 2 */
-#define	 iac3	0x13a	/* instruction address compare 3 */
-#define	 iac4	0x13b	/* instruction address compare 4 */
-#define	 dac1	0x13c	/* data address compare 1 */
-#define	 dac2	0x13d	/* data address compare 2 */
-#define	 dvc1	0x13e	/* data value compare 1 */
-#define	 dvc2	0x13f	/* data value compare 2 */
-#define	 tsr	0x150	/* timer status register */
-#define	 tcr	0x154	/* timer control register */
-#define	 ivor0	0x190	/* interrupt vector offset register 0 */
-#define	 ivor1	0x191	/* interrupt vector offset register 1 */
-#define	 ivor2	0x192	/* interrupt vector offset register 2 */
-#define	 ivor3	0x193	/* interrupt vector offset register 3 */
-#define	 ivor4	0x194	/* interrupt vector offset register 4 */
-#define	 ivor5	0x195	/* interrupt vector offset register 5 */
-#define	 ivor6	0x196	/* interrupt vector offset register 6 */
-#define	 ivor7	0x197	/* interrupt vector offset register 7 */
-#define	 ivor8	0x198	/* interrupt vector offset register 8 */
-#define	 ivor9	0x199	/* interrupt vector offset register 9 */
-#define	 ivor10 0x19a	/* interrupt vector offset register 10 */
-#define	 ivor11 0x19b	/* interrupt vector offset register 11 */
-#define	 ivor12 0x19c	/* interrupt vector offset register 12 */
-#define	 ivor13 0x19d	/* interrupt vector offset register 13 */
-#define	 ivor14 0x19e	/* interrupt vector offset register 14 */
-#define	 ivor15 0x19f	/* interrupt vector offset register 15 */
-#if defined(CONFIG_440)
-#define	 mcsrr0 0x23a	/* machine check save/restore register 0 */
-#define	 mcsrr1 0x23b	/* mahcine check save/restore register 1 */
-#define	 mcsr	0x23c	/* machine check status register */
-#endif
-#define	 inv0	0x370	/* instruction cache normal victim 0 */
-#define	 inv1	0x371	/* instruction cache normal victim 1 */
-#define	 inv2	0x372	/* instruction cache normal victim 2 */
-#define	 inv3	0x373	/* instruction cache normal victim 3 */
-#define	 itv0	0x374	/* instruction cache transient victim 0 */
-#define	 itv1	0x375	/* instruction cache transient victim 1 */
-#define	 itv2	0x376	/* instruction cache transient victim 2 */
-#define	 itv3	0x377	/* instruction cache transient victim 3 */
-#define	 dnv0	0x390	/* data cache normal victim 0 */
-#define	 dnv1	0x391	/* data cache normal victim 1 */
-#define	 dnv2	0x392	/* data cache normal victim 2 */
-#define	 dnv3	0x393	/* data cache normal victim 3 */
-#define	 dtv0	0x394	/* data cache transient victim 0 */
-#define	 dtv1	0x395	/* data cache transient victim 1 */
-#define	 dtv2	0x396	/* data cache transient victim 2 */
-#define	 dtv3	0x397	/* data cache transient victim 3 */
-#define	 dvlim	0x398	/* data cache victim limit */
-#define	 ivlim	0x399	/* instruction cache victim limit */
-#define	 rstcfg 0x39b	/* reset configuration */
-#define	 dcdbtrl 0x39c	/* data cache debug tag register low */
-#define	 dcdbtrh 0x39d	/* data cache debug tag register high */
-#define	 icdbtrl 0x39e	/* instruction cache debug tag register low */
-#define	 icdbtrh 0x39f	/* instruction cache debug tag register high */
-#define	 mmucr	0x3b2	/* mmu control register */
-#define	 ccr0	0x3b3	/* core configuration register 0 */
-#define  ccr1	0x378	/* core configuration for 440x5 only */
-#define	 icdbdr 0x3d3	/* instruction cache debug data register */
-#define	 dbdr	0x3f3	/* debug data register */
-
 /******************************************************************************
  * DCRs & Related
  ******************************************************************************/