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| author | Wolfgang Denk <wd@pollux.denx.de> | 2007-03-08 11:34:24 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2007-03-08 11:34:24 +0100 |
| commit | d8be57669b37d57625bbe37c4603dab05058cea7 (patch) | |
| tree | cbe4aa270b000a8b0667e43b5581ddce89593342 /include/ppc440.h | |
| parent | 647d3c3eed0da1d1505eecabe0b0fab96f956e68 (diff) | |
| parent | 46270c285190b35d2e99f7181ec6e8c0d2d6ef4c (diff) | |
| download | u-boot-imx-d8be57669b37d57625bbe37c4603dab05058cea7.zip u-boot-imx-d8be57669b37d57625bbe37c4603dab05058cea7.tar.gz u-boot-imx-d8be57669b37d57625bbe37c4603dab05058cea7.tar.bz2 | |
Merge with /home/git/u-boot
Diffstat (limited to 'include/ppc440.h')
| -rw-r--r-- | include/ppc440.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/include/ppc440.h b/include/ppc440.h index 1c7f11c..25e338f 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -3293,26 +3293,26 @@ typedef struct { unsigned long add; /* gpio core base address */ /* * Macros for accessing the indirect EBC registers */ -#define mtebc(reg, data) { mtdcr(ebccfga,reg);mtdcr(ebccfgd,data); } -#define mfebc(reg, data) { mtdcr(ebccfga,reg);data = mfdcr(ebccfgd); } +#define mtebc(reg, data) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,data); } while (0) +#define mfebc(reg, data) do { mtdcr(ebccfga,reg);data = mfdcr(ebccfgd); } while (0) /* * Macros for accessing the indirect SDRAM controller registers */ -#define mtsdram(reg, data) { mtdcr(memcfga,reg);mtdcr(memcfgd,data); } -#define mfsdram(reg, data) { mtdcr(memcfga,reg);data = mfdcr(memcfgd); } +#define mtsdram(reg, data) do { mtdcr(memcfga,reg);mtdcr(memcfgd,data); } while (0) +#define mfsdram(reg, data) do { mtdcr(memcfga,reg);data = mfdcr(memcfgd); } while (0) /* * Macros for accessing the indirect clocking controller registers */ -#define mtclk(reg, data) { mtdcr(clkcfga,reg);mtdcr(clkcfgd,data); } -#define mfclk(reg, data) { mtdcr(clkcfga,reg);data = mfdcr(clkcfgd); } +#define mtclk(reg, data) do { mtdcr(clkcfga,reg);mtdcr(clkcfgd,data); } while (0) +#define mfclk(reg, data) do { mtdcr(clkcfga,reg);data = mfdcr(clkcfgd); } while (0) /* * Macros for accessing the sdr controller registers */ -#define mtsdr(reg, data) { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } -#define mfsdr(reg, data) { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } +#define mtsdr(reg, data) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } while (0) +#define mfsdr(reg, data) do { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } while (0) #ifndef __ASSEMBLY__ |