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| author | roy zang <tie-fei.zang@freescale.com> | 2007-02-28 16:46:48 +0800 |
|---|---|---|
| committer | Zang Tiefei <roy@bus.ap.freescale.net> | 2007-02-28 16:46:48 +0800 |
| commit | 00b574bdc8c54dbc9e03f63c24f62955d483e3ef (patch) | |
| tree | dc49c4219bafd43c2ace6c5a3e6745d7b7264194 /include/ppc440.h | |
| parent | 30bddf2c46ab2e824f217a38db033118ac4622af (diff) | |
| parent | ccbc7036648e465697ca298ba51e0e76dda352a0 (diff) | |
| download | u-boot-imx-00b574bdc8c54dbc9e03f63c24f62955d483e3ef.zip u-boot-imx-00b574bdc8c54dbc9e03f63c24f62955d483e3ef.tar.gz u-boot-imx-00b574bdc8c54dbc9e03f63c24f62955d483e3ef.tar.bz2 | |
Merge branch 'master' into hpc2
Conflicts:
drivers/Makefile
Fix the merge conflict in file drivers/Makefile
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Diffstat (limited to 'include/ppc440.h')
| -rw-r--r-- | include/ppc440.h | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/include/ppc440.h b/include/ppc440.h index 91cff41..c24f5b7 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -533,9 +533,12 @@ #define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */ #define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */ #define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */ -#define SDRAM_MCSTAT_SRMS_MASK 0x80000000 /* Mem self refresh stat mask */ +#define SDRAM_MCSTAT_SRMS_MASK 0x40000000 /* Mem self refresh stat mask */ #define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */ -#define SDRAM_MCSTAT_SRMS_SF 0x80000000 /* Mem in self refresh */ +#define SDRAM_MCSTAT_SRMS_SF 0x40000000 /* Mem in self refresh */ +#define SDRAM_MCSTAT_IDLE_MASK 0x20000000 /* Mem self refresh stat mask */ +#define SDRAM_MCSTAT_IDLE_NOT 0x00000000 /* Mem contr not idle */ +#define SDRAM_MCSTAT_IDLE 0x20000000 /* Mem contr idle */ /*-----------------------------------------------------------------------------+ | Memory Controller Options 1 @@ -730,6 +733,7 @@ #define SDRAM_WRDTR_LLWP_1_CYC 0x00000000 #define SDRAM_WRDTR_WTR_MASK 0x0E000000 #define SDRAM_WRDTR_WTR_0_DEG 0x06000000 +#define SDRAM_WRDTR_WTR_90_DEG_ADV 0x04000000 #define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000 #define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000 @@ -847,6 +851,7 @@ #define pbear 0x20 /* periph bus error addr reg */ #define pbesr 0x21 /* periph bus error status reg */ #define xbcfg 0x23 /* external bus configuration reg */ +#define EBC0_CFG 0x23 /* external bus configuration reg */ #define xbcid 0x24 /* external bus core id reg */ #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ |