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| author | Wolfgang Denk <wd@denx.de> | 2007-07-06 02:50:34 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2007-07-06 02:50:34 +0200 |
| commit | e80955f07de03fef0196353e77534b2300193c1c (patch) | |
| tree | 2fbe65d20537c38a71bacf505e285595ddd3e01a /include/ppc440.h | |
| parent | f1152f8c28db4a22087c21c618a3f7baa48e9a4f (diff) | |
| parent | b44896215a09c60fa40cae906f7ed207bbc2c492 (diff) | |
| download | u-boot-imx-e80955f07de03fef0196353e77534b2300193c1c.zip u-boot-imx-e80955f07de03fef0196353e77534b2300193c1c.tar.gz u-boot-imx-e80955f07de03fef0196353e77534b2300193c1c.tar.bz2 | |
Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xx
Diffstat (limited to 'include/ppc440.h')
| -rw-r--r-- | include/ppc440.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/include/ppc440.h b/include/ppc440.h index 76330f1..93c10f1 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -282,7 +282,6 @@ #define sdr_sdstp3 0x4003 #endif /* CONFIG_440GX */ -#ifdef CONFIG_440 /*----------------------------------------------------------------------------+ | Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only). +----------------------------------------------------------------------------*/ @@ -306,7 +305,6 @@ #define MMUCR_IULXE 0x00400000 #define MMUCR_STS 0x00100000 #define MMUCR_STID_MASK 0x000000FF -#endif /* CONFIG_440 */ #ifdef CONFIG_440SPE #undef sdr_sdstp2 @@ -1025,7 +1023,7 @@ #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */ #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -#define SDR_USB2D0CR 0x0320 +#define SDR0_USB2D0CR 0x0320 #define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC Master Selection */ #define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection */ #define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */ @@ -1423,7 +1421,7 @@ #define uicvr uic0vr #define uicvcr uic0vcr -#if defined(CONFIG_440SPE) +#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) /*----------------------------------------------------------------------------+ | Clock / Power-on-reset DCR's. +----------------------------------------------------------------------------*/ @@ -1492,9 +1490,11 @@ #define CPR0_OPBD_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1) #define CPR0_PERD 0xE0 +#if !defined(CONFIG_440EPX) #define CPR0_PERD_PERDV0_MASK 0x03000000 #define CPR0_PERD_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) #define CPR0_PERD_PERDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1) +#endif #define CPR0_MALD 0x100 #define CPR0_MALD_MALDV0_MASK 0x03000000 |