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| author | Stefan Roese <sr@denx.de> | 2008-10-21 11:43:08 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-10-21 11:43:08 +0200 |
| commit | f61f1e150c84f5b9347fca79a4bc5f2286c545d2 (patch) | |
| tree | ab90f076f18e56b2b3e8c9375b95917daa78c1d9 /include/ppc440.h | |
| parent | ec081c2c190148b374e86a795fb6b1c49caeb549 (diff) | |
| parent | f82642e33899766892499b163e60560fbbf87773 (diff) | |
| download | u-boot-imx-f61f1e150c84f5b9347fca79a4bc5f2286c545d2.zip u-boot-imx-f61f1e150c84f5b9347fca79a4bc5f2286c545d2.tar.gz u-boot-imx-f61f1e150c84f5b9347fca79a4bc5f2286c545d2.tar.bz2 | |
Merge branch 'master' of /home/stefan/git/u-boot/u-boot
Diffstat (limited to 'include/ppc440.h')
| -rw-r--r-- | include/ppc440.h | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/include/ppc440.h b/include/ppc440.h index be8d3ff..664f802 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -46,7 +46,7 @@ #ifndef __PPC440_H__ #define __PPC440_H__ -#define CFG_DCACHE_SIZE (32 << 10) /* For AMCC 440 CPUs */ +#define CONFIG_SYS_DCACHE_SIZE (32 << 10) /* For AMCC 440 CPUs */ /*--------------------------------------------------------------------- */ /* Special Purpose Registers */ @@ -1886,17 +1886,17 @@ /*----------------------------------------------------------------------------- | PCI Internal Registers et. al. (accessed via plb) +----------------------------------------------------------------------------*/ -#define PCIX0_CFGADR (CFG_PCI_BASE + 0x0ec00000) -#define PCIX0_CFGDATA (CFG_PCI_BASE + 0x0ec00004) -#define PCIX0_CFGBASE (CFG_PCI_BASE + 0x0ec80000) -#define PCIX0_IOBASE (CFG_PCI_BASE + 0x08000000) +#define PCIX0_CFGADR (CONFIG_SYS_PCI_BASE + 0x0ec00000) +#define PCIX0_CFGDATA (CONFIG_SYS_PCI_BASE + 0x0ec00004) +#define PCIX0_CFGBASE (CONFIG_SYS_PCI_BASE + 0x0ec80000) +#define PCIX0_IOBASE (CONFIG_SYS_PCI_BASE + 0x08000000) #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* PCI Local Configuration Registers --------------------------------- */ -#define PCI_MMIO_LCR_BASE (CFG_PCI_BASE + 0x0f400000) /* Real => 0x0EF400000 */ +#define PCI_MMIO_LCR_BASE (CONFIG_SYS_PCI_BASE + 0x0f400000) /* Real => 0x0EF400000 */ /* PCI Master Local Configuration Registers */ #define PCIX0_PMM0LA (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */ @@ -1981,7 +1981,7 @@ #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* USB2.0 Device */ -#define USB2D0_BASE CFG_USB2D0_BASE +#define USB2D0_BASE CONFIG_SYS_USB2D0_BASE #define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) @@ -2011,7 +2011,7 @@ #if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460SX) -#define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000700) +#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000700) #define GPIO0_OR (GPIO0_BASE+0x0) #define GPIO0_TCR (GPIO0_BASE+0x4) @@ -2022,8 +2022,8 @@ #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000B00) -#define GPIO1_BASE (CFG_PERIPHERAL_BASE+0x00000C00) +#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000B00) +#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000C00) #define GPIO0_OR (GPIO0_BASE+0x0) #define GPIO0_TCR (GPIO0_BASE+0x4) |