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authorStefan Roese <sr@denx.de>2010-08-26 17:14:51 +0200
committerStefan Roese <sr@denx.de>2010-09-03 11:14:21 +0200
commitc1ab75c7d4e5d080c630335b78681c50aa3569a5 (patch)
tree61e5c6b109fb5ed73257663dfb92aca36a34891f /include/ppc440.h
parent38570b2ff3b618892b7b7f2d4c80f5b79d49018f (diff)
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ppc4xx: Fix 440EPx bug in reconfigure_pll()
This patch fixes a bug in reconfigure_pll(), where the detection of the current bootstrap option is wrong. The ICS bits where incorrectly shifted. This bug was found on the lwmon5 board, which uses bootstrap option H (I2C bootstrap EEPROM). Additionally a bit of code was moved into the if statement, since its only used after later on. No need to run this code all the time. Also, a few empty lines are added to make the code better readable. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Rupjyoti Sarmah <rsarmah@amcc.com> Cc: Victor Gallardo <vgallardo@appliedmicro.com>
Diffstat (limited to 'include/ppc440.h')
-rw-r--r--include/ppc440.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/ppc440.h b/include/ppc440.h
index c807dda..6727753 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -1711,6 +1711,7 @@
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define CPR0_ICFG_RLI_MASK 0x80000000
+#define CPR0_ICFG_ICS_MASK 0x00000007
#define CPR0_SPCID_SPCIDV0_MASK 0x03000000
#define CPR0_SPCID_SPCIDV0_DIV1 0x01000000
#define CPR0_SPCID_SPCIDV0_DIV2 0x02000000