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| author | Stefan Roese <sr@denx.de> | 2007-06-22 10:28:26 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-06-22 10:28:26 +0200 |
| commit | e08e6453fced498b28950f36088c87c0b639a682 (patch) | |
| tree | 5730c11e7440a6b88094d050172b8e5b4b707fbd /include/ppc440.h | |
| parent | d7d5204ce2e0985ff2dfdf3a6b5b6a526cdb1c1e (diff) | |
| parent | 83b4cfa3d629dff0264366263c5e94d9a50ad80b (diff) | |
| download | u-boot-imx-e08e6453fced498b28950f36088c87c0b639a682.zip u-boot-imx-e08e6453fced498b28950f36088c87c0b639a682.tar.gz u-boot-imx-e08e6453fced498b28950f36088c87c0b639a682.tar.bz2 | |
Merge with git://www.denx.de/git/u-boot.git
Diffstat (limited to 'include/ppc440.h')
| -rw-r--r-- | include/ppc440.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/include/ppc440.h b/include/ppc440.h index 07f75de..09f8430 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -82,10 +82,7 @@ #define ivor13 0x19d /* interrupt vector offset register 13 */ #define ivor14 0x19e /* interrupt vector offset register 14 */ #define ivor15 0x19f /* interrupt vector offset register 15 */ -#if defined(CONFIG_440GX) || \ - defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#if defined(CONFIG_440) #define mcsrr0 0x23a /* machine check save/restore register 0 */ #define mcsrr1 0x23b /* mahcine check save/restore register 1 */ #define mcsr 0x23c /* machine check status register */ @@ -956,7 +953,8 @@ #define plb1_bearl (PLB_ARBITER_BASE+ 0x0C) #define plb1_bearh (PLB_ARBITER_BASE+ 0x0D) -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* Pin Function Control Register 1 */ #define SDR0_PFC1 0x4101 #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ @@ -1103,6 +1101,8 @@ #define SDR0_PFC2_SELECT_CONFIG_5 0xC0000000 /* 2xRTBI using RGMII bridge */ #define SDR0_PFC2_SELECT_CONFIG_6 0x40000000 /* 2xSMII using ZMII bridge */ +#define SDR0_PFC4 0x4104 + /* USB2PHY0 Control Register */ #define SDR0_USB2PHY0CR 0x4103 #define SDR0_USB2PHY0CR_UTMICN_MASK 0x00100000 /* PHY UTMI interface connection */ |