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authorStefan Roese <sr@denx.de>2007-06-04 08:17:29 +0200
committerStefan Roese <sr@denx.de>2007-06-04 08:17:29 +0200
commitd7d5204ce2e0985ff2dfdf3a6b5b6a526cdb1c1e (patch)
treec71da8013140d7bd5024dcde5f9cd075d4c012e2 /include/ppc440.h
parent7ebb4479b07ff294eb4d76e420753a0349f7c93b (diff)
parent19bf91f9628f80a55d4f171df71041574882b3d6 (diff)
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Merge with git://www.denx.de/git/u-boot.git
Diffstat (limited to 'include/ppc440.h')
-rw-r--r--include/ppc440.h20
1 files changed, 17 insertions, 3 deletions
diff --git a/include/ppc440.h b/include/ppc440.h
index bc1d7aa..07f75de 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -1425,9 +1425,6 @@
/*----------------------------------------------------------------------------+
| Clock / Power-on-reset DCR's.
+----------------------------------------------------------------------------*/
-#define CPR0_CFGADDR 0x00C
-#define CPR0_CFGDATA 0x00D
-
#define CPR0_CLKUPD 0x20
#define CPR0_CLKUPD_BSY_MASK 0x80000000
#define CPR0_CLKUPD_BSY_COMPLETED 0x00000000
@@ -3314,6 +3311,23 @@
#define mtsdr(reg, data) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } while (0)
#define mfsdr(reg, data) do { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } while (0)
+/*
+ * All 44x except 440GP have CPR registers (indirect DCR)
+ */
+#if !defined(CONFIG_440GP)
+#define CPR0_CFGADDR 0x00C
+#define CPR0_CFGDATA 0x00D
+
+#define mtcpr(reg, data) do { \
+ mtdcr(CPR0_CFGADDR, reg); \
+ mtdcr(CPR0_CFGDATA, data); \
+ } while (0)
+
+#define mfcpr(reg, data) do { \
+ mtdcr(CPR0_CFGADDR, reg); \
+ data = mfdcr(CPR0_CFGDATA); \
+ } while (0)
+#endif
#ifndef __ASSEMBLY__