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authorStefan Roese <sr@denx.de>2007-03-08 10:32:45 +0100
committerStefan Roese <sr@denx.de>2007-03-08 10:32:45 +0100
commitcd84528f203a28f73e09c11e2737218938eaf71b (patch)
tree69ace4c4c5dbc7cfc36da54469b3ee70edeae05f /include/ppc440.h
parentfa1aef15bcd47736687be1af544506e90fba545d (diff)
parent00cdb4ce5e1b42248e7e6522ad0da3421b988afa (diff)
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Merge with /home/stefan/git/u-boot/yucca-ddr2
Diffstat (limited to 'include/ppc440.h')
-rw-r--r--include/ppc440.h25
1 files changed, 24 insertions, 1 deletions
diff --git a/include/ppc440.h b/include/ppc440.h
index 1c7f11c..5fe4076 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -417,7 +417,9 @@
#define SDR0_PEGPLLSET1 0x000003A0 /* PE Pll LC Tank Setting1 */
#define SDR0_PEGPLLSET2 0x000003A1 /* PE Pll LC Tank Setting2 */
#define SDR0_PEGPLLSTS 0x000003A2 /* PE Pll LC Tank Status */
+#endif /* CONFIG_440SPE */
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
/*----------------------------------------------------------------------------+
| SDRAM Controller
+----------------------------------------------------------------------------*/
@@ -453,9 +455,16 @@
/*-----------------------------------------------------------------------------+
| Memory Bank 0-7 configuration
+-----------------------------------------------------------------------------*/
-#define SDRAM_RXBAS_SDBA_MASK 0xFF800000 /* Base address */
+#if defined(CONFIG_440SPE)
+#define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */
#define SDRAM_RXBAS_SDBA_ENCODE(n) ((((unsigned long)(n))&0xFFE00000)>>2)
#define SDRAM_RXBAS_SDBA_DECODE(n) ((((unsigned long)(n))&0xFFE00000)<<2)
+#endif /* CONFIG_440SPE */
+#if defined(CONFIG_440SP)
+#define SDRAM_RXBAS_SDBA_MASK 0xFF800000 /* Base address */
+#define SDRAM_RXBAS_SDBA_ENCODE(n) ((((unsigned long)(n))&0xFF800000))
+#define SDRAM_RXBAS_SDBA_DECODE(n) ((((unsigned long)(n))&0xFF800000))
+#endif /* CONFIG_440SP */
#define SDRAM_RXBAS_SDSZ_MASK 0x0000FFC0 /* Size */
#define SDRAM_RXBAS_SDSZ_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<6)
#define SDRAM_RXBAS_SDSZ_DECODE(n) ((((unsigned long)(n))>>6)&0x3FF)
@@ -2167,6 +2176,20 @@
/*-----------------------------------------------------------------------------+
| SDR0 Bit Settings
+-----------------------------------------------------------------------------*/
+#if defined(CONFIG_440SP)
+#define SDR0_SRST 0x0200
+
+#define SDR0_DDR0 0x00E1
+#define SDR0_DDR0_DPLLRST 0x80000000
+#define SDR0_DDR0_DDRM_MASK 0x60000000
+#define SDR0_DDR0_DDRM_DDR1 0x20000000
+#define SDR0_DDR0_DDRM_DDR2 0x40000000
+#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29)
+#define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03)
+#define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0)
+#define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF)
+#endif
+
#if defined(CONFIG_440SPE)
#define SDR0_CP440 0x0180
#define SDR0_CP440_ERPN_MASK 0x30000000