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authorMarian Balakowicz <m8@semihalf.com>2006-06-30 18:35:04 +0200
committerMarian Balakowicz <m8@semihalf.com>2006-06-30 18:35:04 +0200
commitbba68377320608b3c3f7c0fef30452bdaa8b0408 (patch)
tree23913f4a408cc4b70f67f7f7570a2d0eb3dbbe7d /include/ppc440.h
parent971a5dd11a6b74f45b92473c6126e05229700d46 (diff)
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Fix CONFIG_440_GX define usage.
Diffstat (limited to 'include/ppc440.h')
-rw-r--r--include/ppc440.h9
1 files changed, 3 insertions, 6 deletions
diff --git a/include/ppc440.h b/include/ppc440.h
index ea46cc0..d5a9f66 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -214,14 +214,14 @@
#define mem_dlycal 0x0084 /* delay line calibration register */
#define mem_eccesr 0x0098 /* ECC error status */
-#ifdef CONFIG_440_GX
+#ifdef CONFIG_440GX
#define sdr_amp 0x0240
#define sdr_xpllc 0x01c1
#define sdr_xplld 0x01c2
#define sdr_xcr 0x01c0
#define sdr_sdstp2 0x4001
#define sdr_sdstp3 0x4003
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
#ifdef CONFIG_440SPE
#undef sdr_sdstp2
@@ -759,9 +759,6 @@
#define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */
#endif /* CONFIG_440SPE */
-#ifndef CONFIG_440_GX
-#endif /* not CONFIG_440SPE */
-
/*-----------------------------------------------------------------------------
| External Bus Controller
+----------------------------------------------------------------------------*/
@@ -1626,7 +1623,7 @@
#define UICB0_ALL (UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \
UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI)
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
/*---------------------------------------------------------------------------+
| Universal interrupt controller interrupts
+---------------------------------------------------------------------------*/