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authorStefan Roese <sr@denx.de>2008-03-19 16:20:49 +0100
committerStefan Roese <sr@denx.de>2008-03-27 09:54:41 +0100
commit4c9e855734c523900322a7c3cdd9099b4f51b51d (patch)
tree2701c888929cf2559477fd63c03eaf23648d81a9 /include/ppc440.h
parentd8bd643141af4710d7f1b69bbab6b760de0af0a1 (diff)
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ppc4xx: Add AMCC Glacier 406GT eval board support
This patch adds support for the AMCC Glacier 460GT eval board. The main difference to the Canyonlands board are listed here: - 4 ethernet ports instead of 2 - no SATA port - no USB port Currently EMAC2+3 are not working. This will be fixed in a later release. Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include/ppc440.h')
-rw-r--r--include/ppc440.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/include/ppc440.h b/include/ppc440.h
index 10517cb..642d1de 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -2023,9 +2023,13 @@
#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg */
#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg */
#define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table pointer reg */
+#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table pointer reg */
+#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table pointer reg */
#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */
#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */
#define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */
+#define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */
+#define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */
#endif /* CONFIG_440GX */