ppc4xx: Consolidate PPC4xx UIC defines

This 2nd patch now removes all UIC mask bit definition. They should be
generated from the vectors by using the UIC_MASK() macro from now on.
This way only the vectors need to get defined for new PPC's.

Also only the really used interrupt vectors are now defined. This makes
definitions for new PPC versions easier and less error prone.

Another part of this patch is that the 4xx emac driver got a little
cleanup, since now the usage of the interrupts is clearer.

Signed-off-by: Stefan Roese <sr@denx.de>

1 files changed, 0 insertions, 708 deletions

diff --git a/include/ppc440.h b/include/ppc440.h
index f843792..5df8eb0 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -864,98 +864,6 @@
 #define cntrl0		(CNTRL_DCR_BASE+0x3b)	/* Control 0 register		*/
 #define cntrl1		(CNTRL_DCR_BASE+0x3a)	/* Control 1 register		*/
 
-/*-----------------------------------------------------------------------------
- | Universal interrupt controller
- +----------------------------------------------------------------------------*/
-#define UIC_SR	0x0			/* UIC status			   */
-#define UIC_ER	0x2			/* UIC enable			   */
-#define UIC_CR	0x3			/* UIC critical			   */
-#define UIC_PR	0x4			/* UIC polarity			   */
-#define UIC_TR	0x5			/* UIC triggering		   */
-#define UIC_MSR 0x6			/* UIC masked status		   */
-#define UIC_VR	0x7			/* UIC vector			   */
-#define UIC_VCR 0x8			/* UIC vector configuration	   */
-
-#define UIC0_DCR_BASE 0xc0
-#define uic0sr	(UIC0_DCR_BASE+0x0)   /* UIC0 status			   */
-#define uic0er	(UIC0_DCR_BASE+0x2)   /* UIC0 enable			   */
-#define uic0cr	(UIC0_DCR_BASE+0x3)   /* UIC0 critical			   */
-#define uic0pr	(UIC0_DCR_BASE+0x4)   /* UIC0 polarity			   */
-#define uic0tr	(UIC0_DCR_BASE+0x5)   /* UIC0 triggering		   */
-#define uic0msr (UIC0_DCR_BASE+0x6)   /* UIC0 masked status		   */
-#define uic0vr	(UIC0_DCR_BASE+0x7)   /* UIC0 vector			   */
-#define uic0vcr (UIC0_DCR_BASE+0x8)   /* UIC0 vector configuration	   */
-
-#define UIC1_DCR_BASE 0xd0
-#define uic1sr	(UIC1_DCR_BASE+0x0)   /* UIC1 status			   */
-#define uic1er	(UIC1_DCR_BASE+0x2)   /* UIC1 enable			   */
-#define uic1cr	(UIC1_DCR_BASE+0x3)   /* UIC1 critical			   */
-#define uic1pr	(UIC1_DCR_BASE+0x4)   /* UIC1 polarity			   */
-#define uic1tr	(UIC1_DCR_BASE+0x5)   /* UIC1 triggering		   */
-#define uic1msr (UIC1_DCR_BASE+0x6)   /* UIC1 masked status		   */
-#define uic1vr	(UIC1_DCR_BASE+0x7)   /* UIC1 vector			   */
-#define uic1vcr (UIC1_DCR_BASE+0x8)   /* UIC1 vector configuration	   */
-
-#if defined(CONFIG_440SPE) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_460SX)
-#define UIC2_DCR_BASE 0xe0
-#define uic2sr	(UIC2_DCR_BASE+0x0)   /* UIC2 status-Read Clear		*/
-#define uic2srs	(UIC2_DCR_BASE+0x1)   /* UIC2 status-Read Set */
-#define uic2er	(UIC2_DCR_BASE+0x2)   /* UIC2 enable			*/
-#define uic2cr	(UIC2_DCR_BASE+0x3)   /* UIC2 critical			*/
-#define uic2pr	(UIC2_DCR_BASE+0x4)   /* UIC2 polarity			*/
-#define uic2tr	(UIC2_DCR_BASE+0x5)   /* UIC2 triggering		*/
-#define uic2msr (UIC2_DCR_BASE+0x6)   /* UIC2 masked status		*/
-#define uic2vr	(UIC2_DCR_BASE+0x7)   /* UIC2 vector			*/
-#define uic2vcr (UIC2_DCR_BASE+0x8)   /* UIC2 vector configuration	*/
-
-#define UIC3_DCR_BASE 0xf0
-#define uic3sr	(UIC3_DCR_BASE+0x0)   /* UIC3 status-Read Clear		*/
-#define uic3srs	(UIC3_DCR_BASE+0x1)   /* UIC3 status-Read Set */
-#define uic3er	(UIC3_DCR_BASE+0x2)   /* UIC3 enable			*/
-#define uic3cr	(UIC3_DCR_BASE+0x3)   /* UIC3 critical			*/
-#define uic3pr	(UIC3_DCR_BASE+0x4)   /* UIC3 polarity			*/
-#define uic3tr	(UIC3_DCR_BASE+0x5)   /* UIC3 triggering		*/
-#define uic3msr (UIC3_DCR_BASE+0x6)   /* UIC3 masked status		*/
-#define uic3vr	(UIC3_DCR_BASE+0x7)   /* UIC3 vector			*/
-#define uic3vcr (UIC3_DCR_BASE+0x8)   /* UIC3 vector configuration	*/
-#endif /* CONFIG_440SPE */
-
-#if defined(CONFIG_440GX)
-#define UIC2_DCR_BASE 0x210
-#define uic2sr	(UIC2_DCR_BASE+0x0)   /* UIC2 status			   */
-#define uic2er	(UIC2_DCR_BASE+0x2)   /* UIC2 enable			   */
-#define uic2cr	(UIC2_DCR_BASE+0x3)   /* UIC2 critical			   */
-#define uic2pr	(UIC2_DCR_BASE+0x4)   /* UIC2 polarity			   */
-#define uic2tr	(UIC2_DCR_BASE+0x5)   /* UIC2 triggering		   */
-#define uic2msr (UIC2_DCR_BASE+0x6)   /* UIC2 masked status		   */
-#define uic2vr	(UIC2_DCR_BASE+0x7)   /* UIC2 vector			   */
-#define uic2vcr (UIC2_DCR_BASE+0x8)   /* UIC2 vector configuration	   */
-
-
-#define UIC_DCR_BASE 0x200
-#define uicb0sr	 (UIC_DCR_BASE+0x0)   /* UIC Base Status Register	   */
-#define uicb0er	 (UIC_DCR_BASE+0x2)   /* UIC Base enable		   */
-#define uicb0cr	 (UIC_DCR_BASE+0x3)   /* UIC Base critical		   */
-#define uicb0pr	 (UIC_DCR_BASE+0x4)   /* UIC Base polarity		   */
-#define uicb0tr	 (UIC_DCR_BASE+0x5)   /* UIC Base triggering		   */
-#define uicb0msr (UIC_DCR_BASE+0x6)   /* UIC Base masked status		   */
-#define uicb0vr	 (UIC_DCR_BASE+0x7)   /* UIC Base vector		   */
-#define uicb0vcr (UIC_DCR_BASE+0x8)   /* UIC Base vector configuration	   */
-#endif /* CONFIG_440GX */
-
-/* The following is for compatibility with 405 code */
-#define uicsr  uic0sr
-#define uicer  uic0er
-#define uiccr  uic0cr
-#define uicpr  uic0pr
-#define uictr  uic0tr
-#define uicmsr uic0msr
-#define uicvr  uic0vr
-#define uicvcr uic0vcr
-
 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX)
 /*----------------------------------------------------------------------------+
 | Clock / Power-on-reset DCR's.
@@ -1139,622 +1047,6 @@
 #define malrcbs24   (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg    */
 #endif /* CONFIG_440GX */
 
-
-/*---------------------------------------------------------------------------+
-|  Universal interrupt controller 0 interrupts (UIC0)
-+---------------------------------------------------------------------------*/
-#if defined(CONFIG_440SP)
-#define UIC_U0		0x80000000	/* UART 0			    */
-#define UIC_U1		0x40000000	/* UART 1			    */
-#define UIC_IIC0	0x20000000	/* IIC				    */
-#define UIC_IIC1	0x10000000	/* IIC				    */
-#define UIC_PIM		0x08000000	/* PCI0 inbound message		    */
-#define UIC_PCRW	0x04000000	/* PCI0 command write register	    */
-#define UIC_PPM		0x02000000	/* PCI0 power management	    */
-#define UIC_PVPD	0x01000000	/* PCI0 VPD Access		    */
-#define UIC_MSI0	0x00800000	/* PCI0 MSI level 0		    */
-#define UIC_P1IM	0x00400000	/* PCI1 Inbound Message		    */
-#define UIC_P1CRW	0x00200000	/* PCI1 command write register	    */
-#define UIC_P1PM	0x00100000	/* PCI1 power management	    */
-#define UIC_P1VPD	0x00080000	/* PCI1 VPD Access		    */
-#define UIC_P1MSI0	0x00040000	/* PCI1 MSI level 0		    */
-#define UIC_P2IM	0x00020000	/* PCI2 inbound message		    */
-#define UIC_P2CRW	0x00010000	/* PCI2 command register write	    */
-#define UIC_P2PM	0x00008000	/* PCI2 power management	    */
-#define UIC_P2VPD	0x00004000	/* PCI2 VPD access		    */
-#define UIC_P2MSI0	0x00002000	/* PCI2 MSI level 0		    */
-#define UIC_D0CPF	0x00001000	/* DMA0 command pointer		    */
-#define UIC_D0CSF	0x00000800	/* DMA0 command status		    */
-#define UIC_D1CPF	0x00000400	/* DMA1 command pointer		    */
-#define UIC_D1CSF	0x00000200	/* DMA1 command status		    */
-#define UIC_I2OID	0x00000100	/* I2O inbound doorbell		    */
-#define UIC_I2OPLF	0x00000080	/* I2O inbound post list	    */
-#define UIC_I2O0LL	0x00000040	/* I2O0 low latency PLB write	    */
-#define UIC_I2O1LL	0x00000020	/* I2O1 low latency PLB write	    */
-#define UIC_I2O0HB	0x00000010	/* I2O0 high bandwidth PLB write    */
-#define UIC_I2O1HB	0x00000008	/* I2O1 high bandwidth PLB write    */
-#define UIC_GPTCT	0x00000004	/* GPT count timer		    */
-#define UIC_UIC1NC	0x00000002	/* UIC1 non-critical interrupt	    */
-#define UIC_UIC1C	0x00000001	/* UIC1 critical interrupt	    */
-#elif defined(CONFIG_440GX) || defined(CONFIG_440EP)
-#define UIC_U0		0x80000000	/* UART 0			    */
-#define UIC_U1		0x40000000	/* UART 1			    */
-#define UIC_IIC0	0x20000000	/* IIC				    */
-#define UIC_IIC1	0x10000000	/* IIC				    */
-#define UIC_PIM		0x08000000	/* PCI inbound message		    */
-#define UIC_PCRW	0x04000000	/* PCI command register write	    */
-#define UIC_PPM		0x02000000	/* PCI power management		    */
-#define UIC_MSI0	0x01000000	/* PCI MSI level 0		    */
-#define UIC_MSI1	0x00800000	/* PCI MSI level 1		    */
-#define UIC_MSI2	0x00400000	/* PCI MSI level 2		    */
-#define UIC_MTE		0x00200000	/* MAL TXEOB			    */
-#define UIC_MRE		0x00100000	/* MAL RXEOB			    */
-#define UIC_D0		0x00080000	/* DMA channel 0		    */
-#define UIC_D1		0x00040000	/* DMA channel 1		    */
-#define UIC_D2		0x00020000	/* DMA channel 2		    */
-#define UIC_D3		0x00010000	/* DMA channel 3		    */
-#define UIC_RSVD0	0x00008000	/* Reserved			    */
-#define UIC_RSVD1	0x00004000	/* Reserved			    */
-#define UIC_CT0		0x00002000	/* GPT compare timer 0		    */
-#define UIC_CT1		0x00001000	/* GPT compare timer 1		    */
-#define UIC_CT2		0x00000800	/* GPT compare timer 2		    */
-#define UIC_CT3		0x00000400	/* GPT compare timer 3		    */
-#define UIC_CT4		0x00000200	/* GPT compare timer 4		    */
-#define UIC_EIR0	0x00000100	/* External interrupt 0		    */
-#define UIC_EIR1	0x00000080	/* External interrupt 1		    */
-#define UIC_EIR2	0x00000040	/* External interrupt 2		    */
-#define UIC_EIR3	0x00000020	/* External interrupt 3		    */
-#define UIC_EIR4	0x00000010	/* External interrupt 4		    */
-#define UIC_EIR5	0x00000008	/* External interrupt 5		    */
-#define UIC_EIR6	0x00000004	/* External interrupt 6		    */
-#define UIC_UIC1NC	0x00000002	/* UIC1 non-critical interrupt	    */
-#define UIC_UIC1C	0x00000001	/* UIC1 critical interrupt	    */
-
-#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-
-#define UIC_U0        0x80000000  /* UART 0                             */
-#define UIC_U1        0x40000000  /* UART 1                             */
-#define UIC_IIC0      0x20000000  /* IIC                                */
-#define UIC_KRD       0x10000000  /* Kasumi Ready for data              */
-#define UIC_KDA       0x08000000  /* Kasumi Data Available              */
-#define UIC_PCRW      0x04000000  /* PCI command register write         */
-#define UIC_PPM       0x02000000  /* PCI power management               */
-#define UIC_IIC1      0x01000000  /* IIC                                */
-#define UIC_SPI       0x00800000  /* SPI                                */
-#define UIC_EPCISER   0x00400000  /* External PCI SERR                  */
-#define UIC_MTE       0x00200000  /* MAL TXEOB                          */
-#define UIC_MRE       0x00100000  /* MAL RXEOB                          */
-#define UIC_D0        0x00080000  /* DMA channel 0                      */
-#define UIC_D1        0x00040000  /* DMA channel 1                      */
-#define UIC_D2        0x00020000  /* DMA channel 2                      */
-#define UIC_D3        0x00010000  /* DMA channel 3                      */
-#define UIC_UD0       0x00008000  /* UDMA irq 0                         */
-#define UIC_UD1       0x00004000  /* UDMA irq 1                         */
-#define UIC_UD2       0x00002000  /* UDMA irq 2                         */
-#define UIC_UD3       0x00001000  /* UDMA irq 3                         */
-#define UIC_HSB2D     0x00000800  /* USB2.0 Device                      */
-#define UIC_OHCI1     0x00000400  /* USB2.0 Host OHCI irq 1             */
-#define UIC_OHCI2     0x00000200  /* USB2.0 Host OHCI irq 2             */
-#define UIC_EIP94     0x00000100  /* Security EIP94                     */
-#define UIC_ETH0      0x00000080  /* Emac 0                             */
-#define UIC_ETH1      0x00000040  /* Emac 1                             */
-#define UIC_EHCI      0x00000020  /* USB2.0 Host EHCI                   */
-#define UIC_EIR4      0x00000010  /* External interrupt 4               */
-#define UIC_UIC2NC    0x00000008  /* UIC2 non-critical interrupt        */
-#define UIC_UIC2C     0x00000004  /* UIC2 critical interrupt            */
-#define UIC_UIC1NC    0x00000002  /* UIC1 non-critical interrupt        */
-#define UIC_UIC1C     0x00000001  /* UIC1 critical interrupt            */
-
-/* For compatibility with 405 code */
-#define UIC_MAL_TXEOB	UIC_MTE
-#define UIC_MAL_RXEOB	UIC_MRE
-
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
-
-#define UIC_RSVD0	0x80000000	/* N/A - unused			    */
-#define UIC_U1		0x40000000	/* UART 1			    */
-#define UIC_IIC0	0x20000000	/* IIC				    */
-#define UIC_IIC1	0x10000000	/* IIC				    */
-#define UIC_PIM		0x08000000	/* PCI inbound message		    */
-#define UIC_PCRW	0x04000000	/* PCI command register write	    */
-#define UIC_PPM		0x02000000	/* PCI power management		    */
-#define UIC_PCIVPD	0x01000000	/* PCI VPD			    */
-#define UIC_MSI0	0x00800000	/* PCI MSI level 0		    */
-#define UIC_EIR0	0x00400000	/* External interrupt 0		    */
-#define UIC_UIC2NC	0x00200000	/* UIC2 non-critical interrupt	    */
-#define UIC_UIC2C	0x00100000	/* UIC2 critical interrupt	    */
-#define UIC_D0		0x00080000	/* DMA channel 0		    */
-#define UIC_D1		0x00040000	/* DMA channel 1		    */
-#define UIC_D2		0x00020000	/* DMA channel 2		    */
-#define UIC_D3		0x00010000	/* DMA channel 3		    */
-#define UIC_UIC3NC	0x00008000	/* UIC3 non-critical interrupt	    */
-#define UIC_UIC3C	0x00004000	/* UIC3 critical interrupt	    */
-#define UIC_EIR1	0x00002000	/* External interrupt 1		    */
-#define UIC_TRNGDA	0x00001000	/* TRNG data available		    */
-#define UIC_PKAR1	0x00000800	/* PKA ready (PKA[1])		    */
-#define UIC_D1CPFF	0x00000400	/* DMA1 cp fifo full		    */
-#define UIC_D1CSNS	0x00000200	/* DMA1 cs fifo needs service	    */
-#define UIC_I2OID	0x00000100	/* I2O inbound door bell	    */
-#define UIC_I2OLNE	0x00000080	/* I2O Inbound Post List FIFO Not Empty */
-#define UIC_I20R0LL	0x00000040	/* I2O Region 0 Low Latency PLB Write */
-#define UIC_I2OR1LL	0x00000020	/* I2O Region 1 Low Latency PLB Write */
-#define UIC_I20R0HB	0x00000010	/* I2O Region 0 High Bandwidth PLB Write */
-#define UIC_I2OR1HB	0x00000008	/* I2O Region 1 High Bandwidth PLB Write */
-#define UIC_EIP94	0x00000004	/* Security EIP94		    */
-#define UIC_UIC1NC	0x00000002	/* UIC1 non-critical interrupt	    */
-#define UIC_UIC1C	0x00000001	/* UIC1 critical interrupt	    */
-
-#elif !defined(CONFIG_440SPE)
-#define UIC_U0		0x80000000	/* UART 0			    */
-#define UIC_U1		0x40000000	/* UART 1			    */
-#define UIC_IIC0	0x20000000	/* IIC				    */
-#define UIC_IIC1	0x10000000	/* IIC				    */
-#define UIC_PIM		0x08000000	/* PCI inbound message		    */
-#define UIC_PCRW	0x04000000	/* PCI command register write	    */
-#define UIC_PPM		0x02000000	/* PCI power management		    */
-#define UIC_MSI0	0x01000000	/* PCI MSI level 0		    */
-#define UIC_MSI1	0x00800000	/* PCI MSI level 1		    */
-#define UIC_MSI2	0x00400000	/* PCI MSI level 2		    */
-#define UIC_MTE		0x00200000	/* MAL TXEOB			    */
-#define UIC_MRE		0x00100000	/* MAL RXEOB			    */
-#define UIC_D0		0x00080000	/* DMA channel 0		    */
-#define UIC_D1		0x00040000	/* DMA channel 1		    */
-#define UIC_D2		0x00020000	/* DMA channel 2		    */
-#define UIC_D3		0x00010000	/* DMA channel 3		    */
-#define UIC_RSVD0	0x00008000	/* Reserved			    */
-#define UIC_RSVD1	0x00004000	/* Reserved			    */
-#define UIC_CT0		0x00002000	/* GPT compare timer 0		    */
-#define UIC_CT1		0x00001000	/* GPT compare timer 1		    */
-#define UIC_CT2		0x00000800	/* GPT compare timer 2		    */
-#define UIC_CT3		0x00000400	/* GPT compare timer 3		    */
-#define UIC_CT4		0x00000200	/* GPT compare timer 4		    */
-#define UIC_EIR0	0x00000100	/* External interrupt 0		    */
-#define UIC_EIR1	0x00000080	/* External interrupt 1		    */
-#define UIC_EIR2	0x00000040	/* External interrupt 2		    */
-#define UIC_EIR3	0x00000020	/* External interrupt 3		    */
-#define UIC_EIR4	0x00000010	/* External interrupt 4		    */
-#define UIC_EIR5	0x00000008	/* External interrupt 5		    */
-#define UIC_EIR6	0x00000004	/* External interrupt 6		    */
-#define UIC_UIC1NC	0x00000002	/* UIC1 non-critical interrupt	    */
-#define UIC_UIC1C	0x00000001	/* UIC1 critical interrupt	    */
-#endif /* CONFIG_440GX */
-
-/* For compatibility with 405 code */
-#define UIC_MAL_TXEOB	UIC_MTE
-#define UIC_MAL_RXEOB	UIC_MRE
-
-/*---------------------------------------------------------------------------+
-|  Universal interrupt controller 1 interrupts (UIC1)
-+---------------------------------------------------------------------------*/
-#if defined(CONFIG_440SP)
-#define UIC_EIR0	0x80000000	/* External interrupt 0		    */
-#define UIC_MS		0x40000000	/* MAL SERR			    */
-#define UIC_MTDE	0x20000000	/* MAL TXDE			    */
-#define UIC_MRDE	0x10000000	/* MAL RXDE			    */
-#define UIC_DECE	0x08000000	/* DDR SDRAM correctible error	    */
-#define UIC_EBCO	0x04000000	/* EBCO interrupt status	    */
-#define UIC_MTE		0x02000000	/* MAL TXEOB			    */
-#define UIC_MRE		0x01000000	/* MAL RXEOB			    */
-#define UIC_P0MSI1	0x00800000	/* PCI0 MSI level 1		    */
-#define UIC_P1MSI1	0x00400000	/* PCI1 MSI level 1		    */
-#define UIC_P2MSI1	0x00200000	/* PCI2 MSI level 1		    */
-#define UIC_L2C		0x00100000	/* L2 cache			    */
-#define UIC_CT0		0x00080000	/* GPT compare timer 0		    */
-#define UIC_CT1		0x00040000	/* GPT compare timer 1		    */
-#define UIC_CT2		0x00020000	/* GPT compare timer 2		    */
-#define UIC_CT3		0x00010000	/* GPT compare timer 3		    */
-#define UIC_CT4		0x00008000	/* GPT compare timer 4		    */
-#define UIC_EIR1	0x00004000	/* External interrupt 1		    */
-#define UIC_EIR2	0x00002000	/* External interrupt 2		    */
-#define UIC_EIR3	0x00001000	/* External interrupt 3		    */
-#define UIC_EIR4	0x00000800	/* External interrupt 4		    */
-#define UIC_EIR5	0x00000400	/* External interrupt 5		    */
-#define UIC_DMAE	0x00000200	/* DMA error			    */
-#define UIC_I2OE	0x00000100	/* I2O error			    */
-#define UIC_SRE		0x00000080	/* Serial ROM error		    */
-#define UIC_P0AE	0x00000040	/* PCI0 asynchronous error	    */
-#define UIC_P1AE	0x00000020	/* PCI1 asynchronous error	    */
-#define UIC_P2AE	0x00000010	/* PCI2 asynchronous error	    */
-#define UIC_ETH0	0x00000008	/* Ethernet 0			    */
-#define UIC_EWU0	0x00000004	/* Ethernet 0 wakeup		    */
-#define UIC_ETH1	0x00000002	/* Reserved			    */
-#define UIC_XOR		0x00000001	/* XOR				    */
-#elif defined(CONFIG_440GX) || defined(CONFIG_440EP)
-#define UIC_MS		0x80000000	/* MAL SERR			    */
-#define UIC_MTDE	0x40000000	/* MAL TXDE			    */
-#define UIC_MRDE	0x20000000	/* MAL RXDE			    */
-#define UIC_DEUE	0x10000000	/* DDR SDRAM ECC uncorrectible error*/
-#define UIC_DECE	0x08000000	/* DDR SDRAM correctible error	    */
-#define UIC_EBCO	0x04000000	/* EBCO interrupt status	    */
-#define UIC_EBMI	0x02000000	/* EBMI interrupt status	    */
-#define UIC_OPB		0x01000000	/* OPB to PLB bridge interrupt stat */
-#define UIC_MSI3	0x00800000	/* PCI MSI level 3		    */
-#define UIC_MSI4	0x00400000	/* PCI MSI level 4		    */
-#define UIC_MSI5	0x00200000	/* PCI MSI level 5		    */
-#define UIC_MSI6	0x00100000	/* PCI MSI level 6		    */
-#define UIC_MSI7	0x00080000	/* PCI MSI level 7		    */
-#define UIC_MSI8	0x00040000	/* PCI MSI level 8		    */
-#define UIC_MSI9	0x00020000	/* PCI MSI level 9		    */
-#define UIC_MSI10	0x00010000	/* PCI MSI level 10		    */
-#define UIC_MSI11	0x00008000	/* PCI MSI level 11		    */
-#define UIC_PPMI	0x00004000	/* PPM interrupt status		    */
-#define UIC_EIR7	0x00002000	/* External interrupt 7		    */
-#define UIC_EIR8	0x00001000	/* External interrupt 8		    */
-#define UIC_EIR9	0x00000800	/* External interrupt 9		    */
-#define UIC_EIR10	0x00000400	/* External interrupt 10	    */
-#define UIC_EIR11	0x00000200	/* External interrupt 11	    */
-#define UIC_EIR12	0x00000100	/* External interrupt 12	    */
-#define UIC_SRE		0x00000080	/* Serial ROM error		    */
-#define UIC_RSVD2	0x00000040	/* Reserved			    */
-#define UIC_RSVD3	0x00000020	/* Reserved			    */
-#define UIC_PAE		0x00000010	/* PCI asynchronous error	    */
-#define UIC_ETH0	0x00000008	/* Ethernet 0			    */
-#define UIC_EWU0	0x00000004	/* Ethernet 0 wakeup		    */
-#define UIC_ETH1	0x00000002	/* Ethernet 1			    */
-#define UIC_EWU1	0x00000001	/* Ethernet 1 wakeup		    */
-
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
-
-#define UIC_EIR2	0x80000000	/* External interrupt 2		    */
-#define UIC_U0		0x40000000	/* UART 0			    */
-#define UIC_SPI		0x20000000	/* SPI				    */
-#define UIC_TRNGAL	0x10000000	/* TRNG alarm			    */
-#define UIC_DEUE	0x08000000	/* DDR SDRAM ECC correct/uncorrectable error */
-#define UIC_EBCO	0x04000000	/* EBCO interrupt status	    */
-#define UIC_NDFC	0x02000000	/* NDFC				    */
-#define UIC_EIPPKPSE	0x01000000	/* EIPPKP slave error		    */
-#define UIC_P0MSI1	0x00800000	/* PCI0 MSI level 1		    */
-#define UIC_P0MSI2	0x00400000	/* PCI0 MSI level 2		    */
-#define UIC_P0MSI3	0x00200000	/* PCI0 MSI level 3		    */
-#define UIC_L2C		0x00100000	/* L2 cache			    */
-#define UIC_CT0		0x00080000	/* GPT compare timer 0		    */
-#define UIC_CT1		0x00040000	/* GPT compare timer 1		    */
-#define UIC_CT2		0x00020000	/* GPT compare timer 2		    */
-#define UIC_CT3		0x00010000	/* GPT compare timer 3		    */
-#define UIC_CT4		0x00008000	/* GPT compare timer 4		    */
-#define UIC_CT5		0x00004000	/* GPT compare timer 5		    */
-#define UIC_CT6		0x00002000	/* GPT compare timer 6		    */
-#define UIC_GPTDC	0x00001000	/* GPT decrementer pulse	    */
-#define UIC_EIR3	0x00000800	/* External interrupt 3		    */
-#define UIC_EIR4	0x00000400	/* External interrupt 4		    */
-#define UIC_DMAE	0x00000200	/* DMA error			    */
-#define UIC_I2OE	0x00000100	/* I2O error			    */
-#define UIC_SRE		0x00000080	/* Serial ROM error		    */
-#define UIC_P0AE	0x00000040	/* PCI0 asynchronous error	    */
-#define UIC_EIR5	0x00000020	/* External interrupt 5		    */
-#define UIC_EIR6	0x00000010	/* External interrupt 6		    */
-#define UIC_U2		0x00000008	/* UART 2			    */
-#define UIC_U3		0x00000004	/* UART 3			    */
-#define UIC_EIR7	0x00000002	/* External interrupt 7		    */
-#define UIC_EIR8	0x00000001	/* External interrupt 8		    */
-
-#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-
-#define UIC_MS        0x80000000  /* MAL SERR                           */
-#define UIC_MTDE      0x40000000  /* MAL TXDE                           */
-#define UIC_MRDE      0x20000000  /* MAL RXDE                           */
-#define UIC_U2        0x10000000  /* UART 2                             */
-#define UIC_U3        0x08000000  /* UART 3                             */
-#define UIC_EBCO      0x04000000  /* EBCO interrupt status              */
-#define UIC_NDFC      0x02000000  /* NDFC                               */
-#define UIC_KSLE      0x01000000  /* KASUMI slave error                 */
-#define UIC_CT5       0x00800000  /* GPT compare timer 5                */
-#define UIC_CT6       0x00400000  /* GPT compare timer 6                */
-#define UIC_PLB34I0   0x00200000  /* PLB3X4X MIRQ0                      */
-#define UIC_PLB34I1   0x00100000  /* PLB3X4X MIRQ1                      */
-#define UIC_PLB34I2   0x00080000  /* PLB3X4X MIRQ2                      */
-#define UIC_PLB34I3   0x00040000  /* PLB3X4X MIRQ3                      */
-#define UIC_PLB34I4   0x00020000  /* PLB3X4X MIRQ4                      */
-#define UIC_PLB34I5   0x00010000  /* PLB3X4X MIRQ5                      */
-#define UIC_CT0       0x00008000  /* GPT compare timer 0                */
-#define UIC_CT1       0x00004000  /* GPT compare timer 1                */
-#define UIC_EIR7      0x00002000  /* External interrupt 7               */
-#define UIC_EIR8      0x00001000  /* External interrupt 8               */
-#define UIC_EIR9      0x00000800  /* External interrupt 9               */
-#define UIC_CT2       0x00000400  /* GPT compare timer 2                */
-#define UIC_CT3       0x00000200  /* GPT compare timer 3                */
-#define UIC_CT4       0x00000100  /* GPT compare timer 4                */
-#define UIC_SRE       0x00000080  /* Serial ROM error                   */
-#define UIC_GPTDC     0x00000040  /* GPT decrementer pulse              */
-#define UIC_RSVD0     0x00000020  /* Reserved                           */
-#define UIC_EPCIPER   0x00000010  /* External PCI PERR                  */
-#define UIC_EIR0      0x00000008  /* External interrupt 0               */
-#define UIC_EWU0      0x00000004  /* Ethernet 0 wakeup                  */
-#define UIC_EIR1      0x00000002  /* External interrupt 1               */
-#define UIC_EWU1      0x00000001  /* Ethernet 1 wakeup                  */
-
-/* For compatibility with 405 code */
-#define UIC_MAL_SERR	UIC_MS
-#define UIC_MAL_TXDE	UIC_MTDE
-#define UIC_MAL_RXDE	UIC_MRDE
-#define UIC_ENET	UIC_ETH0
-
-#elif !defined(CONFIG_440SPE)
-#define UIC_MS		0x80000000	/* MAL SERR			    */
-#define UIC_MTDE	0x40000000	/* MAL TXDE			    */
-#define UIC_MRDE	0x20000000	/* MAL RXDE			    */
-#define UIC_DEUE	0x10000000	/* DDR SDRAM ECC uncorrectible error*/
-#define UIC_DECE	0x08000000	/* DDR SDRAM correctible error	    */
-#define UIC_EBCO	0x04000000	/* EBCO interrupt status	    */
-#define UIC_EBMI	0x02000000	/* EBMI interrupt status	    */
-#define UIC_OPB		0x01000000	/* OPB to PLB bridge interrupt stat */
-#define UIC_MSI3	0x00800000	/* PCI MSI level 3		    */
-#define UIC_MSI4	0x00400000	/* PCI MSI level 4		    */
-#define UIC_MSI5	0x00200000	/* PCI MSI level 5		    */
-#define UIC_MSI6	0x00100000	/* PCI MSI level 6		    */
-#define UIC_MSI7	0x00080000	/* PCI MSI level 7		    */
-#define UIC_MSI8	0x00040000	/* PCI MSI level 8		    */
-#define UIC_MSI9	0x00020000	/* PCI MSI level 9		    */
-#define UIC_MSI10	0x00010000	/* PCI MSI level 10		    */
-#define UIC_MSI11	0x00008000	/* PCI MSI level 11		    */
-#define UIC_PPMI	0x00004000	/* PPM interrupt status		    */
-#define UIC_EIR7	0x00002000	/* External interrupt 7		    */
-#define UIC_EIR8	0x00001000	/* External interrupt 8		    */
-#define UIC_EIR9	0x00000800	/* External interrupt 9		    */
-#define UIC_EIR10	0x00000400	/* External interrupt 10	    */
-#define UIC_EIR11	0x00000200	/* External interrupt 11	    */
-#define UIC_EIR12	0x00000100	/* External interrupt 12	    */
-#define UIC_SRE		0x00000080	/* Serial ROM error		    */
-#define UIC_RSVD2	0x00000040	/* Reserved			    */
-#define UIC_RSVD3	0x00000020	/* Reserved			    */
-#define UIC_PAE		0x00000010	/* PCI asynchronous error	    */
-#define UIC_ETH0	0x00000008	/* Ethernet 0			    */
-#define UIC_EWU0	0x00000004	/* Ethernet 0 wakeup		    */
-#define UIC_ETH1	0x00000002	/* Ethernet 1			    */
-#define UIC_EWU1	0x00000001	/* Ethernet 1 wakeup		    */
-#endif /* CONFIG_440SP */
-
-/* For compatibility with 405 code */
-#define UIC_MAL_SERR	UIC_MS
-#define UIC_MAL_TXDE	UIC_MTDE
-#define UIC_MAL_RXDE	UIC_MRDE
-#define UIC_ENET	UIC_ETH0
-
-/*---------------------------------------------------------------------------+
-|  Universal interrupt controller 2 interrupts (UIC2)
-+---------------------------------------------------------------------------*/
-#if defined(CONFIG_440GX)
-#define UIC_ETH2	0x80000000	/* Ethernet 2			    */
-#define UIC_EWU2	0x40000000	/* Ethernet 2 wakeup		    */
-#define UIC_ETH3	0x20000000	/* Ethernet 3			    */
-#define UIC_EWU3	0x10000000	/* Ethernet 3 wakeup		    */
-#define UIC_TAH0	0x08000000	/* TAH 0			    */
-#define UIC_TAH1	0x04000000	/* TAH 1			    */
-#define UIC_IMUOBFQ	0x02000000	/* IMU outbound free queue	    */
-#define UIC_IMUIBPQ	0x01000000	/* IMU inbound post queue	    */
-#define UIC_IMUIRQDB	0x00800000	/* IMU irq doorbell		    */
-#define UIC_IMUIBDB	0x00400000	/* IMU inbound doorbell		    */
-#define UIC_IMUMSG0	0x00200000	/* IMU inbound message 0	    */
-#define UIC_IMUMSG1	0x00100000	/* IMU inbound message 1	    */
-#define UIC_IMUTO	0x00080000	/* IMU timeout			    */
-#define UIC_MSI12	0x00040000	/* PCI MSI level 12		    */
-#define UIC_MSI13	0x00020000	/* PCI MSI level 13		    */
-#define UIC_MSI14	0x00010000	/* PCI MSI level 14		    */
-#define UIC_MSI15	0x00008000	/* PCI MSI level 15		    */
-#define UIC_EIR13	0x00004000	/* External interrupt 13	    */
-#define UIC_EIR14	0x00002000	/* External interrupt 14	    */
-#define UIC_EIR15	0x00001000	/* External interrupt 15	    */
-#define UIC_EIR16	0x00000800	/* External interrupt 16	    */
-#define UIC_EIR17	0x00000400	/* External interrupt 17	    */
-#define UIC_PCIVPD	0x00000200	/* PCI VPD			    */
-#define UIC_L2C		0x00000100	/* L2 Cache			    */
-#define UIC_ETH2PCS	0x00000080	/* Ethernet 2 PCS		    */
-#define UIC_ETH3PCS	0x00000040	/* Ethernet 3 PCS		    */
-#define UIC_RSVD26	0x00000020	/* Reserved			    */
-#define UIC_RSVD27	0x00000010	/* Reserved			    */
-#define UIC_RSVD28	0x00000008	/* Reserved			    */
-#define UIC_RSVD29	0x00000004	/* Reserved			    */
-#define UIC_RSVD30	0x00000002	/* Reserved			    */
-#define UIC_RSVD31	0x00000001	/* Reserved			    */
-
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
-
-#define UIC_TAH0	0x80000000	/* TAHOE 0			    */
-#define UIC_TAH1	0x40000000	/* TAHOE 1			    */
-#define UIC_EIR9	0x20000000	/* External interrupt 9		    */
-#define UIC_MS		0x10000000	/* MAL SERR			    */
-#define UIC_MTDE	0x08000000	/* MAL TXDE			    */
-#define UIC_MRDE	0x04000000	/* MAL RXDE			    */
-#define UIC_MTE		0x02000000	/* MAL TXEOB			    */
-#define UIC_MRE		0x01000000	/* MAL RXEOB			    */
-#define UIC_MCTX0	0x00800000	/* MAL interrupt coalescence TX0    */
-#define UIC_MCTX1	0x00400000	/* MAL interrupt coalescence TX1    */
-#define UIC_MCTX2	0x00200000	/* MAL interrupt coalescence TX2    */
-#define UIC_MCTX3	0x00100000	/* MAL interrupt coalescence TX3    */
-#define UIC_MCTR0	0x00080000	/* MAL interrupt coalescence TR0    */
-#define UIC_MCTR1	0x00040000	/* MAL interrupt coalescence TR1    */
-#define UIC_MCTR2	0x00020000	/* MAL interrupt coalescence TR2    */
-#define UIC_MCTR3	0x00010000	/* MAL interrupt coalescence TR3    */
-#define UIC_ETH0	0x00008000	/* Ethernet 0			    */
-#define UIC_ETH1	0x00004000	/* Ethernet 1			    */
-#define UIC_ETH2	0x00002000	/* Ethernet 2			    */
-#define UIC_ETH3	0x00001000	/* Ethernet 3			    */
-#define UIC_EWU0	0x00000800	/* Ethernet 0 wakeup		    */
-#define UIC_EWU1	0x00000400	/* Ethernet 1 wakeup		    */
-#define UIC_EWU2	0x00000200	/* Ethernet 2 wakeup		    */
-#define UIC_EWU3	0x00000100	/* Ethernet 3 wakeup		    */
-#define UIC_EIR10	0x00000080	/* External interrupt 10	    */
-#define UIC_EIR11	0x00000040	/* External interrupt 11	    */
-#define UIC_RSVD2	0x00000020	/* Reserved			    */
-#define UIC_PLB4XAHB	0x00000010	/* PLB4XAHB / AHBARB error	    */
-#define UIC_OTG		0x00000008	/* USB2.0 OTG			    */
-#define UIC_EHCI	0x00000004	/* USB2.0 Host EHCI		    */
-#define UIC_OHCI	0x00000002	/* USB2.0 Host OHCI		    */
-#define UIC_OHCISMI	0x00000001	/* USB2.0 Host OHCI SMI		    */
-
-#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* UIC2 */
-
-#define UIC_EIR5    0x80000000  /* External interrupt 5                 */
-#define UIC_EIR6    0x40000000  /* External interrupt 6                 */
-#define UIC_OPB     0x20000000  /* OPB to PLB bridge interrupt stat     */
-#define UIC_EIR2    0x10000000  /* External interrupt 2                 */
-#define UIC_EIR3    0x08000000  /* External interrupt 3                 */
-#define UIC_DDR2    0x04000000  /* DDR2 sdram                           */
-#define UIC_MCTX0   0x02000000  /* MAl intp coalescence TX0             */
-#define UIC_MCTX1   0x01000000  /* MAl intp coalescence TX1             */
-#define UIC_MCTR0   0x00800000  /* MAl intp coalescence TR0             */
-#define UIC_MCTR1   0x00400000  /* MAl intp coalescence TR1             */
-
-#endif	/* CONFIG_440GX */
-
-/*---------------------------------------------------------------------------+
-|  Universal interrupt controller Base 0 interrupts (UICB0)
-+---------------------------------------------------------------------------*/
-#if defined(CONFIG_440GX)
-#define UICB0_UIC0CI	0x80000000	/* UIC0 Critical Interrupt	    */
-#define UICB0_UIC0NCI	0x40000000	/* UIC0 Noncritical Interrupt	    */
-#define UICB0_UIC1CI	0x20000000	/* UIC1 Critical Interrupt	    */
-#define UICB0_UIC1NCI	0x10000000	/* UIC1 Noncritical Interrupt	    */
-#define UICB0_UIC2CI	0x08000000	/* UIC2 Critical Interrupt	    */
-#define UICB0_UIC2NCI	0x04000000	/* UIC2 Noncritical Interrupt	    */
-
-#define UICB0_ALL	(UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \
-			 UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI)
-
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-      defined(CONFIG_460SX)
-
-#define UICB0_UIC1NCI	0x00000002	/* UIC1 Noncritical Interrupt	    */
-#define UICB0_UIC1CI	0x00000001	/* UIC1 Critical Interrupt	    */
-#define UICB0_UIC2NCI	0x00200000	/* UIC2 Noncritical Interrupt	    */
-#define UICB0_UIC2CI	0x00100000	/* UIC2 Critical Interrupt	    */
-#define UICB0_UIC3NCI	0x00008000	/* UIC3 Noncritical Interrupt	    */
-#define UICB0_UIC3CI	0x00004000	/* UIC3 Critical Interrupt	    */
-
-#define UICB0_ALL	(UICB0_UIC1CI | UICB0_UIC1NCI | UICB0_UIC2CI | \
-			 UICB0_UIC2NCI | UICB0_UIC3CI | UICB0_UIC3NCI)
-
-#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-
-#define UICB0_UIC1CI	0x00000001	/* UIC1 Critical Interrupt	    */
-#define UICB0_UIC1NCI	0x00000002	/* UIC1 Noncritical Interrupt	    */
-#define UICB0_UIC2CI	0x00000004	/* UIC2 Critical Interrupt	    */
-#define UICB0_UIC2NCI	0x00000008	/* UIC2 Noncritical Interrupt	    */
-
-#define UICB0_ALL	(UICB0_UIC1CI | UICB0_UIC1NCI | \
-			 UICB0_UIC1CI | UICB0_UIC2NCI)
-
-#elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \
-    defined(CONFIG_440EP) || defined(CONFIG_440GR)
-
-#define UICB0_UIC1CI	0x00000001	/* UIC1 Critical Interrupt	    */
-#define UICB0_UIC1NCI	0x00000002	/* UIC1 Noncritical Interrupt	    */
-
-#define UICB0_ALL	(UICB0_UIC1CI | UICB0_UIC1NCI)
-
-#endif /* CONFIG_440GX */
-/*---------------------------------------------------------------------------+
-|  Universal interrupt controller interrupts
-+---------------------------------------------------------------------------*/
-#if defined(CONFIG_440SPE)
-/*#define UICB0_UIC0CI	0x80000000*/	/* UIC0 Critical Interrupt	    */
-/*#define UICB0_UIC0NCI	0x40000000*/	/* UIC0 Noncritical Interrupt	    */
-#define UICB0_UIC1CI	0x00000002	/* UIC1 Critical Interrupt	    */
-#define UICB0_UIC1NCI	0x00000001	/* UIC1 Noncritical Interrupt	    */
-#define UICB0_UIC2CI	0x00200000	/* UIC2 Critical Interrupt	    */
-#define UICB0_UIC2NCI	0x00100000	/* UIC2 Noncritical Interrupt	    */
-#define UICB0_UIC3CI	0x00008000	/* UIC3 Critical Interrupt	    */
-#define UICB0_UIC3NCI	0x00004000	/* UIC3 Noncritical Interrupt	    */
-
-#define UICB0_ALL		(UICB0_UIC1CI | UICB0_UIC1NCI | UICB0_UIC2CI | \
-						 UICB0_UIC2NCI | UICB0_UIC3CI | UICB0_UIC3NCI)
-/*---------------------------------------------------------------------------+
-|  Universal interrupt controller 0 interrupts (UIC0)
-+---------------------------------------------------------------------------*/
-#define UIC_U0		0x80000000	/* UART 0			    */
-#define UIC_U1		0x40000000	/* UART 1			    */
-#define UIC_IIC0	0x20000000	/* IIC				    */
-#define UIC_IIC1	0x10000000	/* IIC				    */
-#define UIC_PIM		0x08000000	/* PCI inbound message		    */
-#define UIC_PCRW	0x04000000	/* PCI command register write	    */
-#define UIC_PPM		0x02000000	/* PCI power management		    */
-#define UIC_PVPDA	0x01000000	/* PCIx 0 vpd access		    */
-#define UIC_MSI0	0x00800000	/* PCIx MSI level 0		    */
-#define UIC_EIR15	0x00400000	/* External intp 15		    */
-#define UIC_PEMSI0	0x00080000	/* PCIe MSI level 0		    */
-#define UIC_PEMSI1	0x00040000	/* PCIe MSI level 1		    */
-#define UIC_PEMSI2	0x00020000	/* PCIe MSI level 2		    */
-#define UIC_PEMSI3	0x00010000	/* PCIe MSI level 3		    */
-#define UIC_EIR14	0x00002000	/* External interrupt 14	    */
-#define UIC_D0CPFF	0x00001000	/* DMA0 cp fifo full		    */
-#define UIC_D0CSNS	0x00000800	/* DMA0 cs fifo needs service	    */
-#define UIC_D1CPFF	0x00000400	/* DMA1 cp fifo full		    */
-#define UIC_D1CSNS	0x00000200	/* DMA1 cs fifo needs service	    */
-#define UIC_I2OID	0x00000100	/* I2O inbound door bell	    */
-#define UIC_I2OLNE	0x00000080	/* I2O Inbound Post List FIFO Not Empty */
-#define UIC_I20R0LL	0x00000040	/* I2O Region 0 Low Latency PLB Write */
-#define UIC_I2OR1LL	0x00000020	/* I2O Region 1 Low Latency PLB Write */
-#define UIC_I20R0HB	0x00000010	/* I2O Region 0 High Bandwidth PLB Write */
-#define UIC_I2OR1HB	0x00000008	/* I2O Region 1 High Bandwidth PLB Write */
-#define UIC_CPTCNT	0x00000004	/* GPT Count Timer		    */
-/*---------------------------------------------------------------------------+
-|  Universal interrupt controller 1 interrupts (UIC1)
-+---------------------------------------------------------------------------*/
-#define UIC_EIR13	0x80000000	/* externei intp 13		    */
-#define UIC_MS		0x40000000	/* MAL SERR			    */
-#define UIC_MTDE	0x20000000	/* MAL TXDE			    */
-#define UIC_MRDE	0x10000000	/* MAL RXDE			    */
-#define UIC_DEUE	0x08000000	/* DDR SDRAM ECC correct/uncorrectable error */
-#define UIC_EBCO	0x04000000	/* EBCO interrupt status	    */
-#define UIC_MTE		0x02000000	/* MAL TXEOB			    */
-#define UIC_MRE		0x01000000	/* MAL RXEOB			    */
-#define UIC_MSI1	0x00800000	/* PCI MSI level 1		    */
-#define UIC_MSI2	0x00400000	/* PCI MSI level 2		    */
-#define UIC_MSI3	0x00200000	/* PCI MSI level 3		    */
-#define UIC_L2C		0x00100000	/* L2 cache			    */
-#define UIC_CT0		0x00080000	/* GPT compare timer 0		    */
-#define UIC_CT1		0x00040000	/* GPT compare timer 1		    */
-#define UIC_CT2		0x00020000	/* GPT compare timer 2		    */
-#define UIC_CT3		0x00010000	/* GPT compare timer 3		    */
-#define UIC_CT4		0x00008000	/* GPT compare timer 4		    */
-#define UIC_EIR12	0x00004000	/* External interrupt 12	    */
-#define UIC_EIR11	0x00002000	/* External interrupt 11	    */
-#define UIC_EIR10	0x00001000	/* External interrupt 10	    */
-#define UIC_EIR9	0x00000800	/* External interrupt 9		    */
-#define UIC_EIR8	0x00000400	/* External interrupt 8		    */
-#define UIC_DMAE	0x00000200	/* dma error			    */
-#define UIC_I2OE	0x00000100	/* i2o error			    */
-#define UIC_SRE		0x00000080	/* Serial ROM error		    */
-#define UIC_PCIXAE	0x00000040	/* Pcix0 async error		    */
-#define UIC_EIR7	0x00000020	/* External interrupt 7		    */
-#define UIC_EIR6	0x00000010	/* External interrupt 6		    */
-#define UIC_ETH0	0x00000008	/* Ethernet 0			    */
-#define UIC_EWU0	0x00000004	/* Ethernet 0 wakeup		    */
-#define UIC_ETH1	0x00000002	/* reserved			    */
-#define UIC_XOR		0x00000001	/* xor				    */
-
-/*---------------------------------------------------------------------------+
-|  Universal interrupt controller 2 interrupts (UIC2)
-+---------------------------------------------------------------------------*/
-#define UIC_PEOAL	0x80000000	/* PE0  AL			    */
-#define UIC_PEOVA	0x40000000	/* PE0  VPD access		    */
-#define UIC_PEOHRR	0x20000000	/* PE0 Host reset request rising    */
-#define UIC_PE0HRF	0x10000000	/* PE0 Host reset request falling   */
-#define UIC_PE0TCR	0x08000000	/* PE0 TCR			    */
-#define UIC_PE0BVCO	0x04000000	/* PE0 Busmaster VCO		    */
-#define UIC_PE0DCRE	0x02000000	/* PE0 DCR error		    */
-#define UIC_PE1AL	0x00800000	/* PE1  AL			    */
-#define UIC_PE1VA	0x00400000	/* PE1  VPD access		    */
-#define UIC_PE1HRR	0x00200000	/* PE1 Host reset request rising    */
-#define UIC_PE1HRF	0x00100000	/* PE1 Host reset request falling   */
-#define UIC_PE1TCR	0x00080000	/* PE1 TCR			    */
-#define UIC_PE1BVCO	0x00040000	/* PE1 Busmaster VCO		    */
-#define UIC_PE1DCRE	0x00020000	/* PE1 DCR error		    */
-#define UIC_PE2AL	0x00008000	/* PE2  AL			    */
-#define UIC_PE2VA	0x00004000	/* PE2  VPD access		    */
-#define UIC_PE2HRR	0x00002000	/* PE2 Host reset request rising    */
-#define UIC_PE2HRF	0x00001000	/* PE2 Host reset request falling   */
-#define UIC_PE2TCR	0x00000800	/* PE2 TCR			    */
-#define UIC_PE2BVCO	0x00000400	/* PE2 Busmaster VCO		    */
-#define UIC_PE2DCRE	0x00000200	/* PE2 DCR error		    */
-#define UIC_EIR5	0x00000080	/* External interrupt 5		    */
-#define UIC_EIR4	0x00000040	/* External interrupt 4		    */
-#define UIC_EIR3	0x00000020	/* External interrupt 3		    */
-#define UIC_EIR2	0x00000010	/* External interrupt 2		    */
-#define UIC_EIR1	0x00000008	/* External interrupt 1		    */
-#define UIC_EIR0	0x00000004	/* External interrupt 0		    */
-#endif /* CONFIG_440SPE */
-
 /*-----------------------------------------------------------------------------+
 |  SDR0 Bit Settings
 +-----------------------------------------------------------------------------*/