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| author | Markus Klotzbuecher <mk@denx.de> | 2007-05-29 16:37:57 +0200 |
|---|---|---|
| committer | Markus Klotzbuecher <mk@pollux.denx.de> | 2007-05-29 16:37:57 +0200 |
| commit | 51d8e813222fa3063d423220f6ff1146df58a471 (patch) | |
| tree | a4951077af841bd87a90854b7fb390d12e37b851 /include/ppc440.h | |
| parent | 3a619dd7bed03e8b4d22a3911f90fd12af5376c2 (diff) | |
| parent | 19bf91f9628f80a55d4f171df71041574882b3d6 (diff) | |
| download | u-boot-imx-51d8e813222fa3063d423220f6ff1146df58a471.zip u-boot-imx-51d8e813222fa3063d423220f6ff1146df58a471.tar.gz u-boot-imx-51d8e813222fa3063d423220f6ff1146df58a471.tar.bz2 | |
Merge git://www.denx.de/git/u-boot into 2007_05_15-testing
Diffstat (limited to 'include/ppc440.h')
| -rw-r--r-- | include/ppc440.h | 20 |
1 files changed, 17 insertions, 3 deletions
diff --git a/include/ppc440.h b/include/ppc440.h index bc1d7aa..07f75de 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -1425,9 +1425,6 @@ /*----------------------------------------------------------------------------+ | Clock / Power-on-reset DCR's. +----------------------------------------------------------------------------*/ -#define CPR0_CFGADDR 0x00C -#define CPR0_CFGDATA 0x00D - #define CPR0_CLKUPD 0x20 #define CPR0_CLKUPD_BSY_MASK 0x80000000 #define CPR0_CLKUPD_BSY_COMPLETED 0x00000000 @@ -3314,6 +3311,23 @@ #define mtsdr(reg, data) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } while (0) #define mfsdr(reg, data) do { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } while (0) +/* + * All 44x except 440GP have CPR registers (indirect DCR) + */ +#if !defined(CONFIG_440GP) +#define CPR0_CFGADDR 0x00C +#define CPR0_CFGDATA 0x00D + +#define mtcpr(reg, data) do { \ + mtdcr(CPR0_CFGADDR, reg); \ + mtdcr(CPR0_CFGDATA, data); \ + } while (0) + +#define mfcpr(reg, data) do { \ + mtdcr(CPR0_CFGADDR, reg); \ + data = mfdcr(CPR0_CFGDATA); \ + } while (0) +#endif #ifndef __ASSEMBLY__ |