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| author | Stefan Roese <sr@denx.de> | 2007-08-21 16:33:33 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-08-21 16:33:33 +0200 |
| commit | 93f798346033a1f6d22090b47abad4be88243b04 (patch) | |
| tree | 45b4d2a887a89572015de3234b04b419bfc11b44 /include/ppc405.h | |
| parent | 3ad63878737a5a2b1e60825bf0a7d601d7a695e7 (diff) | |
| parent | 3e66c078003607a7d1d214c15a5f262bc1b4032f (diff) | |
| download | u-boot-imx-93f798346033a1f6d22090b47abad4be88243b04.zip u-boot-imx-93f798346033a1f6d22090b47abad4be88243b04.tar.gz u-boot-imx-93f798346033a1f6d22090b47abad4be88243b04.tar.bz2 | |
Merge with /home/stefan/git/u-boot/u-boot-ppc4xx
Diffstat (limited to 'include/ppc405.h')
| -rw-r--r-- | include/ppc405.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/include/ppc405.h b/include/ppc405.h index 8e64731..0c7bf3e 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -541,6 +541,18 @@ #define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \ PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_3) +#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) +#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_1) +#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) /* * PLL Voltage Controlled Oscillator (VCO) definitions @@ -617,6 +629,8 @@ #define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */ #define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */ +#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ + #define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */ #define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */ #define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */ @@ -1226,6 +1240,8 @@ #define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data) #define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd) +#define mtsdram(reg, data) do { mtdcr(memcfga,reg);mtdcr(memcfgd,data); } while (0) +#define mfsdram(reg, data) do { mtdcr(memcfga,reg);data = mfdcr(memcfgd); } while (0) #ifndef __ASSEMBLY__ |