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authorStefan Roese <sr@denx.de>2007-06-04 08:17:29 +0200
committerStefan Roese <sr@denx.de>2007-06-04 08:17:29 +0200
commitd7d5204ce2e0985ff2dfdf3a6b5b6a526cdb1c1e (patch)
treec71da8013140d7bd5024dcde5f9cd075d4c012e2 /include/ppc405.h
parent7ebb4479b07ff294eb4d76e420753a0349f7c93b (diff)
parent19bf91f9628f80a55d4f171df71041574882b3d6 (diff)
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Merge with git://www.denx.de/git/u-boot.git
Diffstat (limited to 'include/ppc405.h')
-rw-r--r--include/ppc405.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/include/ppc405.h b/include/ppc405.h
index a2503a9..fffae4d 100644
--- a/include/ppc405.h
+++ b/include/ppc405.h
@@ -547,8 +547,8 @@
#define sdrcfga (SDR_DCR_BASE+0x0) /* ADDR */
#define sdrcfgd (SDR_DCR_BASE+0x1) /* Data */
-#define mtsdr(reg, data) mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data)
-#define mfsdr(reg, data) mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd)
+#define mtsdr(reg, data) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } while (0)
+#define mfsdr(reg, data) do { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } while (0)
#define sdrnand0 0x4000
#define sdrultra0 0x4040
@@ -593,8 +593,8 @@
/*
* Macro for accessing the indirect CPR register
*/
-#define mtcpr(reg, data) mtdcr(cprcfga,reg);mtdcr(cprcfgd,data)
-#define mfcpr(reg, data) mtdcr(cprcfga,reg);data = mfdcr(cprcfgd)
+#define mtcpr(reg, data) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,data); } while (0)
+#define mfcpr(reg, data) do { mtdcr(cprcfga,reg);data = mfdcr(cprcfgd); } while (0)
#define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */
#define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */