ppc4xx: Consolidate PPC4xx UIC defines

This 2nd patch now removes all UIC mask bit definition. They should be
generated from the vectors by using the UIC_MASK() macro from now on.
This way only the vectors need to get defined for new PPC's.

Also only the really used interrupt vectors are now defined. This makes
definitions for new PPC versions easier and less error prone.

Another part of this patch is that the 4xx emac driver got a little
cleanup, since now the usage of the interrupts is clearer.

Signed-off-by: Stefan Roese <sr@denx.de>

1 files changed, 0 insertions, 247 deletions

diff --git a/include/ppc405.h b/include/ppc405.h
index fee4ee5..f19b67f 100644
--- a/include/ppc405.h
+++ b/include/ppc405.h
@@ -119,253 +119,6 @@
 #define dmasgc	(DMA_DCR_BASE+0x23)  /* DMA scatter/gather command register  */
 #define dmaadr	(DMA_DCR_BASE+0x24)  /* DMA address decode register	     */
 
-/******************************************************************************
- * Universal interrupt controller
- ******************************************************************************/
-#define UIC_SR	0x0			/* UIC status			   */
-#define UIC_ER	0x2			/* UIC enable			   */
-#define UIC_CR	0x3			/* UIC critical			   */
-#define UIC_PR	0x4			/* UIC polarity			   */
-#define UIC_TR	0x5			/* UIC triggering		   */
-#define UIC_MSR 0x6			/* UIC masked status		   */
-#define UIC_VR	0x7			/* UIC vector			   */
-#define UIC_VCR 0x8			/* UIC vector configuration	   */
-
-#define UIC_DCR_BASE 0xc0
-#define UIC0_DCR_BASE UIC_DCR_BASE
-#define uicsr	     (UIC_DCR_BASE+0x0)  /* UIC status			     */
-#define uicsrs	     (UIC_DCR_BASE+0x1)  /* UIC status set		     */
-#define uicer	     (UIC_DCR_BASE+0x2)  /* UIC enable			     */
-#define uiccr	     (UIC_DCR_BASE+0x3)  /* UIC critical		     */
-#define uicpr	     (UIC_DCR_BASE+0x4)  /* UIC polarity		     */
-#define uictr	     (UIC_DCR_BASE+0x5)  /* UIC triggering		     */
-#define uicmsr	     (UIC_DCR_BASE+0x6)  /* UIC masked status		     */
-#define uicvr	     (UIC_DCR_BASE+0x7)  /* UIC vector			     */
-#define uicvcr	     (UIC_DCR_BASE+0x8)  /* UIC vector configuration	     */
-
-#if defined(CONFIG_405EX)
-#define uic0sr	      uicsr		/* UIC status		 */
-#define uic0srs       uicsrs		/* UIC status set	 */
-#define uic0er	      uicer		/* UIC enable		 */
-#define uic0cr	      uiccr		/* UIC critical		 */
-#define uic0pr	      uicpr		/* UIC polarity		 */
-#define uic0tr	      uictr		/* UIC triggering	 */
-#define uic0msr       uicmsr		/* UIC masked status	 */
-#define uic0vr	      uicvr		/* UIC vector		 */
-#define uic0vcr       uicvcr		/* UIC vector configuration*/
-
-#define UIC_DCR_BASE1 0xd0
-#define UIC1_DCR_BASE 0xd0
-#define uic1sr	      (UIC_DCR_BASE1+0x0)  /* UIC status	    */
-#define uic1srs       (UIC_DCR_BASE1+0x1)  /* UIC status set	    */
-#define uic1er	      (UIC_DCR_BASE1+0x2)  /* UIC enable	    */
-#define uic1cr	      (UIC_DCR_BASE1+0x3)  /* UIC critical	    */
-#define uic1pr	      (UIC_DCR_BASE1+0x4)  /* UIC polarity	    */
-#define uic1tr	      (UIC_DCR_BASE1+0x5)  /* UIC triggering	    */
-#define uic1msr       (UIC_DCR_BASE1+0x6)  /* UIC masked status     */
-#define uic1vr	      (UIC_DCR_BASE1+0x7)  /* UIC vector	    */
-#define uic1vcr       (UIC_DCR_BASE1+0x8)  /* UIC vector configuration*/
-
-#define UIC_DCR_BASE2 0xe0
-#define UIC2_DCR_BASE 0xe0
-#define uic2sr	      (UIC_DCR_BASE2+0x0)  /* UIC status	    */
-#define uic2srs       (UIC_DCR_BASE2+0x1)  /* UIC status set	    */
-#define uic2er	      (UIC_DCR_BASE2+0x2)  /* UIC enable	    */
-#define uic2cr	      (UIC_DCR_BASE2+0x3)  /* UIC critical	    */
-#define uic2pr	      (UIC_DCR_BASE2+0x4)  /* UIC polarity	    */
-#define uic2tr	      (UIC_DCR_BASE2+0x5)  /* UIC triggering	    */
-#define uic2msr       (UIC_DCR_BASE2+0x6)  /* UIC masked status     */
-#define uic2vr	      (UIC_DCR_BASE2+0x7)  /* UIC vector	    */
-#define uic2vcr       (UIC_DCR_BASE2+0x8)  /* UIC vector configuration*/
-#endif
-
-/*-----------------------------------------------------------------------------+
-|  Universal interrupt controller interrupts
-+-----------------------------------------------------------------------------*/
-#if defined(CONFIG_405EZ)
-#define UIC_DMA0	0x80000000	/* DMA chan. 0			*/
-#define UIC_DMA1	0x40000000	/* DMA chan. 1			*/
-#define UIC_DMA2	0x20000000	/* DMA chan. 2			*/
-#define UIC_DMA3	0x10000000	/* DMA chan. 3			*/
-#define UIC_1588	0x08000000	/* IEEE 1588 network synchronization */
-#define UIC_UART0	0x04000000	/* UART 0			*/
-#define UIC_UART1	0x02000000	/* UART 1			*/
-#define UIC_CAN0	0x01000000	/* CAN 0			*/
-#define UIC_CAN1	0x00800000	/* CAN 1			*/
-#define UIC_SPI		0x00400000	/* SPI				*/
-#define UIC_IIC		0x00200000	/* IIC				*/
-#define UIC_CHT0	0x00100000	/* Chameleon timer high pri interrupt */
-#define UIC_CHT1	0x00080000	/* Chameleon timer high pri interrupt */
-#define UIC_USBH1	0x00040000	/* USB Host 1			*/
-#define UIC_USBH2	0x00020000	/* USB Host 2			*/
-#define UIC_USBDEV	0x00010000	/* USB Device			*/
-#define UIC_ENET	0x00008000	/* Ethernet interrupt status	*/
-#define UIC_ENET1	0x00008000	/* dummy define			*/
-#define UIC_EMAC_WAKE	0x00004000	/* EMAC wake up			*/
-
-#define UIC_MADMAL	0x00002000	/* Logical OR of following MadMAL int */
-#define UIC_MAL_SERR	0x00002000	/*   MAL SERR			*/
-#define UIC_MAL_TXDE	0x00002000	/*   MAL TXDE			*/
-#define UIC_MAL_RXDE	0x00002000	/*   MAL RXDE			*/
-
-#define UIC_MAL_TXEOB	0x00001000	/* MAL TXEOB			*/
-#define UIC_MAL_TXEOB1	0x00000800	/* MAL TXEOB1			*/
-#define UIC_MAL_RXEOB	0x00000400	/* MAL RXEOB			*/
-#define UIC_NAND	0x00000200	/* NAND Flash controller	*/
-#define UIC_ADC		0x00000100	/* ADC				*/
-#define UIC_DAC		0x00000080	/* DAC				*/
-#define UIC_OPB2PLB	0x00000040	/* OPB to PLB bridge interrupt	*/
-#define UIC_RESERVED0	0x00000020	/* Reserved			*/
-#define UIC_EXT0	0x00000010	/* External  interrupt 0	*/
-#define UIC_EXT1	0x00000008	/* External  interrupt 1	*/
-#define UIC_EXT2	0x00000004	/* External  interrupt 2	*/
-#define UIC_EXT3	0x00000002	/* External  interrupt 3	*/
-#define UIC_EXT4	0x00000001	/* External  interrupt 4	*/
-
-#elif defined(CONFIG_405EX)
-
-/* UIC 0 */
-#define UIC_U0			0x80000000	/* */
-#define UIC_U1			0x40000000	/* */
-#define UIC_IIC0		0x20000000	/* */
-#define UIC_PKA			0x10000000	/* */
-#define UIC_TRNG		0x08000000	/* */
-#define UIC_EBM			0x04000000	/* */
-#define UIC_BGI			0x02000000	/* */
-#define UIC_IIC1		0x01000000	/* */
-#define UIC_SPI			0x00800000	/* */
-#define UIC_EIRQ0		0x00400000	/**/
-#define UIC_MTE			0x00200000	/*MAL Tx EOB */
-#define UIC_MRE			0x00100000	/*MAL Rx EOB */
-#define UIC_DMA0		0x00080000	/* */
-#define UIC_DMA1		0x00040000	/* */
-#define UIC_DMA2		0x00020000	/* */
-#define UIC_DMA3		0x00010000	/* */
-#define UIC_PCIE0AL		0x00008000	/* */
-#define UIC_PCIE0VPD		0x00004000	/* */
-#define UIC_RPCIE0HRST		0x00002000	/* */
-#define UIC_FPCIE0HRST		0x00001000	/* */
-#define UIC_PCIE0TCR		0x00000800	/* */
-#define UIC_PCIEMSI0		0x00000400	/* */
-#define UIC_PCIEMSI1		0x00000200	/* */
-#define UIC_SECURITY		0x00000100	/* */
-#define UIC_ENET		0x00000080	/* */
-#define UIC_ENET1		0x00000040	/* */
-#define UIC_PCIEMSI2		0x00000020	/* */
-#define UIC_EIRQ4		0x00000010	/**/
-#define UICB0_UIC2NCI		0x00000008	/* */
-#define UICB0_UIC2CI		0x00000004	/* */
-#define UICB0_UIC1NCI		0x00000002	/* */
-#define UICB0_UIC1CI		0x00000001	/* */
-
-#define UICB0_ALL		(UICB0_UIC1CI | UICB0_UIC1NCI | \
-				 UICB0_UIC1CI | UICB0_UIC2NCI)
-
-#define UIC_MAL_TXEOB		UIC_MTE/* MAL TXEOB			     */
-#define UIC_MAL_RXEOB		UIC_MRE/* MAL RXEOB			     */
-/* UIC 1 */
-#define UIC_MS			0x80000000	/* MAL SERR */
-#define UIC_MTDE		0x40000000	/* MAL TXDE */
-#define UIC_MRDE		0x20000000	/* MAL RXDE */
-#define UIC_PCIE0BMVC0		0x10000000	/* */
-#define UIC_PCIE0DCRERR		0x08000000	/* */
-#define UIC_EBC			0x04000000	/* */
-#define UIC_NDFC		0x02000000	/* */
-#define UIC_PCEI1DCRERR		0x01000000	/* */
-#define UIC_GPTCMPT8		0x00800000	/* */
-#define UIC_GPTCMPT9		0x00400000	/* */
-#define UIC_PCIE1AL		0x00200000	/* */
-#define UIC_PCIE1VPD		0x00100000	/* */
-#define UIC_RPCE1HRST		0x00080000	/* */
-#define UIC_FPCE1HRST		0x00040000	/* */
-#define UIC_PCIE1TCR		0x00020000	/* */
-#define UIC_PCIE1VC0		0x00010000	/* */
-#define UIC_GPTCMPT3		0x00008000	/* */
-#define UIC_GPTCMPT4		0x00004000	/* */
-#define UIC_EIRQ7		0x00002000	/* */
-#define UIC_EIRQ8		0x00001000	/* */
-#define UIC_EIRQ9		0x00000800	/* */
-#define UIC_GPTCMP5		0x00000400	/* */
-#define UIC_GPTCMP6		0x00000200	/* */
-#define UIC_GPTCMP7		0x00000100	/* */
-#define UIC_SROM		0x00000080	/* SERIAL ROM*/
-#define UIC_GPTDECPULS		0x00000040	/* GPT Decrement pulse*/
-#define UIC_EIRQ2		0x00000020	/* */
-#define UIC_EIRQ5		0x00000010	/* */
-#define UIC_EIRQ6		0x00000008	/* */
-#define UIC_EMAC0WAKE		0x00000004	/* */
-#define UIC_EIRQ1		0x00000002	/* */
-#define UIC_EMAC1WAKE		0x00000001	/* */
-#define UIC_MAL_SERR		UIC_MS		/* MAL SERR	*/
-#define UIC_MAL_TXDE		UIC_MTDE		/* MAL TXDE	*/
-#define UIC_MAL_RXDE		UIC_MRDE		/* MAL RXDE	*/
-/* UIC 2 */
-#define UIC_PCIE0INTA		0x80000000	/* PCIE0 INTA*/
-#define UIC_PCIE0INTB		0x40000000	/* PCIE0 INTB*/
-#define UIC_PCIE0INTC		0x20000000	/* PCIE0 INTC*/
-#define UIC_PCIE0INTD		0x10000000	/* PCIE0 INTD*/
-#define UIC_EIRQ3		0x08000000	/* External IRQ 3*/
-#define UIC_DDRMCUE		0x04000000	/* */
-#define UIC_DDRMCCE		0x02000000	/* */
-#define UIC_MALINTCOATX0	0x01000000	/* Interrupt coalecence TX0*/
-#define UIC_MALINTCOATX1	0x00800000	/* Interrupt coalecence TX1*/
-#define UIC_MALINTCOARX0	0x00400000	/* Interrupt coalecence RX0*/
-#define UIC_MALINTCOARX1	0x00200000	/* Interrupt coalecence RX1*/
-#define UIC_PCIE1INTA		0x00100000	/* PCIE0 INTA*/
-#define UIC_PCIE1INTB		0x00080000	/* PCIE0 INTB*/
-#define UIC_PCIE1INTC		0x00040000	/* PCIE0 INTC*/
-#define UIC_PCIE1INTD		0x00020000	/* PCIE0 INTD*/
-#define UIC_RPCIEMSI2		0x00010000	/* MSI level 2 Note this looks same as uic0-26*/
-#define UIC_PCIEMSI3		0x00008000	/* MSI level 2*/
-#define UIC_PCIEMSI4		0x00004000	/* MSI level 2*/
-#define UIC_PCIEMSI5		0x00002000	/* MSI level 2*/
-#define UIC_PCIEMSI6		0x00001000	/* MSI level 2*/
-#define UIC_PCIEMSI7		0x00000800	/* MSI level 2*/
-#define UIC_PCIEMSI8		0x00000400	/* MSI level 2*/
-#define UIC_PCIEMSI9		0x00000200	/* MSI level 2*/
-#define UIC_PCIEMSI10		0x00000100	/* MSI level 2*/
-#define UIC_PCIEMSI11		0x00000080	/* MSI level 2*/
-#define UIC_PCIEMSI12		0x00000040	/* MSI level 2*/
-#define UIC_PCIEMSI13		0x00000020	/* MSI level 2*/
-#define UIC_PCIEMSI14		0x00000010	/* MSI level 2*/
-#define UIC_PCIEMSI15		0x00000008	/* MSI level 2*/
-#define UIC_PLB4XAHB		0x00000004	/* PLBxAHB bridge*/
-#define UIC_USBWAKE		0x00000002	/* USB wakup*/
-#define UIC_USBOTG		0x00000001	/*  USB OTG*/
-#define UIC_ETH0	UIC_ENET
-#define UIC_ETH1	UIC_ENET1
-
-#else	/* !defined(CONFIG_405EZ) */
-
-#define UIC_UART0     0x80000000      /* UART 0				    */
-#define UIC_UART1     0x40000000      /* UART 1				    */
-#define UIC_IIC       0x20000000      /* IIC				    */
-#define UIC_EXT_MAST  0x10000000      /* External Master		    */
-#define UIC_PCI       0x08000000      /* PCI write to command reg	    */
-#define UIC_DMA0      0x04000000      /* DMA chan. 0			    */
-#define UIC_DMA1      0x02000000      /* DMA chan. 1			    */
-#define UIC_DMA2      0x01000000      /* DMA chan. 2			    */
-#define UIC_DMA3      0x00800000      /* DMA chan. 3			    */
-#define UIC_EMAC_WAKE 0x00400000      /* EMAC wake up			    */
-#define UIC_MAL_SERR  0x00200000      /* MAL SERR			    */
-#define UIC_MAL_TXEOB 0x00100000      /* MAL TXEOB			    */
-#define UIC_MAL_RXEOB 0x00080000      /* MAL RXEOB			    */
-#define UIC_MAL_TXDE  0x00040000      /* MAL TXDE			    */
-#define UIC_MAL_RXDE  0x00020000      /* MAL RXDE			    */
-#define UIC_ENET      0x00010000      /* Ethernet0			    */
-#define UIC_ENET1     0x00004000      /* Ethernet1 on 405EP		    */
-#define UIC_ECC_CE    0x00004000      /* ECC Correctable Error on 405GP     */
-#define UIC_EXT_PCI_SERR 0x00008000   /* External PCI SERR#		    */
-#define UIC_PCI_PM    0x00002000      /* PCI Power Management		    */
-#define UIC_EXT0      0x00000040      /* External  interrupt 0		    */
-#define UIC_EXT1      0x00000020      /* External  interrupt 1		    */
-#define UIC_EXT2      0x00000010      /* External  interrupt 2		    */
-#define UIC_EXT3      0x00000008      /* External  interrupt 3		    */
-#define UIC_EXT4      0x00000004      /* External  interrupt 4		    */
-#define UIC_EXT5      0x00000002      /* External  interrupt 5		    */
-#define UIC_EXT6      0x00000001      /* External  interrupt 6		    */
-#endif	/* defined(CONFIG_405EZ) */
-
 #ifndef CONFIG_405EP
 /******************************************************************************
  * Decompression Controller